JP4848375B2 - バス・アクセス取り消しを伴うデータ処理システム - Google Patents

バス・アクセス取り消しを伴うデータ処理システム Download PDF

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Publication number
JP4848375B2
JP4848375B2 JP2007534609A JP2007534609A JP4848375B2 JP 4848375 B2 JP4848375 B2 JP 4848375B2 JP 2007534609 A JP2007534609 A JP 2007534609A JP 2007534609 A JP2007534609 A JP 2007534609A JP 4848375 B2 JP4848375 B2 JP 4848375B2
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access
access request
master
revocation
request
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JP2007534609A
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Japanese (ja)
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JP2008515090A (ja
JP2008515090A5 (enExample
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シー． モイヤー、ウィリアム
ダブリュ． マードック、ブレット
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NXP USA Inc
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NXP USA Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP2007534609A 2004-09-30 2005-09-01 バス・アクセス取り消しを伴うデータ処理システム Expired - Fee Related JP4848375B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/955,558 2004-09-30
US10/955,558 US7340542B2 (en) 2004-09-30 2004-09-30 Data processing system with bus access retraction
PCT/US2005/031114 WO2006039039A2 (en) 2004-09-30 2005-09-01 Data processing system with bus access retraction

Publications (3)

Publication Number Publication Date
JP2008515090A JP2008515090A (ja) 2008-05-08
JP2008515090A5 JP2008515090A5 (enExample) 2008-08-14
JP4848375B2 true JP4848375B2 (ja) 2011-12-28

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ID=36100534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007534609A Expired - Fee Related JP4848375B2 (ja) 2004-09-30 2005-09-01 バス・アクセス取り消しを伴うデータ処理システム

Country Status (6)

Country Link
US (1) US7340542B2 (enExample)
EP (1) EP1810158A2 (enExample)
JP (1) JP4848375B2 (enExample)
KR (1) KR20070058561A (enExample)
CN (1) CN100578475C (enExample)
WO (1) WO2006039039A2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100725417B1 (ko) * 2006-02-22 2007-06-07 삼성전자주식회사 우선 순위에 따른 플래시 메모리의 연산 처리 장치 및 방법
US20080040591A1 (en) * 2006-08-11 2008-02-14 Moyer William C Method for determining branch target buffer (btb) allocation for branch instructions
US20080040590A1 (en) * 2006-08-11 2008-02-14 Lea Hwang Lee Selective branch target buffer (btb) allocaiton
KR100951126B1 (ko) * 2008-02-18 2010-04-07 인하대학교 산학협력단 버스 중재 방법 및 장치
US8667226B2 (en) 2008-03-24 2014-03-04 Freescale Semiconductor, Inc. Selective interconnect transaction control for cache coherency maintenance
KR100973419B1 (ko) * 2008-06-11 2010-07-30 인하대학교 산학협력단 버스 중재 방법 및 장치
US8370551B2 (en) * 2010-01-08 2013-02-05 International Business Machines Corporation Arbitration in crossbar interconnect for low latency
US8397006B2 (en) * 2010-01-28 2013-03-12 Freescale Semiconductor, Inc. Arbitration scheme for accessing a shared resource
CN102207919A (zh) * 2010-03-30 2011-10-05 国际商业机器公司 加速数据传输的处理单元、芯片、计算设备和方法
JP2014023094A (ja) * 2012-07-23 2014-02-03 Fujitsu Ltd パケットスイッチ、伝送装置及びパケット伝送方法
CN112241390B (zh) * 2020-10-22 2022-08-30 上海兆芯集成电路有限公司 主机互连装置及其方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
JPH06139188A (ja) * 1992-10-30 1994-05-20 Fujitsu Ltd バス制御装置及び方法
JP2002041445A (ja) * 2000-05-19 2002-02-08 Matsushita Electric Ind Co Ltd 高性能ｄｍａコントローラ
JP2002063130A (ja) * 2000-08-23 2002-02-28 Nec Corp バス調停システム
JP2005025670A (ja) * 2003-07-02 2005-01-27 Matsushita Electric Ind Co Ltd バス制御システム、バスマスタ及びバスアービタ
JP2005158035A (ja) * 2003-11-05 2005-06-16 Matsushita Electric Ind Co Ltd 調停回路及びこれに備える機能処理回路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4620278A (en) * 1983-08-29 1986-10-28 Sperry Corporation Distributed bus arbitration according each bus user the ability to inhibit all new requests to arbitrate the bus, or to cancel its own pending request, and according the highest priority user the ability to stop the bus
KR940002905B1 (en) * 1989-12-15 1994-04-07 Ibm Apparatus for conditioning priority arbitration in buffered direct memory addressing
US20020144054A1 (en) * 2001-03-30 2002-10-03 Fanning Blaise B. Prefetch canceling based on most recent accesses

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
JPH06139188A (ja) * 1992-10-30 1994-05-20 Fujitsu Ltd バス制御装置及び方法
JP2002041445A (ja) * 2000-05-19 2002-02-08 Matsushita Electric Ind Co Ltd 高性能ｄｍａコントローラ
JP2002063130A (ja) * 2000-08-23 2002-02-28 Nec Corp バス調停システム
JP2005025670A (ja) * 2003-07-02 2005-01-27 Matsushita Electric Ind Co Ltd バス制御システム、バスマスタ及びバスアービタ
JP2005158035A (ja) * 2003-11-05 2005-06-16 Matsushita Electric Ind Co Ltd 調停回路及びこれに備える機能処理回路

Also Published As

Publication number Publication date
JP2008515090A (ja) 2008-05-08
KR20070058561A (ko) 2007-06-08
CN101027656A (zh) 2007-08-29
CN100578475C (zh) 2010-01-06
US7340542B2 (en) 2008-03-04
EP1810158A2 (en) 2007-07-25
US20060069839A1 (en) 2006-03-30
WO2006039039A2 (en) 2006-04-13
WO2006039039A3 (en) 2007-04-05

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