CN112241390B - 主机互连装置及其方法 - Google Patents
主机互连装置及其方法 Download PDFInfo
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- CN112241390B CN112241390B CN202011140714.4A CN202011140714A CN112241390B CN 112241390 B CN112241390 B CN 112241390B CN 202011140714 A CN202011140714 A CN 202011140714A CN 112241390 B CN112241390 B CN 112241390B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
Claims (21)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202011140714.4A CN112241390B (zh) | 2020-10-22 | 2020-10-22 | 主机互连装置及其方法 |
US17/087,675 US11188491B1 (en) | 2020-10-22 | 2020-11-03 | Host interconnection device and method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202011140714.4A CN112241390B (zh) | 2020-10-22 | 2020-10-22 | 主机互连装置及其方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN112241390A CN112241390A (zh) | 2021-01-19 |
CN112241390B true CN112241390B (zh) | 2022-08-30 |
Family
ID=74169859
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN202011140714.4A Active CN112241390B (zh) | 2020-10-22 | 2020-10-22 | 主机互连装置及其方法 |
Country Status (2)
Country | Link |
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US (1) | US11188491B1 (zh) |
CN (1) | CN112241390B (zh) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101027656A (zh) * | 2004-09-30 | 2007-08-29 | 飞思卡尔半导体公司 | 具备总线存取收回的数据处理系统 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5704058A (en) * | 1995-04-21 | 1997-12-30 | Derrick; John E. | Cache bus snoop protocol for optimized multiprocessor computer system |
US6338121B1 (en) * | 1999-05-20 | 2002-01-08 | International Business Machines Corporation | Data source arbitration in a multiprocessor system |
US6615323B1 (en) * | 1999-09-02 | 2003-09-02 | Thomas Albert Petersen | Optimizing pipelined snoop processing |
US7139860B2 (en) * | 2002-07-29 | 2006-11-21 | Freescale Semiconductor Inc. | On chip network with independent logical and physical layers |
US7895431B2 (en) * | 2004-09-10 | 2011-02-22 | Cavium Networks, Inc. | Packet queuing, scheduling and ordering |
US8805949B2 (en) * | 2008-01-16 | 2014-08-12 | Netapp, Inc. | System and method for populating a cache using behavioral adaptive policies |
US8458399B2 (en) * | 2010-11-17 | 2013-06-04 | Lsi Corporation | Methods and structure for determining cache size in a storage system |
WO2012135221A1 (en) * | 2011-03-28 | 2012-10-04 | Citrix Systems, Inc. | Systems and methods for tracking application layer flow via a multi-connection intermediary device |
US8751746B2 (en) * | 2011-12-15 | 2014-06-10 | Apple Inc. | QoS management in the L2 cache |
CN102866980B (zh) * | 2012-07-31 | 2015-02-25 | 中国人民解放军国防科学技术大学 | 用于多核微处理器片上互连网络的网络通信胞元 |
US9047198B2 (en) * | 2012-11-29 | 2015-06-02 | Apple Inc. | Prefetching across page boundaries in hierarchically cached processors |
US9075952B2 (en) * | 2013-01-17 | 2015-07-07 | Intel Corporation | Controlling bandwidth allocations in a system on a chip (SoC) |
CN104599227B (zh) * | 2013-10-30 | 2017-09-22 | 南京理工大学 | 用于高速ccd数据存储的ddr3仲裁控制器及方法 |
CN105511838B (zh) * | 2014-09-29 | 2018-06-29 | 上海兆芯集成电路有限公司 | 处理器及其执行方法 |
US10042782B2 (en) * | 2015-06-02 | 2018-08-07 | ALTR Solutions, Inc. | Immutable datastore for low-latency reading and writing of large data sets |
GB2548845B (en) * | 2016-03-29 | 2019-11-27 | Imagination Tech Ltd | Handling memory requests |
US10025718B1 (en) * | 2016-06-28 | 2018-07-17 | Amazon Technologies, Inc. | Modifying provisioned throughput capacity for data stores according to cache performance |
GB2562520A (en) * | 2017-05-17 | 2018-11-21 | John Hamlin Derrick | Digital processing connectivity |
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2020
- 2020-10-22 CN CN202011140714.4A patent/CN112241390B/zh active Active
- 2020-11-03 US US17/087,675 patent/US11188491B1/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101027656A (zh) * | 2004-09-30 | 2007-08-29 | 飞思卡尔半导体公司 | 具备总线存取收回的数据处理系统 |
Non-Patent Citations (1)
Title |
---|
网络空间安全大数据实时计算平台关键技术研究;姚欣;《中国优秀硕士学位论文全文数据库 信息科技》;20170415;1-68 * |
Also Published As
Publication number | Publication date |
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US11188491B1 (en) | 2021-11-30 |
CN112241390A (zh) | 2021-01-19 |
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Effective date of registration: 20221123 Address after: 710075 305, Floor 3, Building B, Xi'an Tengfei Innovation Center, No. 38, Gaoxin 6th Road, High tech Zone, Xi'an City, Shaanxi Province Patentee after: Xi'an Zhaoxin Integrated Circuit Co.,Ltd. Patentee after: VIA ALLIANCE SEMICONDUCTOR Co.,Ltd. Address before: Room 301, 2537 Jinke Road, Zhangjiang hi tech park, Shanghai 201203 Patentee before: VIA ALLIANCE SEMICONDUCTOR Co.,Ltd. |
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Address after: 710075 305, Floor 3, Building B, Xi'an Tengfei Innovation Center, No. 38, Gaoxin 6th Road, High tech Zone, Xi'an City, Shaanxi Province Patentee after: Xi'an Zhaoxin Integrated Circuit Co.,Ltd. Patentee after: Shanghai Zhaoxin Semiconductor Co.,Ltd. Address before: 710075 305, Floor 3, Building B, Xi'an Tengfei Innovation Center, No. 38, Gaoxin 6th Road, High tech Zone, Xi'an City, Shaanxi Province Patentee before: Xi'an Zhaoxin Integrated Circuit Co.,Ltd. Patentee before: VIA ALLIANCE SEMICONDUCTOR Co.,Ltd. |