JP4811928B2 - Pachinko machine - Google Patents

Description

  The present invention relates to a pachinko machine provided with a RAM clear switch for supplying a RAM clear signal to a main control circuit section on a main control board.

  In the main control board that controls the game of the pachinko machine, if it is determined that the content of the RAM built in the MPU (main control circuit unit) provided on the main control board is destroyed, for example, When the clerk or the like presses the RAM clear switch at the time of turning on, a RAM clear signal is input to the MPU, and the MPU executes a RAM clear process (see, for example, Patent Document 1).

  In the pachinko machine described in Patent Document 1, the main control board is housed in a main control board case that is difficult to open and close for protection against fraud, and the RAM clear switch and its peripheral wiring are also housed in the main control board case. This makes it difficult for an unauthorized person to illegally access the RAM clear switch and its surroundings.

  As described in Patent Document 1, the RAM clear switch is provided on the main control board because the RAM clear switch is more effective for preventing fraud than the power supply terminal board or the like. ing.

  By the way, the operating power supply of the RAM clear switch provided on the main control board uses DC 5V. Conventionally, DC + 5V is an operating power supply for the MPU and other logic circuits, and therefore is generated by a regulator disposed on the main control board based on DC + 12V supplied from outside the main control board. ing. For this reason, conventionally, as shown in FIG. 7, + 5V generated by the regulator is used as an operating power source of the MPU and an operating power source of the RAM clear switch.

JP 2003-164594 A (see paragraph 0049, FIG. 5)

  The RAM clear switch is a push button type switch. If operation is required, an operator such as an attendant operates the pachinko machine with the RAM clear switch turned on. However, when the RAM clear switch is pressed, it is impossible to deny the possibility that the operator will accidentally come into contact with the conductive part in a state of being charged with static electricity. There was a risk of getting into the MPU and destroying the MPU (see FIG. 7).

  Therefore, an object of the present invention is to provide a pachinko machine in which countermeasures against static electricity are surely taken so that static noise does not enter the main control device from a RAM clear switch provided on a main control board operated by an attendant or the like. It is to provide.

  The pachinko machine according to claim 1 includes a RAM clear switch that allows an operation input, and a RAM clear switch circuit unit that provides a RAM clear signal to the main control circuit unit according to an operation to the RAM clear switch. In order to solve the above-described problem, a first DC power supply generation circuit that rectifies an AC power supply used as a voltage for a gaming machine and generates a first DC power supply is provided. In addition to the first DC power supply generation circuit unit, a second DC power supply having a voltage lower than that of the first DC power supply is generated by rectifying the AC power supply used as the voltage for the gaming machine. And a power supply board on which a second DC power supply generation circuit unit is arranged, and the main control board is supplied with the first DC power from the power supply board through a first DC power supply wiring and the power supply board. From The second DC power supply is supplied through two DC power supply wirings, and the main control board generates an operation power supply for the main control circuit unit based on the second DC power supply. A main control circuit unit power generation unit for supplying to the control circuit unit is provided, and the first DC power source is a dedicated power source for operating the RAM clear switch circuit unit, and the RAM clear switch circuit unit One end of the RAM clear switch is connected to the anode of the diode, the cathode of the diode is connected to the first DC power supply wiring which is the dedicated power supply, and the first DC power supply wiring is grounded via the surge absorbing element. A pachinko machine characterized by

  According to the pachinko machine of the first aspect, the operation power source for the RAM clear switch circuit is a dedicated power source different from the power source for operation of the main control circuit unit (MPU), and the RAM clear switch circuit unit has a RAM clear switch circuit unit. One end is connected to the anode of the diode, the cathode of the diode is connected to the first DC power supply wiring which is a dedicated power supply, and the first DC power supply wiring is grounded via the surge absorbing element. The static noise does not enter the main control circuit section from the RAM clear switch provided on the main control board to be operated, and the electrostatic noise is passed through the surge absorbing element through the first DC power supply wiring which is a dedicated power source. So that you can be sure to take countermeasures against static electricity.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a front view of a game board 46 provided in a pachinko machine according to an embodiment of the present invention. Hereinafter, various components provided in the game area 47 defined in the game board 46 will be described with reference to FIG.

  As shown in FIG. 1, a prize distribution device 50 (distribution device) is arranged at substantially the center of the game area 47. The winning distribution device 50 has won a winning opening 51 (ball entrance) arranged at the upper end position, a winning opening switch (not shown) for detecting a game ball won in the winning opening 51, and the winning opening 51. A spiral-shaped guide passage 52 that guides the game ball downward, and a Clune rolling plate 54 (rotation plate) that rolls the game ball dropped and discharged from the ball discharge port 53 of the guide passage 52 so as to be visible. And a lower space 55 for receiving a game ball dropped and discharged from a ball drop opening (not shown) of the crurn rolling plate 54.

  The lower space 55 is provided with a ball receiving and rotating body 57 (ball distributing means) that always rotates clockwise based on driving of a motor (not shown). The outer periphery of the ball receiving rotor 57 is provided with three notches that are sized to receive one game ball along the entire circumference, and one of these notches constitutes the winning notch 58. The remaining two cutouts constitute a lost cutout 59. Then, the game ball that has entered the winning cutout 58 is sent to a special passage portion (not shown) on the back surface of the game board 46 as the ball receiving rotor 57 rotates, thereby generating a winning gaming state to be described later. On the other hand, the game ball that has entered the unsuccessful cutout portion 59 is sent to a discharge passage portion (not shown) on the back surface of the game board 46 with the rotation of the ball receiving rotor 57 and is collected. Note that the detailed configuration of the winning distribution device 50 is not directly related to the gist of the present invention, and thus the description thereof is omitted.

  An upper variable winning ball device 60 (variable winning ball device) is disposed below the winning distribution device 50, and a lower variable winning ball device 80 (variable winning ball device) is disposed below the upper variable winning ball device 60. Has been placed.

  The upper variable winning ball device 60 has an attachment board 61 for mounting the upper variable winning ball device 60 on the surface of the game board 46 (game area 47). The upper portion of the mounting board 61 is provided with a pair of left and right first and fourth variable winning holes 61a and 61d formed in the size of one game ball. A pair of left and right variable winning openings 61b and 61c formed in the size of one game ball are formed. That is, the first to fourth variable winning holes 61 a to 61 d (winning holes) are provided at a total of four locations on the mounting substrate 61, that is, upper left, lower left, lower right, and upper right.

  Further, the mounting is located between the upper part where the first and fourth variable winning ports 61a and 61d are formed and the lower part where the second and third variable winning ports 61b and 61c are formed. At both left and right ends of the substrate 61, guide protrusions 61e are provided so as to be inclined downward toward the center of the mounting substrate 61, respectively. The left guide protrusion 61e is provided in the vicinity of the upper left portion of the second variable winning opening 61b, thereby guiding the game ball flowing down on the guide protrusion 61e toward the second variable winning opening 61b. The right guiding protrusion 61e is provided in the vicinity of the upper right portion of the third variable winning opening 61c, thereby guiding the game ball flowing down on the guiding protrusion 61e toward the third variable winning opening 61c.

  Opening / closing members 62 (rotating members) are provided in the first to fourth variable prize winning openings 61a to 61d, respectively. The opening / closing member 62 is tilted (variable winning openings 61a to 61d) by an opening mechanism and a closing mechanism (a mechanism that physically uses the weight of the game ball, the detailed structure will be described later) provided on the back surface of the game board 46. And a vertical position (positions at which the variable winning openings 61a to 61d are closed) can be shifted. Specifically, the first to fourth variable winning openings 61a to 61d are obtained by operating the opening mechanism on the back surface of the game board 46 by the game ball that has entered the above-described winning cutout portion 58 and fed into the special passage portion. All of the open / close members 62 are shifted from the vertical position to the tilted position, and the first to fourth variable prize winning openings 61a to 61d are opened. That is, the opening mechanism is configured to open all the variable prize winning openings 61a to 61d by the action of the game ball sent to the special passage portion.

  On the other hand, when the game ball wins in the first to fourth variable winning ports 61a to 61d in the open state, the game ball operates a closing mechanism on the back surface of the game board 46, so that the opening / closing member 62 is moved from the tilt position. It shifts to a vertical position and closes the 1st-4th variable prize winning openings 61a-61d. However, the closing mechanism acts for each of the variable winning ports 61a to 61d so as to close only the variable winning port (opening / closing member 62) where the game ball has won among the first to fourth variable winning ports 61a to 61d. It has become.

  In addition, on the back side of the first to fourth variable winning openings 61a to 61d, respective guide paths (not shown) for guiding the winning game balls in respective directions are provided in communication with each other. Is provided with a winning opening switch (not shown) for detecting a game ball that has entered each of the variable winning openings 61a to 61d. The guide path that communicates with the first variable winning opening 61a is the direction of the first winning ball apparatus 91 (specifically, the first tulip type winning opening 91c) that will be described later for the game balls that have entered the first variable winning opening 61a. To the opening mechanism). The guide path that communicates with the second variable winning opening 61b is a direction of a second winning ball apparatus 92 (specifically, a second tulip type winning opening 92c), which will be described later, with game balls that have entered the second variable winning opening 61b. To the opening mechanism). The guide path that communicates with the third variable winning opening 61c is a direction of a third winning ball apparatus 93 (specifically, a third tulip type winning opening 93c) that will be described later with the game ball that has entered the third variable winning opening 61c. To the opening mechanism). The guide path that communicates with the fourth variable winning opening 61d is a direction of a fourth winning ball apparatus 94 (specifically, a fourth tulip type winning opening 94c), which will be described later. To the opening mechanism).

  Next, the lower variable winning ball device 80 disposed below the upper variable winning ball device 60 will be described. The lower variable winning ball device 80 has a mounting substrate 81 for mounting the lower variable winning ball device 80 to the surface of the game board 46 (game area 47). The upper portion of the mounting board 81 is provided with a pair of left and right fifth and eighth variable winning holes 81a, 81d formed in the size of one game ball. Sixth and seventh variable prize winning openings 81b and 81c formed in the size of one game ball are formed in a pair of left and right. That is, like the first to fourth variable winning holes 61a to 61d of the upper variable winning ball apparatus 60, the fifth to eighth variable winning holes 81a to 81d (winning holes) are the upper left, lower left, It is provided at a total of 4 locations in the lower right and upper right.

  In addition, the mounting is located between the upper portion where the fifth and eighth variable winning ports 81a and 81d are formed and the lower portion where the sixth and seventh variable winning ports 81b and 81c are formed. Similarly to the guide protrusions 61e of the upper variable winning ball apparatus 60, a pair of left and right guide protrusions 81e that protrude downward toward the center of the mounting substrate 81 are provided at the left and right ends of the substrate 81. The left guiding protrusion 81e is provided in the vicinity of the upper left portion of the sixth variable winning opening 81b, thereby guiding the game ball flowing down on the guiding protrusion 81e toward the sixth variable winning opening 81b. The right guiding protrusion 81e is provided in the vicinity of the upper right portion of the seventh variable winning opening 81c, thereby guiding the game ball flowing down on the guiding protrusion 81e toward the seventh variable winning opening 81c.

  The fifth to eighth variable winning holes 81a to 81d are respectively provided with an opening mechanism and a closing mechanism (mechanism that physically uses the weight of the game ball, detailed structure will be described later) provided on the back surface of the game board 46. ) Is provided with an opening / closing member 82 that can be shifted between a tilt position (a position for opening the variable winning openings 81a to 81d) and a vertical position (a position for closing the variable winning openings 81a to 81d). The opening mechanism of the fifth to eighth variable prize winning openings 81a to 81d, like the opening mechanism of the first to fourth variable winning prize openings 61a to 61d, entered the winning cutout 58 and was sent to the special passage section. The fifth to eighth variable winning ports 81a to 81d are all opened by operating by the dead weight of the game ball and moving the opening / closing member 82 from the vertical position to the tilting position. Also, the closing mechanisms of the fifth to eighth variable winning ports 81a to 81d are provided for the variable winning ports 81a to 81d in the same manner as the closing mechanisms of the first to fourth variable winning ports 61a to 61d. Of the fifth to eighth variable winning openings 81a to 81d, only the variable winning opening (opening / closing member 82) where the game ball has been won is closed.

  In addition, guide paths (not shown) for guiding the winning game balls are provided in communication with the back surfaces of the fifth to eighth variable winning openings 81a to 81d, respectively. A winning port switch (not shown) is provided for detecting game balls that have entered the winning ports 81a to 81d. However, the guide paths that communicate with the variable winning ports 81a to 81d guide the game balls that have entered the variable winning ports 81a to 81d, respectively, to a collection passage (not shown) that discharges them to the back side of the pachinko machine. The detailed configurations of the upper variable winning ball device 60 and the lower variable winning ball device 80 are not directly related to the gist of the present invention, and thus the description thereof is omitted.

  On the left and right sides of the upper variable winning ball device 60 and the lower variable winning ball device 80, first to fourth winning ball devices 91 to 94 are provided. The first winning ball apparatus 91 is disposed at the side end position of the game area 47 on the left side of the upper variable winning ball apparatus 60, and the second winning ball apparatus 92 is positioned in the vicinity on the left side of the lower variable winning ball apparatus 80. Has been placed. On the other hand, the third winning ball device 93 is arranged in the vicinity of the right side of the lower variable winning ball device 80, and the fourth winning ball device 94 is the side edge of the game area 47 on the right side of the upper variable winning ball device 60. Placed in position. That is, the first and fourth winning ball devices 91 and 94 located at the left and right ends of the first to fourth winning ball devices 91 to 94 are compared to the second and third winning ball devices 92 and 93. It is arranged at a slightly higher position.

  The first winning ball apparatus 91 has an attachment board 91a for attaching the first winning ball apparatus 91 to the surface (game area 47) of the game board 46. The upper portion of the mounting board 91a is provided with a first open winning opening 91b in which a winning opening switch (not shown) is incorporated, and a winning opening switch (not shown) is provided on the lower portion of the mounting board 91a. The first tulip-type winning opening 91c (which is a variable winning ball device provided with a pair of left and right opening and closing pieces, and is incorporated in the tulip type winning prize hereinafter. Mouth). The opening / closing piece 97 is tilted by a release mechanism and a closing mechanism (a mechanism that physically uses the weight of the game ball) provided on the back surface of the game board 46 (position where the first tulip-type winning opening 91c is opened). It is possible to move between the vertical position (position where the first tulip type winning opening 91c is closed).

  The opening mechanism of the first tulip type winning opening 91c is operated by the weight of the game ball that has entered the first opening winning opening 91b, and the opening and closing piece 97 is shifted from the vertical position to the tilted position. 91c is opened. On the other hand, when the game ball wins in the first tulip type winning opening 91c in the open state, the game ball operates the closing mechanism on the back surface of the game board 46, so that the opening / closing piece 97 shifts from the tilted position to the vertical position. Then, the first tulip type winning opening 91c is closed. That is, when a game ball wins at the first open winning opening 91b, the first tulip type winning opening 91c is opened as a bonus privilege, and when a gaming ball wins at the first tulip type winning opening 91c, the first tulip type winning opening 91c. Is closed. Note that the game ball that has entered the first variable prize opening 61a is also sent to the opening mechanism of the first tulip type winning opening 91c. The winning opening 91c is opened. That is, the first tulip type winning opening 91c is opened in conjunction with winning in the first opening winning opening 91b and winning in the first variable winning opening 61a.

  Next, the second to fourth winning ball devices 92 to 94 will be described. However, the second to fourth winning ball devices 92 to 94 are configured by the same constituent members as the first winning ball device 91, respectively. For this reason, while omitting a detailed description of the same constituent members, the same constituent members are denoted by the same reference numerals. The second winning ball apparatus 92 has an attachment board 92a for attaching the second winning ball apparatus 92 to the surface (game area 47) of the game board 46. Similarly to the mounting board 91a of the first winning ball apparatus 91, the mounting board 92a has a second open winning opening 92b with a winning opening switch (not shown) and a winning opening switch (not shown). In addition, a second tulip type winning opening 92c provided with a pair of left and right open / close pieces 97 is provided. The opening mechanism of the second tulip type winning opening 92c is operated by the weight of the game ball that has entered the second opening winning opening 92b in the same manner as the opening mechanism of the first tulip type winning opening 91c, so that the open / close piece 97 is moved from the vertical position. By shifting to the tilt position, the second tulip-type winning opening 92c is opened.

  On the other hand, as for the closing mechanism of the second tulip type winning opening 92c, similarly to the closing mechanism of the first tulip type winning opening 91c, when a gaming ball wins in the open second tulip type winning opening 92c, the gaming ball However, by operating the closing mechanism on the back surface of the game board 46, the opening / closing piece 97 shifts from the tilting position to the vertical position and closes the second tulip type winning opening 92c. That is, when a game ball wins at the second open winning opening 92b, the second tulip type winning opening 92c is opened as a bonus privilege, and when a gaming ball wins at the second tulip type winning opening 92c, the second tulip type winning opening 92c. Is closed. Note that the game ball that has entered the second variable prize opening 61b is also sent to the opening mechanism of the second tulip type winning opening 92c. The winning opening 92c is opened. In other words, the second tulip type winning opening 92c is opened in conjunction with winning in the second opening winning opening 92b and winning in the second variable winning opening 61b.

  The third winning ball device 93 has an attachment board 93a for attaching the third winning ball device 93 to the surface of the game board 46 (game area 47). Similarly to the mounting board 91a of the first winning ball apparatus 91, the mounting board 93a has a third open winning opening 93b in which a winning opening switch (not shown) is incorporated and a winning opening switch (not shown). In addition, a third tulip type winning opening 93c provided with a pair of left and right opening and closing pieces 97 is provided. The opening mechanism of the third tulip-type winning opening 93c is operated by the weight of the game ball that has entered the third opening winning opening 93b in the same manner as the opening mechanism of the first tulip-type winning opening 91c. By shifting to the tilting position, the third tulip winning prize opening 93c is opened.

  On the other hand, with respect to the closing mechanism of the third tulip type winning opening 93c, similarly to the closing mechanism of the first tulip type winning opening 91c, when a gaming ball wins at the third tulip type winning opening 93c, the gaming ball However, by operating the closing mechanism on the back surface of the game board 46, the opening / closing piece 97 shifts from the tilting position to the vertical position and closes the third tulip type winning opening 93c. That is, when a game ball wins in the third open winning opening 93b, the third tulip type winning opening 93c is opened as a bonus privilege, and when a gaming ball wins in the third tulip type winning opening 93c, the third tulip type winning opening 93c. Is closed. It should be noted that the game ball that has entered the above-described third variable prize opening 61c is also sent to the opening mechanism of the third tulip type prize opening 93c. The winning opening 93c is opened. In other words, the third tulip type winning opening 93c is opened in conjunction with winning in the third opening winning opening 93b and winning in the third variable winning opening 61c.

  The fourth winning ball apparatus 94 has an attachment board 94a for attaching the fourth winning ball apparatus 94 to the surface of the game board 46 (game area 47). Similarly to the mounting board 91a of the first winning ball apparatus 91, the mounting board 94a has a fourth open winning opening 94b with a winning opening switch (not shown) and a winning opening switch (not shown). In addition, a fourth tulip winning prize port 94c provided with a pair of left and right open / close pieces 97 is provided. The opening mechanism of the fourth tulip type winning opening 94c is operated by the weight of the game ball that has entered the fourth opening winning opening 94b in the same manner as the opening mechanism of the first tulip type winning opening 91c. By shifting to the tilting position, the fourth tulip type winning opening 94c is opened.

  On the other hand, as for the closing mechanism of the fourth tulip type winning opening 94c, similarly to the closing mechanism of the first tulip type winning opening 91c, when the gaming ball wins in the open fourth tulip type winning opening 94c, the gaming ball However, by operating the closing mechanism on the back surface of the game board 46, the opening / closing piece 97 shifts from the tilting position to the vertical position and closes the fourth tulip type winning opening 94c. That is, when a game ball wins at the fourth open winning opening 94b, the fourth tulip type winning opening 94c is opened as a bonus privilege, and when a game ball wins at the fourth tulip type winning opening 94c, the fourth tulip type winning opening 94c. Is closed. Note that the game ball that has entered the above-described fourth variable prize opening 61d is also sent to the opening mechanism of the fourth tulip-type prize opening 94c. The winning opening 94c is opened. In other words, the fourth tulip type winning opening 94c is opened in conjunction with winning in the fourth opening winning opening 94b and winning in the fourth variable winning opening 61d.

  In addition to the above configuration, the game area 47 is provided with a general winning port 48, an out port 49, and the like. The general winning port 48 guides the received game balls to a winning port switch (not shown) provided on the back surface of the game board 46, and a total of three locations above and to the left and right of the winning distribution device 50. Is arranged. The out port 49 is provided at the lowermost end of the game area 47, and accepts game balls that have not won any winning port and collects them as out balls.

  Next, a power supply system provided in the pachinko machine of the embodiment will be described. FIG. 2 is a block diagram illustrating a power supply system provided in the pachinko machine according to the embodiment. First, the main power supply AC24V of the pachinko machine is generated, for example, by transforming the commercial power supply 100V by a transformer in an island facility where the pachinko machine (not shown) is installed. (Not shown) to the pachinko machine.

  The power supply board 1 is rectified and smoothed based on the power supply AC24V dedicated to the gaming machine to generate a DC power supply 34V (hereinafter simply referred to as 34V), rectified and smoothed based on the power supply AC24V, 12V generating circuit 3 that generates a DC constant voltage + 12V (hereinafter simply referred to as 12V) stabilized by a regulator, and 5V that generates a DC constant voltage + 5V stabilized by a regulator based on + 12V generated by the 12V generating circuit 3 Power generation detection circuit 5 for detecting a voltage drop of 12V generated by the generation circuit 4 and 12V generation circuit 3, a capacitor 6 as a backup power source for storing and holding the MPU disposed on the main control board 10, and a payout control board 11 is provided with a capacitor 7 as a backup power source for storing and holding the MPU arranged in 11 There.

  In the power supply substrate 1 described above, 34V corresponds to the first DC power supply, and the 34V generation circuit 2 corresponds to the first DC power supply generation circuit unit. 12V corresponds to a second DC power supply having a voltage lower than that of the first DC power supply, and the 12V generating circuit 3 corresponds to a second DC power supply generating circuit unit.

  The 34V power generated by the 34V generating circuit 2 of the power supply board 1 is supplied from the power supply board 1 to the payout control board 11 through the 34V power supply wiring 15a after passing through the fuse 8. The 12V power generated by the 12V generating circuit 3 of the power supply board 1 is supplied from the power supply board 1 to the payout control board 11 through the 12V power supply wiring 16a. Further, the 5V power generated by the 5V creating circuit 4 is supplied to the power failure detection circuit 5 as an operating power.

  The payout control board 11 has a 34V use circuit unit 17 (for example, a payout motor drive circuit for driving a payout motor for operating the prize ball payout device) that operates using 34V as an operating power supply, and a 12V that operates using 12V as an operating power supply. Used circuit unit 18 (for example, a command input circuit for inputting a command transmitted from the main control board, a sand IF circuit for performing data communication with a sand lending machine, and an operation signal or detection signal input by a switch) And an MPU other logic circuit unit 19 mainly for performing payout control of prize balls.

  The 34V power supplied to the payout control board 11 through the 34V power supply wiring 15a is bifurcated in the payout control board 11, one is supplied from the payout control board 11 to the main control board 10 through the 34V power supply wiring 15b, and the other is the payout. The control board 11 is supplied to the launch control board 12 through the 34V power supply wiring 15c. The 34V power supply is branched from the middle of the supply line to the launch control board 12 and supplied to the 34V use circuit unit 17.

  The 12V power supplied to the payout control board 11 through the 12V power supply wiring 16a is bifurcated in the payout control board 11, one is supplied from the payout control board 11 to the main control board 10 through the 12V power supply wiring 16b, and the other is the payout. It is supplied from the control board 11 to the launch control board 12 through the 12V power supply wiring 16c. Further, the 12V power supply is branched from the middle of the supply line to the launch control board 12, and further branched into two. One is directly supplied to the 12V use circuit unit 18, and the other is supplied to the regulator 20. The regulator 20 generates a stabilized DC constant voltage 5 V based on the supplied 12 V, and the 5 V power generated by the regulator 20 is supplied to the MPU other logic circuit unit 19 as an operating power.

  The launch control board 12 has a 34V use circuit unit 21 (for example, a motor drive circuit for driving a launch motor that operates the ball striking device) that operates using 34V as an operation power supply, and a 12V use circuit that operates using 12V as an operation power supply. A unit 22 (for example, a command input circuit for inputting a command transmitted from the payout control board) and a motor control IC 23 for performing a firing motor control are provided.

  The 34V power supplied to the launch control board 12 through the 34V power supply wiring 15c is supplied to the 34V use circuit unit 21. The 12V power supplied to the launch control board 12 through the 12V power supply wiring 16c is bifurcated on the launch control board 12, one is directly supplied to the 12V use circuit unit 22, and the other is supplied to the regulator 24. The regulator 24 generates a stabilized constant voltage + 5V based on the supplied + 12V, and the 5V power generated by the regulator 24 is supplied to the motor control IC 23 as an operating power.

  The main control board 10 has a 12V use circuit unit 25 (for example, a command input circuit for inputting a command transmitted from the payout control board and a detection signal from various detection switches used for game control) that operates using 12V as an operation power source. A game SWIF circuit for inputting, a SWIF circuit for inputting a detection signal by each switch different from the game control, a motor driving circuit for driving a motor for rotating the ball receiving rotating body 47), An MPU other logic circuit unit 26 including an MPU mainly for game control and a RAM clear switch circuit unit 27 are provided.

  The 12V power supplied to the main control board 10 through the 12V power supply wiring 16b is bifurcated in the main control board 10, one is supplied from the main control board 10 to the sub-integrated board 13 through the 12V power supply wiring 16d, and the other is further One of them is directly supplied to the 12V use circuit unit 25 and the other is supplied to the regulator 28. The regulator 28 generates a stabilized DC constant voltage 5 V based on the supplied 12 V, and the 5 V power generated by the regulator 28 is supplied to the MPU other logic circuit unit 26 as an operating power. Further, the 34V power supplied to the main control board 10 through the 34V power supply wiring 15b is bifurcated in the main control board 10, and one of them is a dedicated power supply for operating the RAM clear switch circuit section 27. To be supplied. The other is supplied from the main control board 10 to the sub integrated board 13 through the 34V power supply wiring 15d.

  The sub-integrated board 13 includes a 12V use circuit unit 29 (for example, a command input circuit that inputs a command transmitted from the main control board, an amplifier of a voice circuit unit), a CPU circuit unit 30 that operates using 12V as an operation power A logic circuit unit 31 and an audio circuit unit 32 for audio output are provided.

  The 12V power supplied to the sub-integrated board 13 through the 12V power wiring 16d is bifurcated in the sub-integrated board 13, one is supplied from the sub-integrated board 13 to the lamp driving board 14 through the 12V power wiring 16e, and the other is further One of them is directly supplied to the 12V use circuit unit 29, and the other is supplied to the regulator 33. The regulator 33 generates stabilized DC constant voltages 5V and 3.3V based on the supplied 12V, and the 5V power generated by the regulator 33 is supplied to the CPU circuit unit 30 as an operating power source. .3V power is supplied to the logic circuit unit 31. Further, the 5V power supply and the 3.3V power supply generated by the regulator 33 are also supplied to the audio circuit unit 32 and used as an operating power supply for the audio circuit unit 32. The 34V power supplied to the sub integrated board 13 through the 34V power wiring 15d is only relayed on the sub integrated board 13, and is supplied from the sub integrated board 13 to the frame decoration board 34 through the 34V power wiring 15e. It is used as a power source for lighting an LED for notifying a gaming state or an LED for notifying an abnormal state.

  The lamp driving board 14 is operated by a 12V use circuit unit 35 (for example, a decorative LED driver that is arranged on the game board and controlled to be turned on in accordance with the game state), and operates by using 12V as an operation power source. A vibration detection circuit 36 for detecting the hit is provided. In addition, since the game board 46 of the embodiment gives a great benefit to the player when the game ball enters the winning cutout 58 of the ball receiving rotor 57, the game ball is placed in the lower space 55. There is a possibility that a violating gaming act of hitting the gaming board 46 at the timing of rolling to change the movement of the gaming ball and aiming at entering the winning cutout 58 may be performed. The vibration detection circuit 36 detects a strike on the game board as described above, and notifies it by turning on an LED that notifies the abnormality arranged on the frame decoration board 34.

  The 12V power supplied to the lamp drive board 14 through the 12V power supply wiring 16e is branched into two branches in the lamp drive board 14, one is directly supplied to the 12V use circuit unit 35 as a lighting power supply, and the other is supplied to the regulator 37. The The regulator 37 generates a stabilized DC constant voltage 5 V based on the supplied 12 V, and the 5 V power generated by the regulator 37 is supplied to the vibration detection circuit 36 as an operating power.

  Among the boards described above, the power supply board 1, the payout control board 11, the launch control board 12, and the frame decoration board 34 are arranged on a base frame (frame side) (not shown) of the pachinko machine. The main control board 10, the sub-integrated board 13, and the lamp driving board 14 are disposed on the back surface (game panel side) of the game board 46 that is attached to a front frame (not shown).

  In FIG. 2, when the power of the pachinko machine is cut off, or when a power failure or a momentary power failure occurs, the voltage of the 12V power supply cannot maintain 12V and drops. The power failure detection circuit 9 outputs a power failure signal as a power failure warning when the 12V power supply voltage is equal to or lower than the power failure warning voltage. The power failure signal output by the power failure detection circuit 9 is input to the MPU of the payout control board 11, the MPU of the main control board 10, and the sub integrated board 13.

  Although not shown, the capacitor 6 provided on the power supply board 1 is charged by being connected to the 5V power supply generated in the main control board 10 and functions as a backup power supply when the pachinko machine is turned off. Then, the memory of the MPU RAM arranged on the main control board 10 is held. Similarly, the capacitor 7 provided on the power supply board 1 is charged by being connected to the 5V power supply generated in the payout control board 11, and functions as a backup power supply when the pachinko machine is powered off. The memory of the RAM of the MPU arranged in 11 is held.

  In the electric system of FIG. 2 described above, the 34V power supply wires 15a and 15b correspond to first DC power supply wires, and the 12V power supply wires 16a and 16b correspond to second DC power supply wires. The regulator 28 of the main control board 10 corresponds to a main control circuit unit power generation unit. In the main control board 10, the 34V power supply is a dedicated power supply for operating the RAM clear switch circuit unit 27.

  FIG. 3 is a block diagram showing a power supply system of a circuit portion in the main control board 10. 3 shows only the MPU in the MPU other logic circuit unit shown in FIG. As shown in FIG. 3, the RAM clear switch circuit unit 27 to which 34V power is supplied includes a resistor R1 having one end connected to the 34V power supply line 41 and a cathode connected in series to the other end of the resistor R1. A Zener diode D1 having an anode connected to the ground, a resistor R2 having one end connected to a connection point A between the resistor R1 and the Zener diode D1, and one contact point at the connection point B to the other end of the resistor R2. The RAM clear switch 38, which is a push button type normally open contact switch whose other contact point is connected to the ground, and an anode with respect to a connection point B between the resistor R2 and one contact point of the RAM clear switch 38. And a diode D2 whose cathode is connected to the 34V power supply line 41, a resistor R3 having one end connected to the connection point B, and a resistor R3 A resistor R4 and the other end is connected to ground one end is connected to the end, and a transistor TR for the detection signal.

  The base of the transistor TR is connected to a connection point C between the resistors R3 and R4, the emitter of the transistor TR is grounded, and the collector of the transistor TR is connected to the 5V power supply line 43 via the resistor R5. The collector of the transistor TR is connected to the input terminal PIA of the I / O (expansion port IC) 39, and the I / O 39 data output terminal and the data input terminal of the MPU 40 are connected.

  On the other hand, the input terminal of the regulator (3-terminal regulator) 28 is connected to the 12V power supply line 42, and the output terminal of the regulator 28 is connected to the 5V power supply line 43. The regulator 28 generates a stabilized DC constant voltage 5 V based on the supplied 12 V. The 5 V power generated by the regulator 28 is used for operating the MPU 40 operating power terminal and the I / O 39 through the 5 V power supply line 43. Supplied to the power terminal.

  In the RAM clear switch circuit unit 27 configured as described above, the Zener diode D1 suppresses the voltage at the connection point A from becoming 12V or more. The operation of the RAM clear switch circuit unit 27 will be described. In a state where the RAM clear switch 38 is not operated, the RAM clear switch 38 is open and passes through the resistor R1, the connection point A, the resistor R2, the connection point B, the resistor R3, the connection point C, and the resistor R4 from the 34V power supply line 41. Current flows toward ground. As described above, the voltage at the connection point A does not exceed 12 V due to the Zener voltage of the Zener diode D1. The resistors R2, R3, and R4 are set so that the voltage at the connection point B is approximately 5V. Since the voltage at the connection point C is applied to the base of the transistor TR, the transistor TR is turned on, and current flows from the 5V power supply line 43 through the resistor R5, the collector and emitter of the transistor TR toward the ground. Accordingly, the voltage at the collector of the transistor TR is almost the same level as the ground, and the input of the input terminal PIA of the I / O 39 is at the low level. Therefore, the MPU inputs a low level (no operation) as a detection signal indicating the state of the RAM clear switch 38.

  Next, when the RAM clear switch 38 is operated (when pressed), the RAM clear switch 38 is closed. For this reason, the voltage at the connection point B becomes the same as the ground, and a current flows from the 34V power supply line 41 to the ground through the resistor R1, the connection point A, the resistor R2, and the RAM clear switch 38. Further, since the voltage at the connection point B is the same as the ground, the voltage at the connection point C is also the same as the ground, so the transistor TR is turned off. Therefore, the voltage at the collector of the transistor TR becomes the same level as that of the 5V power supply line 43 connected via the resistor R5, and the input of the input terminal PIA of the I / O 39 becomes high level. Therefore, the MPU inputs a high level (with operation) as a detection signal indicating the state of the RAM clear switch 38.

  In addition, when the operator accidentally contacts the conductive portion of the RAM clear switch 38 (one terminal not connected to the ground) while being charged with static electricity, the voltage at the connection point B instantaneously exceeds 34V. Will be much higher. Therefore, electrostatic noise enters the 34V power supply line 41 through one terminal of the RAM clear switch 38, the connection point B, and the diode D2, and further passes through the 34V power supply wiring 15b and the 34V power supply wiring 15a in FIG. To flow. As a result, electrostatic noise is released to the power supply substrate 1 through the 34V power supply wiring.

  FIG. 4 is a circuit diagram specifically showing the 34V creation circuit unit and the 12V creation circuit unit of the power supply board 1 and the distribution board 120 that is harness-connected to the power supply board 1. Reference numeral 100 denotes a rectifier circuit composed of three sets of diode bridges. AC 24 V is supplied from the distribution board 120 to the rectification circuit 100 via a choke coil 107 arranged as a countermeasure against common mode noise from the distribution board 120 side. The Further, the smoothing capacitor 103 smoothes the output rectified by the rectifier circuit 100 and supplies it to the 34V supply line. The smoothing capacitor 104 smoothes the output 34V rectified by the rectifier circuit 100 and supplies it to the regulator 105. The regulator 105 supplies the DC constant voltage + 12V to the 12V supply line based on the rectified 34V. A varistor 106 is connected as a surge absorbing element between the 34V supply line and the ground line GND.

  The distribution board 120 includes capacitors 108 and 109 and varistors 112 and 113 as countermeasures against common mode noise from the power supply side, and a capacitor 110 and varistor 111 as countermeasures against normal mode noise. Is well known as in the prior art. The varistors 112 and 113 function as surge absorbing elements.

  The electrostatic noise that enters the power supply substrate 1 through the 34V power supply wiring enters the distribution substrate 120 through the diodes 101 and 102 of the rectifier circuit 100 and further through the choke coil 107 when the varistor 106 is turned on. The electrostatic noise that enters the distribution board 120 flows toward the ground when the varistor 112 or varistor 113 is conducted.

  As described above, one end of the RAM clear switch 38 of the RAM clear switch circuit unit in which the operating power source of the RAM clear switch circuit unit 27 is a dedicated power source different from the operating power source of the main control circuit unit (MPU 40). Is connected to the anode of the diode D2, the cathode of the diode D2 is connected to a 34V power supply line 41 which is a dedicated power supply, and the 34V power supply line is grounded via a surge absorbing element (varistor 106, varistor 112, 113). Therefore, electrostatic noise does not enter the main control circuit unit (MPU 40) from the RAM clear switch 38 provided on the main control board 10 operated by an attendant or the like, and it is possible to reliably take measures against static electricity.

  Next, various control processes performed by the CPU (see FIG. 3, hereinafter simply referred to as CPU) of the MPU 40 of the main control board 10 as the game of the pachinko machine proceeds. First, the power-on process will be described, and then the timer interrupt process will be described. FIG. 5 is a flowchart showing an example of power-on processing, and FIG. 6 is a flowchart showing an example of timer interrupt processing.

  When power is turned on to the pachinko machine, the CPU of the main control board 10 performs power-on processing. When the power-on process is started, the CPU sets an interrupt mode (step S01). The interrupt mode is for setting the priority order of interrupts of the CPU. In this embodiment, a timer interrupt, which will be described later, is set as the highest priority, and when this timer interrupt occurs, timer interrupt processing is preferentially performed. Subsequent to step S01, input / output setting (I / O input / output setting) is performed (step S02). In the I / O input / output setting, the CPU I / O is set.

  For example, a terminal that outputs an excitation signal for driving a stepping motor that rotates the ball receiving and rotating body 57 shown in FIG. 1 is set as an output terminal (Output). Further, a terminal to which a detection signal from a winning opening switch for detecting a game ball that has entered the first variable winning opening 61a of the upper variable winning ball apparatus 60 is set as an input terminal (Input).

  Subsequent to step S02, the watchdog timer incorporated in the CPU is set to be valid (step S03). The watchdog timer is for monitoring the operation (system) of the CPU. When the watchdog timer is not cleared within a certain period, the CPU is reset (periodically diagnosing whether the CPU system is out of control). .

  Following step S03, wait timer processing 1 is performed (step S04). The voltage does not increase immediately from when the power is turned on until the voltage reaches the predetermined voltage. On the other hand, when a power outage or a momentary power failure (a phenomenon in which the supply of power is suddenly stopped) occurs, the voltage decreases, and when the voltage falls below the power outage warning voltage, a power outage signal is input as a power outage notice. A power failure signal is input when the voltage falls below the power failure warning voltage from when the power is turned on to when the voltage rises to a predetermined voltage. Therefore, in the wait timer process 1, after the power is turned on, the process waits until the voltage becomes higher than the power failure notice voltage. In this embodiment, 200 milliseconds (ms) is set as the waiting time (wait timer).

  Subsequent to step S04, it is determined whether or not the RAM clear switch 38 is operated (step S05). This determination is made based on whether or not an operation signal (detection signal) of the RAM clear switch 38 is input to the CPU when the RAM clear switch 38 of the main control board 10 is operated. When the detection signal is input, it is determined that the RAM clear switch 38 is operated. On the other hand, when the detection signal is not input, it is determined that the RAM clear switch 38 is not operated.

  When it is determined in step S05 that the RAM clear switch 38 is operated, “1 (operation exists)” is set to the RAM clear notification flag (step S06), and the process proceeds to step S08. On the other hand, when it is determined in step S05 that the RAM clear switch 38 has not been operated, “0 (no operation)” is set to the RAM clear notification flag (step S07), and the process proceeds to step S08. The RAM clear notification flag is a flag indicating whether or not game information relating to a game such as an unpaid prize ball, which is stored in the RAM 10c of the main control board 10, is to be erased. "0" is set when game information is not deleted. Note that the RAM clear notification flag set in step S06 and step S07 is stored in a general-purpose storage element (general-purpose register) of the CPU.

  In step S08, a setting for permitting access to the RAM (see FIG. 3) is performed (step S08). This setting makes it possible to access the RAM. For example, game information can be written (stored) or read. Next, the stack pointer is set (step S09). The stack pointer indicates, for example, the address accumulated on the stack to temporarily store the contents of the memory element (register) being used, or temporarily returns the return address of this routine when returning to this routine after completing the subroutine. It indicates the address that is stacked on the stack for storage, and the stack pointer advances each time the stack is stacked. In step S09, an initial address is set in the stack pointer, and the contents of the register, the return address, etc. are stacked on the stack from this initial address. Then, the stack pointer is returned to the initial address by reading from the last stacked stack to the first stacked stack.

  Subsequent to step S09, it is determined whether or not the RAM clear notification flag is “0” (step S10). As described above, the RAM clear notification flag is set to “1” when the game information is erased, and “0” when the game information is not erased. In step S10, when the RAM clear notification flag is “0”, that is, when the game information is not deleted, the process proceeds to step S11 to calculate a checksum (step S11).

  The checksum is calculated by regarding the game information stored in the RAM as a numerical value and calculating the sum. Next, it is determined whether or not the calculated checksum value matches a checksum value stored in a power-off process (power-off) described later (step S12). If it is determined in step S12 that the calculated checksum value matches the stored checksum value in the power-off process (power-off process), the process proceeds to step S13, and the backup flag is set to “1”. ] Is determined (step S13). The backup flag is a flag indicating whether backup information such as game information, a checksum value, and a backup flag value is stored in the RAM in the power-off process described later. When the power-off process is performed, “1” is set to “0” when the power-off process is not performed.

  In step S13, when the backup flag is “1”, that is, when the power-off process is performed, the process proceeds to step S14, and the RAM work area is set when power is restored (step S14). For the power recovery setting, the backup flag is cleared to 0, the power recovery information is read from the ROM of the main control board 10, and the read power recovery information is set in the RAM work area. Here, “at power recovery” includes not only a state in which the power is turned off but also a state in which the power is turned on, and a state in which power is restored after a power failure or a momentary power failure.

  Next, the process proceeds to step S15, where power-on command creation processing is performed (step S15). When step S15 is completed, the process proceeds to step S19. In the power-on command creation process, the game information is read from the backup information, and various commands corresponding to the game information are stored in a predetermined storage area of the RAM. Note that various commands will be described later.

  On the other hand, in step S10, when the RAM clear notification flag is not “0” (that is, “1”), that is, when the game information is deleted, the process proceeds to step S16. In step S12, when the checksum values do not match, the process proceeds to step S16. Further, in step S13, when the backup flag is not “1” (that is, “0”), that is, when the power-off process is not performed, the process proceeds to step S16.

  When the process proceeds to step S16, the entire area of the RAM is cleared (step S16), and the RAM work area is set as an initial setting (step S17). For this setting, initial information is read from R0M of the main control board 10, and this initial information is set in the work area of the RAM. Next, RAM clear notification and test command creation processing is performed (step S18). When step S18 is completed, the process proceeds to step S19. In the RAM clear notification and test command creation processing, a RAM clear notification command for notifying the sub-integrated board 13 shown in FIG. 2 that the RAM clear switch 38 has been operated and various inspections of the sub-integrated board 13 are performed. And a test command for generating a test command, and storing the test command in the transmission information storage area as transmission information.

  If it progresses to step S19, interruption initial setting will be performed (step S19). This setting is to set an interrupt cycle when a timer interrupt process described later is performed. In this embodiment, it is set to 4 ms. Next, interrupt permission setting is performed (step S20). With this setting, the timer interrupt process is repeated every interrupt cycle set in step S19, that is, every 4 ms.

  When step S20 ends, the process proceeds to step S21, and a value A is set in the watchdog timer clear register WCL (step S21). The watchdog timer is cleared by setting the value A, the value B, and the value C in this order in the watchdog timer clear register WCL. Next, the CPU determines whether or not a power failure signal is input (step S22). As described above, when the power of the pachinko machine is shut off, or when a power failure or a momentary power failure occurs, a power failure signal is input as a power failure warning voltage when the voltage falls below the power failure warning voltage. The determination in step S22 is made based on this power failure signal.

  If it is determined that the power failure signal has not been input, the process returns to step S21 again, and the value A is set in the watchdog timer clear register WCL. Accordingly, the processing routine for determining NO in steps S21 and S22 is repeated. Note that the processing in steps S21 to S22 is referred to as “main processing”.

  On the other hand, when a power failure signal is input in step S22, the process proceeds to step S30, and interrupt prohibition setting is performed (step S30). Due to the interrupt prohibition setting, a timer interrupt process described later is not performed, writing to the RAM is prevented, and rewriting of game information is protected. Subsequent to step S30, a checksum is calculated and the calculated value is stored (step S31). The checksum is calculated by regarding the game information in the RAM work area excluding the storage area for the checksum value and backup flag value described above as a numerical value.

  Next, a value 1 is set in the backup flag (step S32). This completes the storage of the backup information. Next, access prohibition to the RAM is set (step S33). With this setting, access to the RAM is prohibited, and writing and reading cannot be performed, and backup information stored in the RAM is protected. Following step S33, the watchdog timer is cleared (step S34). As described above, this clearing is performed by setting the value A, the value B, and the value C in the watchdog timer clear register WCL in order.

  When the CPU performs step S34, the CPU enters an infinite loop. In the infinite loop, since the value A, the value B, and the value C are not sequentially set in the watchdog timer clear register WCL, the watchdog timer is not cleared. For this reason, the CPU is reset, and then the CPU performs this power-on process again. The processing from step S30 to step S34 and the infinite loop are referred to as “power-off processing”.

  The pachinko machine (CPU) is reset when a power failure occurs or when an instantaneous power failure occurs, and the power-on process is performed after the power is restored.

  Next, the timer interrupt process will be described. The timer interrupt process is repeatedly performed every interrupt period (4 ms in the present embodiment) set in the power-on process shown in FIG.

  When the timer interrupt process is started, the CPU of the main control board 10 sets the timer interrupt to be prohibited and switches (saves) the register as shown in FIG. 6 (step S40). Here, the storage element (register) used in the main process is switched to the auxiliary register, and this auxiliary register is used in the timer interrupt process. For this reason, the value of the register used in the main process is not overwritten, and the contents are prevented from being destroyed.

  Next, the value B is set in the watchdog timer clear register WCL (step S41). At this time, the value B is set in the watchdog timer clear register WCL following the value A set in step S21 of the power-on process (main process).

  Next, switch input processing is performed (step S42). In this switch input process, the input state of the terminal set as the input terminal (Input) in the I / O input / output setting in step S02 of the power-on process is read and stored as input information in the input information storage area of the RAM. . For example, a detection signal from a winning opening switch that detects a game ball that has entered the first variable winning opening 61a of the upper variable winning ball apparatus 60 of FIG. 1 is read and stored in the input information storage area.

  Subsequent to step S42, timer subtraction processing is performed (step S43). In this timer subtraction process, for example, the time output from the output terminal is managed in a port output process (step S49) described later.

  Following the step S43, a prize ball control process is performed (step S44). In the prize ball control process, the input state of the input terminal, that is, the input information is read from the above-described input state storage area, and a prize ball command for paying out a game ball is created based on this input information. Then, the created prize ball command is transmitted to the payout control board 11 shown in FIG.

  When step S44 is performed, a winning number check process is performed (step S45). In the winning number check process, an abnormal state related to the winning ball is confirmed. For example, when a predetermined number or more of game balls enter the first variable winning opening 61a of the upper variable winning ball apparatus 60 in FIG. 1, a prize ball abnormality notification command is created as an abnormal state, and the transmission information described above as transmission information. Store in the storage area.

  When step S45 is performed, a payout abnormality command reception process is performed (step S46). The payout control board 11 transmits a payout abnormality command to the main control board 10 when, for example, a payout abnormality (for example, the game ball cannot be paid out due to a clogged ball) occurs in a payout device (not shown). In the payout abnormality command reception process in step S46, when a payout abnormality command is received, a payout abnormality notification command is created and stored as transmission information in the transmission information storage area.

  Subsequent to step S46, a game effect command creation process is performed (step S47). In the game effect command creation process, input information is read from the above-described input intelligence storage area, and based on this input information, a game effect command for playing and controlling the lighting and decoration LEDs on the sub-integrated board 13 is created. The transmission information is stored in the transmission information storage area described above.

  If step S47 is performed, it will progress to step S48 and will perform a motor drive signal preparation process (step S48). In the motor drive signal creation process, excitation signal data for driving the stepping motor that rotates the ball receiving and rotating body 57 of FIG. 1 is stored in the output information storage area.

  Subsequent to step S48, port output processing is performed (step S49). In the port output process, output information is read from the output information storage area described above, and output control of the output terminal is performed based on this output information. For example, an excitation signal for driving a stepping motor that rotates the ball receiving rotor 57 of FIG. 1 is output.

  Subsequent to step S49, command transmission processing related to the sub-integrated base slope 13 is performed (step S50). In the command transmission process, the transmission information is read from the transmission information storage area described above, and this transmission information is transmitted to the sub-integrated board 13 shown in FIG. This transmission information is configured by combining the above-described game effect command, RAM clear notification command, test command, prize ball abnormality notification command, payout abnormality notification command, and the like.

  Subsequent to step S50, a value C is set in the watchdog timer clear register WCL (step S51). At this time, the value C is set in the watchdog timer clear register WCL following the value B set in step S41. As a result, the value A, the value B, and the value C are sequentially set in the watchdog timer clear register WCL, and the watchdog timer is cleared. Subsequent to step S51, the register is switched (returned) (step S52). This return is performed by reading the contents saved on the stack in step S40 and writing the contents in a register. Subsequent to step S52, interrupt permission is set (step S53), and this routine ends.

It is a front view of the game board deployed in the pachinko machine according to one embodiment of the present invention. It is a block diagram which shows the power supply system arrange | positioned at the pachinko machine of embodiment. It is a block diagram which shows the RAM clear switch circuit part and main control circuit part in a main control board. It is the circuit diagram which showed concretely the 34V creation circuit part and 12V creation circuit part of a power supply board, and the power distribution board currently harness-connected with the power supply board. It is a flowchart which shows an example of the power-on process which CPU of a main control board performs. It is a flowchart which shows an example of the timer interruption process which CPU of a main control board performs. It is a block diagram which shows the RAM clear switch circuit part and main control circuit part in the conventional main control board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Power supply board 2 34V creation circuit 3 12V creation circuit 4 5V creation circuit 5 Power failure detection circuit 6 Capacitor 7 Capacitor 8 Fuse 9 Power failure detection circuit 10 Main control board 11 Discharge control board 12 Launch control board 13 Sub-integrated board 14 Lamp drive board 15a -15e 34V power supply wiring 16a-16e 12V power supply wiring 17 34V use circuit part 18 12V use circuit part 19 MPU other logic circuit part 20 regulator 21 34V use circuit part 22 12V use circuit part 23 Motor control IC
24 regulator 25 12V use circuit part 26 MPU other logic circuit part 27 RAM clear switch circuit part 28 regulator 29 12V use circuit part 30 CPU circuit part 31 logic circuit part 32 audio circuit part 33 regulator 34 frame decoration board 35 12V use circuit part 36 Vibration detection circuit 37 Regulator 38 RAM clear switch 39 I / O
40 MPU
41 34V power supply line 42 12V power supply line 43 5V power supply line 46 Game board 47 Game area 48 General winning port 49 Out port 50 Winning distribution device 51 Winning port 52 Guidance passage 53 Ball discharge port 54 Clune rolling plate 55 Lower space 57 ball Rotating body 58 Winning cutout portion 59 Declined cutout portion 60 Upper variable winning ball device 61 Mounting substrate 61a First variable winning port 61b Second variable winning port 61c Third variable winning port 61d Fourth variable winning port 61e Guidance Projection 62 Opening / closing member 80 Lower variable winning ball device 81 Mounting substrate 81a Fifth variable winning port 81b Sixth variable winning port 81c Seventh variable winning port 81d Eight variable winning port 81e Guide projection 82 Opening / closing member 91 1st Winning ball apparatus 91a Mounting board 91b First open winning opening 91c First tulip type winning opening 92 Second winning prize Ball device 92a Mounting board 92b Second open prize opening 92c Second tulip type prize opening 93 Third winning ball apparatus 93a Attachment board 93b Third open prize opening 93c Third tulip type prize opening 94 Fourth winning ball apparatus 94a Mounting board 94b 4th open prize opening 94c 4th tulip type prize opening 97 Opening and closing piece 100 Rectifier circuit 101 Diode 102 Diode 103 Smoothing capacitor 104 Smoothing capacitor 105 Regulator 106 Varistor 107 Choke coil 108 Capacitor 109 Capacitor 110 Capacitor 111 Varistor 112 Varistor 113 Varistor R1 Resistance R2 Resistor R3 Resistor R4 Resistor R5 Resistor D1 Zener diode TR transistor

Claims (1)

A pachinko machine having a main control board on which a RAM clear switch capable of operation input and a RAM clear switch circuit unit for supplying a RAM clear signal to the main control circuit unit according to an operation to the RAM clear switch are provided. In the machine
Separately from the first DC power supply generation circuit unit that rectifies the AC power supply for the gaming machine and generates a first DC power supply, and for the gaming machine A power supply board provided with a second direct current power generation circuit unit that rectifies the alternating current power supply having a voltage to generate a second direct current power supply having a voltage lower than that of the first direct current power supply, The control board is configured such that the first DC power is supplied from the power board through the first DC power wiring and the second DC power is supplied from the power board through the second DC power wiring. The main control board includes a main control circuit unit power generation unit that generates an operation power source for the main control circuit unit based on the second DC power source and supplies the main control circuit unit to the main control circuit unit. The first DC power supply is connected to the R A first power source that is a dedicated power source for operating the M clear switch circuit unit, one end of the RAM clear switch of the RAM clear switch circuit unit is connected to an anode of a diode, and a cathode of the diode is the dedicated power source. The pachinko machine is connected to a DC power supply wiring, and the first DC power supply wiring is grounded via a surge absorbing element.

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