JP6875580B2 - Pachinko machine - Google Patents

Description

The present invention relates to a gaming machine capable of playing a game such as a pachinko gaming machine.

In gaming machines such as pachinko gaming machines, techniques related to signal lines for connecting electrical components such as CPUs and ROMs have been proposed (for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2014-223336

According to the technique described in Patent Document 1, there is a possibility that an appropriate substrate configuration cannot be obtained, for example, signal synchronization is likely to be disturbed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a gaming machine capable of an appropriate substrate configuration.

(A) In order to achieve the above object, the gaming machine according to the claim of the present application is
A Yu technique capable gaming machine,
A power supply substrate capable of supplying electric power to the electrical components,
And a control board supplied with power supply voltage from the previous SL power supply board, and
Before Symbol control board,
A control circuit that can control the progress of the production,
A generation circuit that can generate the power supply voltage used in the control circuit,
A stabilization circuit that stabilizes the power supply voltage,
An audio circuit that can output audio signals and
Including a monitoring circuit that can monitor the power supply voltage,
The generation circuit generates a predetermined output voltage, which is a voltage lower than the predetermined input voltage, from a predetermined input voltage input to the generation circuit.
The monitoring circuit can monitor the predetermined input voltage and output a specific signal to the control circuit when the voltage value of the predetermined input voltage is lower than the predetermined value.
As the power source voltage supplied from the power board includes a first power supply voltage, a second power supply voltage different from the said first power supply voltage,
The pre-Symbol first power supply voltage, and the power supply voltage for driving the particular electrical components, after branching to a power supply voltage to be supplied to the audio circuit, the voice power supply voltage stabilized by the stabilization circuit Supply to the circuit,
Before SL particular electrical components includes a circuit element of the current driven type,
Power supply voltage for driving the pre-Symbol particular electrical component, the power supply path after branching the first supply voltage is connected to the noise reduction circuit,
The wiring length from the previous SL stabilization circuit to said audio circuit is shorter than the wiring length from the branches of the first power supply voltage to be input to the stabilization circuit,
Before Stories second power supply voltage is not connected to the stabilization circuit,
And wherein a call.
(1) The other game machine is a game machine capable of playing a game (for example, a pachinko game machine 1), and a pattern constituting a plurality of signal wirings is formed (see, for example, FIG. 17), and the plurality of signals are described. A board (for example, a main board 11) to which a plurality of electric components (for example, RAM 102 and CPU 103) are connected by wiring is provided, and the pattern is a parallel wiring in which the plurality of signal wirings are parallel or substantially parallel to each other. A portion (for example, region 30AK10R) and a specific wiring portion (for example, region 30AK11R) in which at least one of the plurality of signal wirings has a second shape that is not parallel to the other signal wirings. The wiring length of each signal wiring included in the plurality of signal wirings is the same or substantially the same.
With such a configuration, an appropriate substrate configuration becomes possible.

(2) In the game machine of the above (1), in the signal wiring not including the second shape (for example, the signal wiring configured by the wiring pattern 30AK10D), the distance between the connection terminals in the plurality of electrical components is the said. It may be longer than the signal wiring including the second shape (for example, the signal wiring configured by the wiring patterns 30AK11D to 30AK13D).
In such a configuration, an appropriate substrate configuration becomes possible.

(3) In the gaming machine of the above (1) or (2), a conductor may not be provided in a predetermined region (for example, a space region 30AK0SP) close to the signal wiring having the second shape.
In such a configuration, an appropriate substrate configuration becomes possible.

(4) In any of the game machines (1) to (3) above, the board is electrically provided with signal wiring provided on one surface of the board and signal wiring provided on the other side of the board. Through holes (for example, through holes 30AK1H, 30AK2H, etc.) that can be connected to the through holes are provided, and the wiring length of each signal wiring included in the plurality of signal wirings is such that the signal wirings connected by the through holes are of the through holes. It may be the same or substantially the same including the length.
In such a configuration, an appropriate substrate configuration becomes possible.

(5) In any of the gaming machines (1) to (4), the substrate is composed of a plurality of layers (for example, surface layer 30AK1S, ground layer 30AK1L, power supply layer 30AK2L, wiring layer 30AK3L, power supply layer 30AK4L, back surface layer). 30AK2S and the like), and the conductor layer (for example, the ground layer 30AK1L and the like) adjacent to the layer in which the signal wiring having the second shape is provided among the plurality of layers may not transmit the signal.
In such a configuration, an appropriate substrate configuration becomes possible.

(6) In any of the gaming machines (1) to (5), the processing means (for example, CPU 103) capable of executing a predetermined process and the information related to the execution of the process are stored as the plurality of electric components. A possible storage means (eg, RAM 102, etc.) may be connected.
In such a configuration, an appropriate substrate configuration becomes possible.

(7) Alternatively, in a game machine capable of playing a game (for example, a pachinko game machine 1 or the like), a pattern constituting a plurality of signal wirings is formed (see, for example, FIG. 17), and a plurality of the plurality of signal wirings are used. A board (for example, main board 11) to which electrical components (for example, RAM 102 and CPU 103) are connected is provided, and the pattern is a parallel wiring portion (for example, a region) in which the plurality of signal wirings are parallel or substantially parallel to each other in the first shape. 30AK10R, etc.) and a specific wiring portion (for example, region 30AK11R, etc.) in which at least one of the plurality of signal wirings has a second shape different from the first shape, and the plurality of signal wirings include. The wiring length of each signal wiring included may be the same or substantially the same.
Such a configuration also enables an appropriate substrate configuration.

(8) Alternatively, in a game machine capable of playing a game (for example, a pachinko game machine 1 or the like), a pattern constituting a plurality of signal wirings is formed (see, for example, FIG. 17), and a plurality of the plurality of signal wirings are used. A substrate (for example, a main substrate 11) to which electrical components (for example, RAM 102 and CPU 103) are connected is provided, and the pattern includes a linear shape or a substantially linear shape in at least one signal wiring among the plurality of signal wirings. The first pattern (for example, wiring pattern 30AK10D) that becomes the first shape and the other signal wiring that is not included in the first pattern among the plurality of signal wirings have a second shape that is different from the first shape. The first pattern and the second pattern include the second pattern (for example, wiring patterns 30AK11D to 30AK13D), and the wiring lengths of the respective signal wirings included in the plurality of signal wirings are the same or substantially the same. You may become.
Such a configuration also enables an appropriate substrate configuration.

(9) Alternatively, in a game machine capable of playing a game (for example, a pachinko game machine 1 or the like), a pattern constituting a plurality of signal wirings is formed (see, for example, FIG. 17), and a plurality of the plurality of signal wirings are used. A board (for example, main board 11) to which electrical components (for example, RAM 102 and CPU 103) are connected is provided, and in the pattern, at least one signal wiring among the plurality of signal wirings has a predetermined section (for example, section 30AK0SC). The first pattern (for example, wiring patterns 30AK10D, 30AK11D, etc.) and other signal wirings that are not included in the first pattern among the plurality of signal wirings form the predetermined section. The first pattern and the second pattern include each signal wiring included in the plurality of signal wirings, including a second pattern (for example, wiring patterns 30AK12D, 30AK13D, etc.) connected at a longer distance than the first pattern. The wiring lengths of the above may be the same or substantially the same.
Such a configuration also enables an appropriate substrate configuration.

(10) In the gaming machine of the above (8) or (9), in the first pattern, the distance between the connection terminals in the plurality of electric components may be longer than that of the second pattern.
In such a configuration, an appropriate substrate configuration becomes possible.

(11) In any of the gaming machines (8) to (10), a conductor may not be provided in a predetermined region (for example, a space region 30AK0SP) close to the second pattern.
In such a configuration, an appropriate substrate configuration becomes possible.

(12) In any of the gaming machines (8) to (11), the substrate has a plurality of layers (for example, surface layer 30AK1S, ground layer 30AK1L, power supply layer 30AK2L, wiring layer 30AK3L, power supply layer 30AK4L, back surface layer). 30AK2S and the like) and the conductor layer (for example, the ground layer 30AK1L and the like) adjacent to the layer in which the signal wiring included in the second pattern is provided among the plurality of layers may not transmit the signal.
In such a configuration, an appropriate substrate configuration becomes possible.

It is a front view of the pachinko gaming machine in this embodiment. It is a block diagram which shows various control boards and the like mounted on the pachinko gaming machine. It is a rear view of the frame for a game machine. It is an exploded perspective view of the state which looked at the substrate case. It is an exploded perspective view of the state which looked at the substrate case. It is a 6-view view which shows the base member. It is a 6-view view which shows the cover member. It is a perspective view of the state which looked at the receptacle. It is a rear view of the state of looking at the receptacle. It is sectional drawing of the state which looked at the receptacle. It is a figure which shows the transmission path corresponding to wiring. It is a figure which shows the transmission path of a power supply voltage. It is a figure which shows the relationship of the wiring length. It is a figure which shows the structural example of a filter circuit. It is a figure which shows the structural example of the noise prevention circuit. It is a figure which shows the power supply monitoring circuit. It is a figure which shows the structural example of the part where the wiring pattern was formed. It is a figure which shows the area and section for explaining a wiring pattern. It is an enlarged view of the region shown in FIG. It is a figure which shows the setting example corresponding to a wiring pattern. It is an enlarged view of the region shown in FIG. It is an enlarged view of the region shown in FIG. It is sectional drawing which shows the structural example of the main board. It is a figure which shows the other configuration example about the wiring pattern.

FIG. 1 is a front view of the pachinko gaming machine 1 according to this embodiment. The pachinko gaming machine 1 includes a gaming board 2 and a gaming machine frame 3. In addition, the pachinko gaming machine 1 includes an outer frame that rotatably supports the gaming machine frame 3. The game board 2 is a gauge board that constitutes the game board surface. The gaming machine frame 3 is an underframe for fixing the gaming board 2. The game board 2 is formed with a game area surrounded by a guide rail or the like. The game ball (game medium) launched from the launcher passes through the launch passage and is driven into the game area. The gaming machine frame 3 is provided with a rotatably glass door frame having a glass window.

At a predetermined position on the game board 2, a first special symbol display device 4A, a second special symbol display device 4B, an image display device 5, a normal winning ball device 6A, a normal variable winning ball device 6B, a special variable winning ball device 7, A normal symbol display 20, a first hold display 25A, a second hold display 25B, a normal figure hold display 25C, a passing gate 41, and the like are provided. In addition, the surface of the game board in the game area may be provided with a windmill, a large number of obstacle nails, a general winning opening, an out opening, and the like. A game effect lamp 9 is provided in the peripheral portion of the game area. Speakers 8L and 8R are provided at the upper left and right positions of the gaming machine frame 3.

A ball striking operation handle (operation knob) is provided at the lower right position of the gaming machine frame 3. The hitting ball operation handle is operated by a player or the like in order to launch the game ball toward the game area, and the elastic force of the game ball is adjusted according to the operation amount (rotation amount). An upper plate (striking ball supply plate) for holding (storing) game balls and a lower plate for holding (storing) surplus balls from the upper plate are provided at predetermined positions of the gaming machine frame 3 below the game area. Has been done. A stick controller 31A is attached to the member forming the lower plate, and a push button 31B is provided to the member forming the upper plate.

On the screens of the first special symbol display device 4A, the second special symbol display device 4B, the image display device 5, and the like, variable display of special symbols and decorative symbols is performed. These variable displays are based on the occurrence of the first starting prize due to the game ball passing (entering) the first starting winning opening formed in the ordinary variable winning ball device 6A, or in the ordinary variable winning ball device 6B. It becomes feasible based on the occurrence of the second start prize due to the game ball passing (entering) the formed second start prize opening. Each of the first special symbol display device 4A and the second special symbol display device 4B is configured by using, for example, a 7-segment or dot matrix LED (light emitting diode), and is identified in a special symbol game which is an example of a variable display game. A special symbol (special symbol), which is information (special identification information), is variably displayed (variable display). The image display device 5 is configured by using, for example, an LCD (liquid crystal display) or the like, and forms a display area for displaying various effect images. On the screen of the image display device 5, the variable display of the special symbol (first special symbol) by the first special symbol display device 4A and the special symbol (second special symbol) by the second special symbol display device 4B in the special symbol game. Corresponding to each of the variable display, the decorative symbol which is the identification information (decorative identification information) is variably displayed in the decorative symbol display area which is a plurality of variable display units such as three. The variable display of this decorative pattern is also included in the variable display game. As an example, on the screen of the image display device 5, "left", "middle", and "right" decorative pattern display areas 5L, 5C, and 5R are arranged.

A hold storage display area 5H is arranged on the screen of the image display device 5. In the hold storage display area 5H, a hold display for identifiablely displaying the number of holds (the number of holds for special figures) of the variable display corresponding to the special figure game is performed. The hold display may be any display that can be displayed corresponding to the hold storage of information related to the variable display. Hold display may be performed together with the hold storage display area 5H or instead of the hold storage display area 5H by using the first hold display 25A and the second hold display 25B.

FIG. 2 is a block diagram showing configuration examples of various substrates and peripheral devices. The pachinko gaming machine 1 is equipped with various control boards such as a main board 11, an effect control board 12, a voice control board 13, and a lamp control board 14, as shown in FIG. 2, for example. Further, the pachinko gaming machine 1 is also equipped with a relay board 15, a driver board 19, a power supply board 92, and the like. In addition, various boards such as a payout control board, an information terminal board, a launch control board, an interface board, a touch sensor board, and the like may be mounted. Various control boards are not limited to electronic circuit boards such as printed wiring boards on which conductor patterns are formed and electrical components are mounted, but also electrical components are mounted (mounted) on the electronic circuit boards to realize specific electrical functions. It is a concept including an electronic circuit mounting board configured as described above.

The power supply board 92 is configured to be able to supply electric power from an AC power source, which is an external power source (commercial power source), to electrical components including various control boards such as the main board 11 and the effect control board 12. The power supply board 92 includes, for example, a rectifying circuit for converting alternating current (AC) to direct current (DC), a power supply circuit for converting a predetermined direct current voltage to a specific direct current voltage (for example, direct current 12V, direct current 5V, etc.), and the like. , Prepared. The voltage generated by the power supply board 92 may be supplied to the main board 11, the effect control board 12, and the like via the drawer relay board.

A game control microcomputer 100, a switch circuit 110, a solenoid circuit 111, and the like are mounted on the main board 11. On the main board 11, signals captured from various detection switches such as the gate switch 21, the start port switch (first start port switch 22A and the second start port switch 22B), and the count switch 23 are transmitted via the switch circuit 110. It is transmitted to the game control microcomputer 100. The gate switch 21 detects a game ball (gate passing ball) that has passed through the passing gate 41. Based on the detection of the gate passing sphere by the gate switch 21, the variable display of the normal symbol by the normal symbol display 20 becomes feasible. The first start opening switch 22A detects a game ball that has passed (entered) the first start winning opening. The second start opening switch 22B detects a game ball that has passed (entered) the second start winning opening. The count switch 23 detects a game ball that has passed (entered) the large winning opening. When a game ball that has passed through various winning openings such as the first starting winning opening, the second starting winning opening, and the large winning opening is detected, the number of winning balls is determined in advance corresponding to each winning opening. The game ball as is paid out.

On the main board 11, the solenoid drive signal from the game control microcomputer 100 is transmitted to the solenoid 81 for the ordinary electric accessory and the solenoid 82 for the grand prize opening door via the solenoid circuit 111. The solenoid 81 for an ordinary electric accessory has a state in which the game ball is difficult to pass (or a state in which it does not pass) and a state in which it is easy to pass (or a state in which it passes) through the second starting winning opening formed in the ordinary variable winning ball device 6B. Make it changeable. The solenoid 82 for the large winning opening door makes the large winning opening formed in the special variable winning ball device 7 changeable between a state in which the game ball cannot pass and a state in which the game ball can pass. From the main board 11, a command signal for performing display control of the first special symbol display device 4A, the second special symbol display device 4B, the ordinary symbol display 20, and the like is transmitted.

The game control microcomputer 100 mounted on the main board 11 is, for example, a one-chip microcomputer, and includes a ROM 101 that stores a game control program, fixed data, and the like, and a RAM 102 that provides a work area for game control. , A CPU 103 that executes a game control program to perform a control operation, a random number circuit 104 that updates numerical data indicating a random value independently of the CPU 103, and an I / O (Input / Output port) 105. Be prepared. As an example, in the game control microcomputer 100, a process for controlling the progress of the game in the pachinko gaming machine 1 is executed by executing the program read from the ROM 101 by the CPU 103. In the game control microcomputer 100 mounted on the main board 11, various random number values used for controlling the progress of the game are set by, for example, a random number circuit 104 or a game random counter provided in a predetermined area of the RAM 102. The indicated numerical data is counted (generated) so that it can be updated. Random numbers used to control the progress of the game are also called game random numbers.

The effect control board 12 includes an image display device 5, speakers 8L, 8R, a game effect lamp 9, and an effect motor based on the reception of a control signal (effect control command) transmitted from the main board 11 via the relay board 15. It is possible to control the effect operation by the effect electric parts such as the 60 and the effect LED 61. The effect control board 12 is equipped with an effect control CPU 120, a ROM 121, a RAM 122, a display control unit 123, a random number circuit 124, an I / O 125, and the like.

The effect control CPU 120 mounted on the effect control board 12 executes a process for controlling the effect operation by the effect electric component by using the effect control program, fixed data, and the like read from the ROM 121. The display control unit 123 mounted on the effect control board 12 determines the control content of the display operation in the image display device 5 based on the display control command from the effect control CPU 120 or the like. For example, the display control unit 123 controls the variable display of the decorative pattern and various effect displays by determining the switching timing of the effect image to be displayed in the display screen of the image display device 5.

The controller sensor unit 35A and the push sensor 35B are connected to the effect control board 12. The controller sensor unit 35A includes a tilt direction sensor and a trigger sensor. The tilting direction sensor makes it possible to detect the tilting direction of the operating rod by using a plurality of sensors when the tilting operation of the stick controller 31A is performed on the operating rod. The trigger sensor makes it possible to detect the presence or absence of a push-pull operation on the trigger button provided on the operation stick of the stick controller 31A. That is, the controller sensor unit 35A can detect the player's operation using the stick controller 31A, such as the tilting operation of the stick controller 31A with respect to the operation stick and the pushing / pulling operation of the trigger button. The push sensor 35B can detect an action of a player using the push button 31B, such as a pressing action on the push button 31B. In the effect control board 12, for example, numerical data indicating various random number values used for controlling the execution of the effect can be updated and counted by a random number circuit 124, a random number counter for effect provided in a predetermined area of the RAM 122, or the like. Is generated). Random numbers used to control the execution of the effect are also called effect random numbers.

The effect control board 12 has a first board 12A and a second board 12B connected to the first board 12A from the board to the board. The first board 12A is equipped with a CPU 120 for effect control, a graphics processor of a display control unit 123, and the like, and the second board 12B is an electrical component in which data unique to a model such as a ROM 121 and an image data memory are stored. Is installed. The graphics processor of the display control unit 123 may be a microprocessor in which the functions of the effect control CPU 120 are integrated, or may be a microprocessor configured as a chip separate from the effect control CPU 120.

The audio control board 13 is a control board for audio output control provided separately from the effect control board 12, and outputs audio from the speakers 8L and 8R based on commands and control data from the effect control board 12. It is equipped with a processing circuit that executes audio signal processing to make it. If the graphics controller or the like constituting the display control unit 123 mounted on the effect control board 12 can execute the audio signal processing, the band filter, the amplifier circuit, or the like may be mounted on the audio control board 13. Alternatively, the voice control board 13 may be omitted, and a band filter, an amplifier circuit, or the like may be mounted on the board of the effect control board 12. The lamp control board 14 is a control board for lamp output control provided separately from the effect control board 12, and is lit on the game effect lamp 9 or the like based on commands and control data from the effect control board 12. It is equipped with a lamp driver circuit that turns off the lights. The driver board 19 is a control board for driving electric components provided separately from the effect control board 12, and various motors included in the effect motor 60 based on commands and control data from the effect control board 12. It is equipped with a driver circuit for controlling the rotation of the above and lighting control of various LEDs included in the effect LED 61. The output signal from the driver board 19 is transmitted toward each motor included in the effect motor 60 and each LED included in the effect LED 61.

In the pachinko gaming machine 1, a predetermined game is performed using a game ball as a game medium, and a predetermined game value can be given based on the game result. As an example of a game using a game ball, a predetermined ball hitting operation handle provided at a lower right position of a game machine frame 3 in the pachinko game machine 1 is determined based on a predetermined operation (for example, a rotation operation) by the player. A gaming ball as a gaming medium is launched toward the gaming area by a launching motor or the like provided in the hitting ball launching device. When a game ball that has flowed down the game area passes (enters) various winning openings, the game ball as a prize ball is paid out. When the variable display result of the special symbol or decorative symbol is "big hit", the big winning opening is opened and the game ball can easily pass (enter), which is an advantageous state for the player. It becomes a big hit game state.

The advantageous state is not limited to the big hit game state, and may include a special game state such as a time saving state or a probability change state. In addition, the maximum number of round games that can be executed in the jackpot game state is the number of first rounds (for example, "15") that is larger than the number of second rounds (for example, "7"), and it can be executed in a time-saving state. The upper limit of the variable display is the first number (for example, "100"), which is larger than the second number (for example, "50"), and the jackpot probability in the probability variation state is higher than the second probability (for example, 1/50). The number of consecutive chans, which is one probability (for example, 1/20) and the number of times that the jackpot game state is repeatedly controlled without being controlled in the normal state, is larger than the number of consecutive chans (for example, "5"). It may include a more favorable gaming situation for the player, such as part or all of the number of consecutive chans (eg, "10").

In the main board 11, when the power supply from the power supply board 92 is started, the CPU 103 of the game control microcomputer 100 is started, and the CPU 103 starts the execution of the game control main process. In the game control main process, the CPU 103 performs necessary initial settings after setting interrupt disable. When the initial setting is completed, interrupt processing is enabled and then loop processing is started. After that, an interrupt request signal is sent from the CTC to the CPU 103 at predetermined time (for example, 2 milliseconds), and the CPU 103 periodically executes the game control timer interrupt process.

The game control timer interrupt processing includes switch processing, main side error processing, information output processing, game random number update processing, special symbol process processing, ordinary symbol process processing, command control processing, and the like. In the switch processing, the state of the detection signals input from various switches is determined. In the error processing on the main side, an abnormality diagnosis of the pachinko gaming machine 1 is performed, and a warning can be generated if necessary. In the information output process, predetermined data supplied to the hall management computer is output. In the game random number update process, at least a part of the game random numbers is updated by software. In the special symbol process process, various processes are selected and executed in order to perform the display control of the special symbol, the opening / closing operation setting of the large winning opening, and the like in a predetermined procedure. In the normal symbol process process, various processes are selected and executed in order to perform display control of the normal symbol, tilting motion setting of the movable wing piece in the normal variable winning ball device 6B, and the like in a predetermined procedure.

In the special symbol process process, first, the start prize determination process is executed. After the start winning determination process is executed, the process selected according to the value of the special figure process flag is executed. The processes that can be selected at this time include special symbol normal processing, variation pattern setting processing, special symbol variation processing, special symbol stop processing, jackpot opening pre-processing, jackpot opening processing, jackpot opening post-processing, jackpot end processing, and the like. I just need to be there.

In the start-up prize determination process, it is determined whether or not the first start-up prize or the second start-up prize has occurred, and if it does occur, a setting for updating the number of reserved special figures is made. In the special symbol normal processing, it is determined whether or not to start the execution of the special symbol game. Further, in the special symbol normal processing, it is determined whether or not the variable display result of the special symbol or the decorative symbol is regarded as a "big hit". Further, in the special symbol normal processing, the finalized special symbol in the special symbol game is set corresponding to the variable display result. In the variation pattern setting process, the variation pattern is determined based on the variable display result and the like. In the special symbol change processing, settings for changing the special symbol, settings for measuring the elapsed time from the start of the change, and the like are performed. In the special symbol stop process, settings are made to stop the fluctuation of the special symbol and to stop display (derive) the confirmed special symbol that is the variable display result.

In the big hit opening pre-processing, the variable display result corresponds to the "big hit", and the setting for opening the big winning opening in the big hit game state is made. In the process of opening the jackpot, it is determined whether or not to return the jackpot from the open state to the closed state. In the jackpot opening post-processing, after returning the jackpot to the closed state, it is determined whether or not the number of round executions has reached the upper limit, and if not, the next round can be executed, and if it has been reached, the next round can be executed. Settings for ending the jackpot game state are made. In the jackpot end process, after waiting until a waiting time corresponding to the execution period of the ending effect for notifying the end of the jackpot game state elapses, settings for starting probability variation control and time saving control are performed.

In the effect control board 12, when the power supply from the power supply board 92 is started, the effect control CPU 120 starts executing the effect control main process. In the effect control main process, after the predetermined initialization is performed, the command analysis process, the effect control process process, and the effect random number update process are executed every time a timer interrupt occurs. In the command analysis process, the effect control command transmitted from the main board 11 is analyzed, and a flag corresponding to the analysis result is set. In the effect control process process, various processes are selected and executed in order to control the electric components for effect according to a predetermined procedure. In the effect random number update process, the count value for generating the effect random number is updated by software.

In the effect control process process, first, the hold display update process is executed. After executing the hold display update process, the process selected according to the value of the effect process flag is executed. The processes that can be selected at this time may include variable display start waiting process, variable display start setting process, variable display in-effect process, variable display stop process, big hit display process, big hit medium effect process, ending effect process, and the like. ..

In the hold display update process, settings for updating the display of the hold storage display area 5H according to the number of special figure hold storages are made. In the variable display start waiting process, it is determined whether or not to start the variable display of the special symbol or the decorative symbol. In the variable display start setting process, settings for starting variable display of the decorative symbol and the like are performed. In the effect processing during variable display, settings for controlling the electric components for effect according to the effect control pattern are made in response to the variable display of the decorative pattern. In the variable display stop process, control is performed such as stopping the variable display of the decorative symbol and deriving a fixed decorative symbol that is a variable display result.

In the big hit display process, the variable display result corresponds to the "big hit", and control for executing an effect (fanfare effect) for notifying the occurrence of the big hit is performed. In the big hit medium effect processing, settings for controlling the electric components for the effect according to the effect control pattern are made in response to the big hit game state. In the ending effect processing, settings for controlling the execution of the ending effect are made in response to the end of the jackpot game state.

FIG. 3 is a rear view of the gaming machine frame 3 included in the pachinko gaming machine 1. A ball tank 150 and a terminal board 154 are provided on the upper back surface of the gaming machine frame 3. Further, a supply passage 151, a payout device 152, and a prize ball passage 153 are also provided. On the back surface of the game board 2, a board case 400 for a game control board, a board case 800 for an effect control board, and a cover body 301 are provided. The board case 400 houses the main board 11. The board case 800 houses the effect control board 12. The cover body 301 is made of a transparent synthetic resin or the like, and covers the substrate case 800 and the upper portion of the substrate case 400. A payout control board 91 and a power supply board 92 are provided so as to overlap each other in the front and rear positions below the board case 400 for the game control board.

The structure of the substrate case 800 for the effect control substrate will be described with reference to FIGS. 4 to 7. FIG. 4 is an exploded perspective view showing a state in which the substrate case 800 is viewed from diagonally above the left rear portion. FIG. 5 is an exploded perspective view showing a state in which the substrate case 800 is viewed from diagonally above the front right portion. FIG. 6 is a six-view view showing the base member 801. FIG. 7 is a six-view view showing the cover member 802. The board case 800 is composed of a base member 801 and a cover member 802, and is assembled so as to sandwich the effect control board 12 from the front and back. The base member 801 covers the front side of the effect control board 12, and the cover member 802 covers the back side of the effect control board 12.

The base member 801 is made of a transparent thermoplastic synthetic resin, and is composed of a base plate 801a formed in a substantially rectangular shape in a vertically long shape, and side walls 801b to 801e erected on the upper, lower, left and right sides toward the back side. , It is formed in a box shape that opens toward the back side. The base plate 801a has bosses 803, 804, locking bars 805, locking hooks 806, locking holes 807, locked portions 808, screw holes 810 for one-way screws 809, mounting holes 811, and ribs for supporting the substrate 812. 813, step portions 814a, 814b, and rib 815 are provided.

The cover member 802 is made of a transparent thermoplastic synthetic resin, and is composed of a base plate 821a formed in a substantially rectangular shape in a vertically long shape, and side walls 821b to 811e erected on the upper, lower, left and right sides toward the back side. , It is formed in a box shape that opens toward the back side. In the base plate 821a, a screw hole 823 into which a screw 822 is screwed, a positioning convex portion 824, a screw hole 826 into which a screw 825 is screwed, a positioning convex portion 827, a locking hook 831, a locking piece 832, and a locking A portion 833, a mounting piece 834 having a mounting hole 834a for the one-way screw 809, a switch opening 835 for the volume adjusting switch 835a to face the outside, and connector openings 836 and 837 are provided.

The connector opening 836 is formed on the upper right side of the base plate 821a so as to have a vertically long shape so that the various substrate-side connectors KCN10 mounted on the first substrate 12A face the outside. The various substrate-side connectors KCN10 may include receptacles KRE1 to KRE4. The receptacle KRE1 is a connector port for wiring the main board. The receptacle KRE2 is a connector port for wiring the power supply board. The receptacle KRE3 is a connector port for wiring the driver board. The receptacle KRE4 is a connector port for wiring the voice control board. The arrangement of the receptacles and the wiring to be connected may be arbitrarily changed according to the specifications of the pachinko gaming machine 1.

The receptacle KRE1 for main board wiring has a configuration of a wiring connection device capable of detachably connecting signal wiring (main board wiring) electrically connected to and from the main board 11. The receptacle KRE2 for power supply board wiring has a configuration of a wiring connection device capable of detachably connecting signal wiring (power supply board wiring) electrically connected to and from the power supply board 92. The receptacle KRE3 for driver board wiring has a configuration of a wiring connection device capable of detachably connecting signal wiring (driver board wiring) electrically connected to and from the driver board 19. The receptacle KRE4 for voice control board wiring has a configuration of a wiring connection device capable of detachably connecting signal wiring (voice control board wiring) electrically connected to and from the voice control board 13.

8 to 10 show a configuration example of the receptacle KRE1. FIG. 8A is a perspective view showing a state viewed from diagonally below the left rear portion. FIG. 8B is a perspective view showing a state seen from diagonally above the left rear portion. FIG. 9 is a rear view showing a state in which the vicinity of the receptacle KRE1 is viewed from the rear side (rear side) outside the cover member 802. FIG. 10 is a cross-sectional view showing a state in which the vicinity of the receptacle KRE1 is viewed from below. The receptacle KRE1 includes a housing in which the insertion port OP1 is formed, and terminals TA01 to TA03.

The insertion port OP1 is an opening to which a connector plug provided in the main board wiring can be inserted and mounted. The terminals TA01 to TA03 are configured by using a metal such as copper, and correspond to a plurality of terminals provided on the connector plug when the connector plug of the main board wiring is inserted into the insertion port OP1. It is a metal member that comes into contact with a terminal arranged at a position and is electrically conductive. In the receptacle KRE1, terminals TA01 and TA03, which are a pair of ground terminals, are surface-mounted on the substrate of the effect control board 12 at positions sandwiching both sides of the terminal TA02, which is a signal terminal. In the main board wiring, a grounding line serving as a pair of grounding voltage lines may be provided at a position sandwiching both sides of the signal line serving as a signal transmission line. Alternatively, a coaxial cable may be used as the main board wiring so that the inner conductor of the coaxial cable is electrically connected to the terminal TA02 and the outer conductor of the coaxial cable is electrically connected to the terminals TA01 and TA03. Good.

In the receptacle KRE1, the terminals TA01 to TA03 are pulled out to the outside on the side surface PL1 which is the terminal arrangement surface, and can be joined to the connection pad provided on the substrate of the effect control substrate 12 (first substrate 12A). The method of joining the terminals to the connection pad may be a metal joining method using solder or the like, or an adhesive joining method such as conductive resin joining or anisotropic conductive member joining. Fixing metal fittings SS01 and SS02 are provided on the side of the side surface PL2, which is the back side of the side surface PL1.

In the cover member 802 of the substrate case 800, of the connector openings 836, the opening region 836a formed corresponding to the receptacle KRE1 has a narrower opening width than the opening region formed corresponding to the other receptacles. It may be formed so as to become. The terminals TA01 to TA03 of the receptacle KRE1 are formed so as to have an exposed portion exposed from the substrate case 800 and a coated portion covered with the substrate case 800 and not exposed in the opening region 836a, respectively. For example, in the terminals TA01 to TA03, the tip portion to be joined to the corresponding connection pad may be included in the covering portion covered with the cover member 802 of the substrate case 800 and not exposed.

If the cover member 802 of the substrate case 800 is integrally formed with the component accommodating portion 802a and the opening peripheral edge portion 840 forming the inner peripheral wall surface 836b serving as the inner end surface in the opening region 836a via the gradient portion 821e1. Good. The component accommodating portion 802a is formed so as to accommodate at least a part of the electric components mounted on the substrate of the effect control substrate 12. In the opening region 836a, the distance between the inner peripheral wall surface 836b and the receptacle KRE1 is such that the distance between the inner peripheral wall surface 836b on the side farther from the component accommodating portion 802a and the side surface PL2 of the receptacle KRE1 is the opening width W1 and the component accommodating portion 802a. The distance between the inner peripheral wall surface 836b on the near side and the side surface PL1 serving as the terminal arrangement surface of the receptacle KRE1 is the opening width W2. The arrangement of the opening region 836a and the receptacle KRE1 may be adjusted so that the opening width W2 is wider than the opening width W1. At the terminals TA01 to TA03 of the receptacle KRE1, the tip portion that is joined to the corresponding connection pad and becomes the surface mount mounting position is covered with the opening peripheral edge portion 840 that forms the inner peripheral wall surface 836b in the opening region 836a. A space SP1 as a space is formed in the cover member 802 by the opening peripheral edge portion 840 and the substrate surface of the effect control substrate 12 in the vicinity of the mounting position of the receptacle KRE1.

The terminal TA01 is joined to the dummy pad DP1 provided on the substrate of the effect control substrate 12. The terminal TA03 is joined to the dummy pad DP2 provided on the substrate of the effect control substrate 12. Further, the terminals TA01 and TA03 are joined to the connection pad GPA1. The connection pad GPA 1 may be connected to the wiring layer LY4 on which the wiring pattern for grounding is formed through the through holes provided in the effect control board 12. The substrate cross section of the effect control substrate 12 shown in FIG. 10 is protected by using, for example, polyimide on the side where the wiring layer LY2 is formed between the insulating layer LY1 and the insulating layer LY3 and the receptacle KRE1 is surface-mounted. It suffices if the layer LY0 is formed. As described above, the wiring pattern on the effect control board 12 may be formed on the wiring layer LY2 provided between the insulating layer LY1 and the insulating layer LY3, which are inner layers in the effect control board 12. Alternatively, the wiring pattern on the effect control board 12 may be surface-formed on the board of the effect control board 12. The terminal TA02 is joined to a connection pad that is electrically connected to a wiring pattern for signal transmission.

The fixing metal fitting SS01 included in the receptacle KRE1 is joined to the dummy pad DP3 provided on the substrate of the effect control substrate 12. The fixing metal fitting SS02 included in the receptacle KRE1 is joined to the dummy pad DP4 provided on the substrate of the effect control substrate 12. In this way, on the side of the side surface PL2 which is the back side of the side surface PL1 where the terminals TA01 to TA03 are arranged, the fixing metal fittings SS01 and SS02 are provided on the substrate of the effect control board 12, and the dummy pads DP3 and DP4 are provided. It suffices to be joined to.

When an effect control command is transmitted from the main board 11 to the effect control board 12, the main board wiring for transmitting the command may have only one signal line as a signal transmission line. .. Correspondingly, in the receptacle KRE1 surface-mounted on the effect control board 12, it is conceivable that only the terminal TA02 serving as the signal terminal is provided. In this case, the area of the joint surface on the substrate of the effect control board 12 according to the width and depth of the receptacle KRE1 is larger than the amount of protrusion of the effect control board 12 from the substrate surface according to the height of the receptacle KRE1. Since it tends to decrease, there is a possibility that sufficient bonding strength cannot be secured by surface mounting of the receptacle KRE1. Therefore, in the receptacle KRE1, the terminals TA01 and TA03, which are a pair of ground terminals, are surface-mounted on the substrate of the effect control board 12 at positions sandwiching both sides of the terminal TA02, which is a signal terminal. This enables an appropriate substrate configuration that can sufficiently secure the bonding strength by surface mounting of the receptacle KRE1. Further, since both sides of the terminal TA02 serving as a signal terminal are sandwiched between the terminals TA01 and TA03 serving as a pair of ground terminals, an appropriate board configuration that is not easily affected by noise becomes possible.

In the receptacle KRE1, the terminal TA01 is joined to the dummy pad DP1 provided on the substrate of the effect control board 12, and the terminal TA03 is joined to the dummy pad DP2 provided on the substrate of the effect control board 12. Further, the tips of the terminals TA01 to TA03 are arranged so as to be covered with the cover member 802 of the substrate case 800. Since the terminals TA01 and TA03 are joined to the dummy pads DP1 and DP2 in this way, an appropriate substrate configuration capable of sufficiently ensuring the joining strength by surface mounting of the receptacle KRE1 becomes possible. Since the tip portions of the terminals TA01 to TA03 are covered with the cover member 802 of the substrate case 800, an appropriate substrate configuration capable of protecting important parts in surface mounting such as a joint portion between the terminal and the substrate surface becomes possible. The terminal TA02, which is a signal terminal, may be joined to the dummy pad or may not be joined to the dummy pad. By preventing the terminal TA02, which is a signal terminal, from being joined to the dummy pad, signal deterioration due to the influence of the conductor shape may be prevented.

In the receptacle KRE1, the fixing metal fitting SS01 is joined to and fixed to the dummy pad DP3 provided on the substrate of the effect control board 12 on the side of the side surface PL2 which is the back side of the side surface PL1 where the terminals TA01 to TA03 are arranged. The metal fitting SS02 is joined to the dummy pad DP4 provided on the substrate of the effect control substrate 12. In this way, since the fixing metal fittings SS01 and SS02 are joined to the dummy pads DP3 and DP4, it is possible to form an appropriate substrate that can sufficiently secure the joining strength by surface mounting of the receptacle KRE1. It should be noted that, regardless of the method of joining metal members such as fixing metal fittings SS01 and SS02 on the substrate, arbitrary fixing such as bonding a fixing member using a synthetic resin similar to the housing of the receptacle KRE1 to the substrate is used. Any material may be used as long as the members can be joined on the substrate.

The component accommodating portion 802a in the cover member 802 of the substrate case 800 is formed so as to accommodate at least a part of the electric components mounted on the substrate of the effect control substrate 12, and includes the inner peripheral wall surface 836b and the receptacle KRE1 in the opening region 836a. The opening width W2 on the side closer to the component accommodating portion 802a is formed wider than the opening width W1 on the far side. The side closer to the component accommodating portion 802a is the side of the side surface PL1 which is the terminal arrangement surface from which the terminals TA01 to TA03 are pulled out in the receptacle KRE1. On the other hand, the side far from the component accommodating portion 802a is the side of the side surface PL2 which is the back side of the terminal arrangement surface in the receptacle KRE1. Therefore, the distance between the inner peripheral wall surface 836b and the receptacle KRE1 in the opening region 836a is the opening width W2 on the side corresponding to the side surface PL1 which is the terminal arrangement surface and the opening width on the side corresponding to the side surface PL2 which is the back surface of the terminal arrangement surface. It is formed wider than W1. Since the opening width is adjusted in this way, it is possible to form an appropriate substrate that allows, for example, the cover member 802 to be easily attached, detached, and aligned. In addition, an appropriate substrate configuration capable of suppressing damage due to collision between the terminal arrangement surface of the receptacle KRE1 and the cover member 802 when the cover member 802 is attached or detached becomes possible.

The terminals TA01 to TA03 of the receptacle KRE1 are formed with an exposed portion that is not covered by the cover member 802 of the substrate case 800 and is exposed by the cover member 802 of the substrate case 800 in the opening region 836a, respectively. To. In this way, unlike the exposed portion, each terminal TA01 to TA03 is formed with a coated portion that is not exposed, so that an important portion in surface mounting such as a joint portion between the terminal and the substrate surface can be protected. Appropriate board configuration is possible.

At the terminals TA01 to TA03 of the receptacle KRE1, the mounting position mounted on the surface of the effect control board 12 so as to be joined to the corresponding connection pad is the opening of the cover member 802 forming the inner peripheral wall surface 836b in the opening region 836a. It is covered by a peripheral edge portion 840. Then, the space SP1 close to the mounting position of the receptacle KRE1 is formed by the opening peripheral edge portion 840 of the cover member 802 and the substrate surface of the effect control board 12. In this way, since the opening peripheral edge portion 840 of the cover member 802 and the substrate surface of the effect control substrate 12 are arranged in a position-adjustable manner, an appropriate substrate configuration capable of protecting the mounting position of the receptacle KRE1 becomes possible.

FIG. 11A shows a transmission path corresponding to the main board wiring. As shown in FIG. 11A, the signal SCD supplied to the terminal TA02 in the receptacle KRE1 for wiring the main board is input to the effect control CPU 120 via the input driver circuit 130. The terminals TA01 and TA03 of the receptacle KRE1 are grounded (connected to the ground line).

FIG. 11B shows a transmission path corresponding to the power supply board wiring. The receptacle KRE2 for wiring the power supply board includes terminals TA11 to TA30. Of these, the terminals TA11 and TA12 and the terminals TA29 and TA30 corresponding to the outside of the receptacle KRE2 are all grounded (connected to the ground line). In addition to the terminals TA11, TA12, TA29, and TA30, the terminals TA25 and TA26 are grounded (connected to the ground line). A DC 34V power supply voltage VSL2 is supplied to the terminals TA13 and TA14 of the receptacle KRE2. A DC 12V power supply voltage VDD2 is supplied to the terminals TA15 to TA20 of the receptacle KRE2. A DC 5V power supply voltage VCS2 is supplied to the terminals TA21 to TA24 of the receptacle KRE2. A DC 12V power supply voltage VDD3 is supplied to the terminals TA27 and TA28 of the receptacle KRE2.

The DC 34V power supply voltage VSL2 supplied from the power supply board 92 to the production control board 12 via the power supply board wiring connected to the receptacle KRE2 for power supply board wiring is directly output from the production control board 12 as the power supply voltage VSL. , It is supplied to the driver board 19 via the driver board wiring connected to the receptacle KRE3 for the driver board wiring. For example, in the receptacle KRE2 for wiring the power supply board, the terminals TA13 and TA14 that receive the supply of the power supply voltage VSL2 are connected to the power supply line LSL, and the power supply line LSL is connected to a predetermined terminal in the receptacle KRE3 for wiring the driver board. .. As shown in FIG. 4, the receptacle KRE2 for wiring the power supply board is provided adjacent to the receptacle KRE3 for wiring the driver board, and the power supply line LSL is an effect control that does not approach the main electric circuits and electric components on the effect control board 12. It may be arranged so as to pass through the end portion of the substrate 12.

FIG. 12 shows a transmission path of the power supply voltage VSL. In the power supply board 92, a power supply voltage VSL2 of DC 34V is generated from a commercial power supply which is an external power supply by using a transformer circuit 501, a DC voltage generation circuit 502, and the like. For example, in the transformer circuit 501, a power supply voltage of AC 24V is generated. The DC voltage generation circuit 502 includes a rectifier circuit and a smoothing circuit, and rectifies and smoothes the AC 24V power supply voltage to generate a DC 34V power supply voltage VSL2. Since the DC 34V power supply voltage VSL2 is not voltage-controlled by feedback control or the like, the DC 34V power supply voltage VSL2 also fluctuates due to fluctuations in the AC 24V power supply voltage. As described above, the DC 34V power supply voltage VSL2 supplied to the terminals TA13 and TA14 of the receptacle KRE2 is a DC voltage having a large fluctuation range (ripple component) without voltage control. On the other hand, it is supplied to the DC 12V power supply voltage VDD2 supplied to the terminals TA15 to TA20 of the receptacle KRE2, the DC 5V power supply voltage VCS2 supplied to the receptacle KRE2 terminals TA21 to TA24, and the terminals TA27 and TA28 of the receptacle KRE2. The DC 12V power supply voltage VDD3 may be any DC voltage that is controlled by feedback control on the power supply board 92 and has a smaller fluctuation range (ripple component) than the DC 34V power supply voltage VSL. ..

In the effect control board 12, the power supply line LSL corresponding to the power supply voltage VSL of DC 34V does not include a stabilizing circuit such as a filter circuit for stabilizing the voltage. On the other hand, in the driver board 19, a DC 34V power supply voltage VSL is input to the filter circuit 511 to stabilize the voltage. Further, in the effect control board 12, a stabilizing circuit for stabilizing the voltage by a filter circuit or the like is interposed in the power supply line corresponding to the power supply voltage different from the power supply voltage VSL of DC 34V.

For example, in the receptacle KRE2 for wiring the power supply board, the terminals TA15 to TA20 to which the power supply voltage VDD2 of DC 12V is supplied are connected to the filter circuit 131a, and the terminals TA21 to TA24 to which the power supply voltage VCS2 of DC 5V is supplied are filters. The terminals TA27 and TA28, which are connected to the circuit 131b and to which the DC 12V power supply voltage VDD3 is supplied, are connected to the filter circuit 131c. The output section of the filter circuit 131a is connected to the power supply line LDS that supplies the DC 12V power supply voltage VDS, and the output section of the filter circuit 131b is connected to the power supply line LCC that supplies the DC 5V power supply voltage VCS. The output unit is connected to a power supply line LDC that supplies a DC 12V power supply voltage VDC. In this way, the filter circuit 131a is interposed between the terminals TA15 to TA20 of the receptacle KRE2 and the power supply line LDS corresponding to the power supply voltage VDS of DC 12V, and the filter circuit 131b is interposed between the terminals TA21 to TA24 of the receptacle KRE2 and the power supply voltage of DC 5V. It is interposed between the power supply line LCC corresponding to the VCS, and the filter circuit 131c is interposed between the terminals TA27 and TA28 of the receptacle KRE2 and the power supply line LDC corresponding to the DC 12V power supply voltage VDC.

The power supply line LSL is provided to supply a power supply voltage VSL of DC 34V. The power supply line LDS is provided to supply a DC 12V power supply voltage VDS. The power supply line LCC is provided to supply a DC 5V power supply voltage VCS. The power supply line LDC is provided to supply a power supply voltage VDC of DC 12V. Therefore, the power supply line LSL without the filter circuit is provided to supply a higher power supply voltage as compared with any of the power supply lines LDS, LCC, and LDC with the filter circuit.

In the receptacle KRE2, six terminals TA15 to TA20 to which a DC 12V power supply voltage VDD2 is supplied, four terminals TA21 to TA24 to which a DC 5V power supply voltage VCS2 is supplied, and two terminals to which a DC 12V power supply voltage VDD3 is supplied. While the terminals TA27 and TA28 are provided, the two terminals TA13 and TA14 to which the DC 34V power supply voltage VSL2 is supplied are provided. Therefore, in the receptacle KRE2, among the terminals to which the power supply voltage is supplied, the number of terminals TA15 to TA20, TA21 to TA24, TA27, and TA28 connected to the filter circuit is not connected to the filter circuit. It is larger than the number of terminals of TA14. The number of terminals corresponding to each power supply voltage may be set according to the power supply capacity and the load current.

In the receptacle KRE2, the DC 12V power supply voltage VDD2 is supplied to the terminals TA15 to TA20, the DC 5V power supply voltage VCS2 is supplied to the terminals TA21 to TA24, and the DC 12V power supply voltage VDD3 is supplied to the terminals TA27 and TA28. Then, a DC 34V power supply voltage VSL2 is supplied to the terminals TA13 and TA14. A filter circuit 131a is interposed between the terminals TA15 to TA20 of the receptacle KRE2 and the power supply line LDS for supplying the DC 12V power supply voltage VDS, and supplies the receptacle KRE2 terminals TA21 to TA24 and the DC 5V power supply voltage VCS. A filter circuit 131b is interposed between the power supply line LCC, and a filter circuit 131c is interposed between the terminals TA27 and TA28 of the receptacle KRE2 and the power supply line LDC for supplying a DC 12V power supply voltage VDC. On the other hand, no filter circuit is interposed between the terminals TA13 and TA14 of the receptacle KRE2 and the power supply line LSL for supplying the power supply voltage VSL of DC 34V. In this way, the power supply lines LDS, LCC, and LDC with the filter circuit intervening can supply a plurality of types of power supply voltages such as DC 12V or DC 5V, and the power supply line LSL without the filter circuit is one type of DC 34V. Power supply voltage can be supplied. In the receptacle KRE2, the terminals TA13 and TA14 are arranged outside the terminals TA15 to TA24 and the like. Alternatively, the receptacle KRE2 includes terminals arranged inside the terminals TA13 and TA14, such as terminals TA15 to TA24, among the terminals TA15 to TA24, TA27, and TA28.

In the receptacle KRE2, terminals TA13 to TA24, TA27, and TA28 are arranged between the terminals TA11 and TA12 and the terminals TA29 and TA30. The terminals TA13 to TA24, TA27, and TA28 are all terminals to which a power supply voltage is supplied, and are power supply voltage terminals connected to various power supply voltages. On the other hand, the terminals TA11 and TA12 and the terminals TA29 and TA30 are terminals to which the power supply voltage is not supplied, and are ground terminals connected to the ground voltage. Therefore, in the receptacle KRE2, terminals TA13 to TA24, TA27, and TA28 that serve as power supply voltage terminals are arranged between the terminals TA11 and TA12 that serve as ground terminals and the terminals TA29 and TA30.

In the receptacle KRE2, the terminals TA13 and TA14 and the terminals TA15 to TA24 are arranged between the terminals TA11 and TA12 and the terminals TA25 and TA26, and the terminals are located between the terminals TA25 and TA26 and the terminals TA29 and TA30. TA27 and TA28 are arranged. The terminals TA13 and TA14 are terminals to which a DC 34V power supply voltage VSL2 is supplied, and are power supply voltage terminals connected to the power supply voltage VSL2. Terminals TA15 to TA20 are terminals to which a DC 12V power supply voltage VDD2 is supplied, and are power supply voltage terminals connected to the power supply voltage VDD2. The terminals TA21 to TA24 are terminals to which a DC 5V power supply voltage VCS2 is supplied, and are power supply voltage terminals connected to the power supply voltage VCS2. The terminals TA27 and TA28 are terminals to which a DC 12V power supply voltage VDD3 is supplied, and are power supply voltage terminals connected to the power supply voltage VDD3. Therefore, the terminals TA13 and TA14 as power supply voltage terminals connected to the DC 34V power supply voltage VSL2 and the terminals TA15 to TA24, TA27, TA28 as power supply voltage terminals connected to a power supply voltage other than the DC 34V power supply voltage VSL2. Terminals TA15 to TA24, which are a part of the above, are arranged between terminals TA11 and TA12 and terminals TA25 and TA26 which are ground terminals. Further, among the terminals TA15 to TA24, TA27, and TA28 as power supply voltage terminals connected to a power supply voltage other than the DC 34V power supply voltage VSL2, the other terminals TA27 and TA28 serve as ground terminals. It is arranged between the TA25 and TA26 and the terminals TA29 and TA30.

The DC 12V power supply voltage VDD3 supplied to the terminals TA27 and TA28 is used to generate a DC 1.05V power supply voltage by the buck converter circuit 132. The DC 1.05V power supply voltage is supplied to a specific microprocessor, for example, the graphics processor of the display control unit 123. Therefore, in the receptacle KRE2, among the terminals TA13 to TA24, TA27, and TA28 connected to the power supply voltage, the terminals TA13 and TA14 connected to the DC 34V power supply voltage VSL2 having a relatively large fluctuation width (ripple component) are , TA27, TA28 connected to the DC 12V power supply voltage VDD3 used to generate the power supply voltage to be supplied to a specific microprocessor such as the graphics processor of the display control unit 123.

In the effect control board 12, it is conceivable that the power supply voltage VSL2 of DC 34V is stabilized and then output as the power supply voltage VSL. However, the installation of the circuit element that stabilizes the DC 34V power supply voltage VSL2, which is not directly used in the effect control board 12, causes an increase in the number of parts and the board volume, and also increases the power loss and the manufacturing cost. Further, the installation of a special circuit element may make it difficult to reuse or standardize the effect control board 12. Therefore, the DC 34V power supply voltage VSL2 for which voltage control is not performed is output as it is as the power supply voltage VSL from the effect control board 12, and is input to the filter circuit 511 on the driver board 19 to stabilize the voltage. This enables an appropriate board configuration that prevents an increase in the number of parts and a board volume, and an increase in power loss and manufacturing cost. In addition, an appropriate board configuration that allows easy reuse and common use of the effect control board 12 becomes possible. Further, the power supply line LSL is arranged away from the main electric circuits and electric components in the effect control board 12, so that an appropriate board configuration for preventing the adverse effect of noise due to a DC voltage having a large fluctuation width (ripple component) is provided. It will be possible.

In the production control board 12, the power supply line LSL for supplying the DC 34V power supply voltage VSL includes a power supply line LDS for supplying the DC 12V power supply voltage VDS, a power supply line LCC for supplying the DC 5V power supply voltage VCS, and a DC 12V power supply. Compared with any of the power supply line LDSs that supply the voltage VDS, DC 34V, which is a high power supply voltage, is supplied. In general, a stabilizing circuit that stabilizes a high power supply voltage tends to have a larger volume and power loss of a circuit element than a stabilizing circuit that stabilizes a low power supply voltage, and the cost of the circuit element is high. It is easy to become a thing. Therefore, by not interposing a filter circuit in the power supply line LSL that supplies the DC 34V power supply voltage VSL, which is a high power supply voltage, an appropriate board configuration that prevents an increase in board volume, power loss, and an increase in manufacturing cost is possible. become.

In the receptacle KRE2, a DC 34V power supply voltage VSL is supplied to the two terminals TA13 and TA14. On the other hand, in the receptacle KRE2, the six terminals TA15 to TA20 are supplied with a DC 12V power supply voltage VDD2, the four terminals TA21 to TA24 are supplied with a DC 5V power supply voltage VCS2, and the two terminals TA27 and TA28 are supplied. Is supplied with a DC 12V power supply voltage VDD3. Therefore, in the effect control board 12, among the terminals to which the power supply voltage is supplied by the receptacle KRE2, the number of terminals of the terminals TA15 to TA24, TA27, and TA28 connected to any of the filter circuits 131a to 131c is the filter circuit. The number of terminals is larger than the number of terminals TA13 and TA14 that are not connected to. Since the number of terminals is set in this way, for example, an appropriate board for improving the degree of freedom in wiring design according to the application of the power supply voltage to be stabilized by the effect control board 12 and the power supply capacity. Configuration is possible.

Among the terminals to which the power supply voltage is supplied in the receptacle KRE2, the terminals TA15 to TA24, TA27, and TA28 connected to any of the filter circuits 131a to 131c on the effect control board 12 have a DC 12V power supply voltage VDD2. The terminals TA15 to TA20 that can be supplied, the terminals TA21 to TA24 that can supply the DC 5V power supply voltage VCS2, and the terminals TA27 and TA28 that can supply the DC 12V power supply voltage VDD3 are included. On the other hand, among the terminals to which the power supply voltage is supplied in the receptacle KRE2, the terminals TA13 and TA14, which are not connected to the filter circuit in the effect control board 12, can supply the power supply voltage VSL2 of DC 34V, and are of other types. Power supply voltage is not supplied. Therefore, the number of types of power supply voltages that can be supplied differs depending on whether the power supply line has a filter circuit or not. More specifically, the power supply line in which the filter circuit is interposed can supply a plurality of types of power supply voltages such as a DC 12V power supply voltage VDD2, a DC 5V power supply voltage VCS2, and a DC 12V power supply voltage VDD2. The power supply line without intervening can supply one kind of power supply voltage of DC 34V power supply voltage VSL. In this way, since the number of types of power supply voltage that can be supplied differs according to the power supply line, the wiring design can be freely selected according to, for example, the application of the power supply voltage for which the voltage is stabilized by the effect control board 12. Appropriate board configuration to improve the degree is possible.

Further, the terminals TA13 and TA14 connected to the power supply line not intervening the filter circuit are arranged outside the terminals TA15 to TA24 connected to the power supply line intervening the filter circuit. Such an arrangement of terminals enables an appropriate board configuration for improving the degree of freedom in wiring design, for example, depending on the application of the power supply voltage for which the voltage is stabilized in the effect control board 12. In addition, an appropriate board configuration for shortening the wiring length for outputting the DC 34V power supply voltage VSL2 supplied to the terminals TA13 and TA14 to the driver board 19 as the power supply voltage VSL as it is becomes possible.

In the receptacle KRE2, the terminals TA13 to TA24, TA27, and TA28 are power supply voltage terminals connected to various power supply voltages. On the other hand, in the receptacle KRE2, the terminals TA11 and TA12 and the terminals TA29 and TA30 are all ground terminals connected to the ground voltage. The terminals TA13 to TA24, TA27, and TA28 are arranged between the terminals TA11 and TA12 and the terminals TA29 and TA30. Such an arrangement of terminals enables an appropriate board configuration that is not easily affected by noise. In addition, an appropriate substrate configuration that shields the power supply voltage and prevents the generation of noise becomes possible.

In the receptacle KRE2, the terminals TA15 to TA24, TA27, and TA28 are first power supply voltage terminals connected to a power supply voltage different from the power supply voltage VSL2 of DC 34V. On the other hand, in the receptacle KRE2, the terminals TA13 and TA14 are second power supply voltage terminals connected to the power supply voltage VSL2 of DC 34V. Further, in the receptacle KRE2, the terminals TA11 and TA12 are the first ground terminals connected to the ground voltage, the terminals TA25 and TA26 are the second ground terminals connected to the ground voltage, and the terminals TA29 and TA30 are connected to the ground voltage. It becomes the third grounding terminal. In the receptacle KRE2, the terminals TA13 and TA14 included in the second power supply voltage terminal and the terminals TA15 to TA24 included in the first power supply voltage terminal are the terminals TA11 and TA12 included in the first ground terminal, and the second The terminals TA27 and TA28 arranged between the terminals TA25 and TA26 included in the ground terminal and included in the first power supply voltage terminal are included in the terminals TA25 and TA26 included in the second ground terminal and the third ground terminal. It is arranged between the terminals TA29 and TA30. Such an arrangement of terminals enables an appropriate board configuration that is not easily affected by noise. In particular, the terminals TA25 and TA26 included in the second ground terminal are included in the terminals TA13 and TA14 included in the second power supply voltage terminal, the terminals TA15 to TA24 included in the first power supply voltage terminal, and the first power supply voltage terminal. By arranging it between TA27 and TA28, it is possible to form an appropriate substrate that is less susceptible to noise. In addition, an appropriate substrate configuration that efficiently shields the power supply voltage and further prevents the generation of noise becomes possible. In addition, the terminals TA13 and TA14 connected to the DC 34V power supply voltage VSL2 are connected to the DC 12V power supply voltage VDD3 used to generate the power supply voltage to be supplied to a specific microprocessor such as the graphics processor of the display control unit 123. Since the TA27 and TA28 are arranged apart from each other, an appropriate board configuration in which a specific microprocessor is less susceptible to noise is possible.

In the effect control board 12, the power supply voltage VDC is branched at the branch point DB1 from the power supply voltage VDD2 supplied at the terminals TA15 to TA20 of the receptacle KRE2. After the power supply voltage VDL is branched at such a branch point DB1, the power supply voltage VDS is stabilized by the filter circuit 131a. The power supply voltage VDC is a DC 12V power supply voltage used for driving a specific electric component such as a specific LED included in the effect LED 61. The power supply voltage VDS is a DC 12V power supply voltage supplied to the amplifier circuit 521 and used to output an audio signal. In this way, the filter circuit 131a stabilizes the power supply voltage VDS after branching the power supply voltage VDD2 of 1 into the power supply voltage VDL and the power supply voltage VDS. An amplifier circuit 521 may be provided on the effect control board 12 so that the audio signals supplied to the speakers 8L and 8R can be output.

FIG. 13A shows the relationship between the wiring lengths in the wiring for supplying the power supply voltage VDS. In the effect control board 12, the power supply line LDS for supplying the power supply voltage VDS to the amplifier circuit 521 is a wiring having a wiring length LL1 from the branch point DB1 to the input portion of the filter circuit 131a and the output portion of the filter circuit 131a. The wiring having the wiring length LL2 to the input portion of the amplifier circuit 521 may be included. Then, the arrangement of the wiring and the circuit on the effect control board 12 may be adjusted so that the wiring length LL2 is shorter than the wiring length LL1. As described above, the wiring length LL2 from the filter circuit 131a to the amplifier circuit 521 is shorter than the wiring length LL1 from the branch point DB1 of the power supply voltage VDS to the filter circuit 131a. The amplifier circuit 521 and the filter circuit 131a are not limited to those installed on the effect control board 12, and may be installed on the voice control board 13.

FIG. 13B shows a transmission path of the power supply voltage VDS when the amplifier circuit 521 and the filter circuit 131a are installed on the voice control board 13. In the power supply board 92, a DC voltage 12V power supply voltage VDD2 is generated from a commercial power supply which is an external power supply by using a transformer circuit 501, a DC voltage generation circuit 502, and the like. The DC 12V power supply voltage VDD2 is supplied to the terminals TA15 to TA20 in the receptacle KRE2 for wiring the power supply board. In the effect control board 12, after the power supply voltage VDC is branched at the branch point DB1 from the power supply voltage VDD2 supplied at the terminals TA15 to TA20 of the receptacle KRE2, the effect control board 12 outputs the power supply voltage VDS as it is. It may be supplied to the voice control board 13 via the voice control board wiring connected to the receptacle KRE4 for the voice board wiring. For example, in the receptacle KRE2 for wiring the power supply board, the terminals TA15 to TA20 that receive the supply of the power supply voltage VDD2 are connected to the power supply line LDS, and the power supply line LDS is connected to a predetermined terminal in the receptacle KRE4 for wiring the voice control board. Just do it. In the effect control board 12, the power supply line LDS corresponding to the power supply voltage VDS of DC 12V does not have to intervene with a stabilizing circuit such as a filter circuit for stabilizing the voltage. On the other hand, in the voice control board 13, a DC 12V power supply voltage VDS is input to the filter circuit 131a to stabilize the voltage. The power supply voltage VDS thus stabilized may be supplied to the amplifier circuit 521.

The voice control board 13 may be provided with a voice control IC 522, a voice data ROM 523, and the like. The voice control IC 522 executes signal processing for generating voices and sound effects in response to commands (sound number data, etc.) output from the effect control CPU 120 of the effect control board 12. The voice data ROM 523 stores control data corresponding to the sound number data. The control data according to the phone number data is a collection of data showing the output mode of voice and sound effect in a predetermined period (for example, a variable display period of a decorative symbol) in chronological order. It should be noted that various configurations provided on the voice control board 13 may be configured to be provided on the effect control board 12 and may not include the voice control board 13.

The amplifier circuit 521, which can amplify the audio signal generated by the audio control IC522 or the like and output it to the speakers 8L, 8R, etc., has a sound quality such that the output audio signal is distorted when the power supply voltage fluctuates. May be adversely affected. Therefore, the DC 12V power supply voltage VDS is supplied to the amplifier circuit 521 after being stabilized by the filter circuit 131a. In the effect control board 12, the power supply voltage VDD2 of 1 is branched into a power supply voltage VDC for driving a specific electric component and a power supply voltage VDS for supplying the amplifier circuit 521, and then the filter circuit 131a is used. The stabilized power supply voltage VDS is supplied to the amplifier circuit 521. By supplying the stabilized power supply voltage VDS to the amplifier circuit 521 using the filter circuit 131a in this way, an appropriate substrate configuration for stably operating the amplifier circuit 521 becomes possible.

In the power supply line LDS corresponding to the power supply voltage VDS for supplying to the amplifier circuit 521, the wiring length LL2 from the filter circuit 131a to the amplifier circuit 521 is transferred to the filter circuit 131a after the power supply voltage VDC is branched at the branch point DB1. The wiring length until input is shorter than LL1. In this way, by shortening the wiring length until the power supply voltage VDS stabilized by using the filter circuit 131a is supplied to the amplifier circuit 521, it is less susceptible to noise and the amplifier circuit 521 is operated stably. It is possible to configure various boards.

In the effect control board 12, the power supply voltage VCL is branched from the power supply voltage VCS2 supplied at the terminals TA21 to TA24 of the receptacle KRE2. After the power supply voltage VCL is branched, the power supply voltage VCS is stabilized by the filter circuit 131b. The power supply voltage VCL is a DC 5V power supply voltage used to drive a specific electric component such as a specific motor included in the effect motor 60 or a specific LED included in the effect LED 61. The power supply voltage VCS is a DC power supply of 5 V DC used for driving a predetermined electric circuit such as the effect control CPU 120. In this way, the filter circuit 131b stabilizes the power supply voltage VDD after the power supply voltage VCS2 of 1 is branched into the power supply voltage VCL and the power supply voltage VDD.

In the effect control board 12, the power supply voltage VDD3 supplied at the terminals TA27 and TA28 of the receptacle KRE2 is stabilized by the filter circuit 131c, and then the power supply voltage VDC is branched so that it can be supplied. The power supply voltage VDC is a DC 12V power supply voltage used for monitoring the occurrence of a power failure. Further, the power supply voltage VDD3 is input to the buck converter circuit 132 after being stabilized by the filter circuit 131c. The buck converter circuit 132 is a circuit that converts a DC voltage of 1 input and 2 outputs. The buck converter circuit 132 shown in FIG. 11 receives a DC 12V power supply voltage VDD3 stabilized by the filter circuit 131c and converts it into a DC 1.05V power supply voltage and a DC 3.3V power supply voltage. And output. The output unit of the buck converter circuit 132 is connected to a power supply line L10 that supplies a power supply voltage of 1.05 V DC and a power supply line L33 that supplies a power supply voltage of 3.3 V DC. The DC 1.05V power supply voltage is used to drive a predetermined electric circuit, for example, a graphics processor included in the display control unit 123. The DC 3.3V power supply voltage is used to drive a predetermined electric circuit such as the ROM 121 or the image data memory included in the display control unit 123. The DC 3.3V power supply voltage is also input to the regulator circuit 133. The regulator circuit 133 may be a linear regulated power supply circuit such as a series regulator such as an LDO (Low Drop-Out) regulator, and a DC 3.3V power supply voltage is input to the DC 1.5V power supply voltage. Convert to and output. The output unit of the regulator circuit 133 is connected to a power supply line L15 that supplies a power supply voltage of DC 1.5V. The DC 1.5V power supply voltage is used to drive a predetermined electrical circuit, such as the RAM 122.

FIG. 14 shows a configuration example of the filter circuits 131a to 131c. FIG. 14A shows a configuration example of the filter circuit 131a corresponding to the power supply voltage VDS. FIG. 14B shows a configuration example of the filter circuit 131b corresponding to the power supply voltage VCS. FIG. 14C shows a configuration example of the filter circuit 131c corresponding to the power supply voltage VDC.

The filter circuit 131a shown in FIG. 14A may be configured by using a three-terminal capacitor 85a, bypass capacitors C10 and C11, and an electrolytic capacitor C1. The bypass capacitors C10 and C11 are electrical components for noise suppression that prevent high-frequency noise as compared with the electrolytic capacitor C1, and are also called decoupling capacitors. The electrolytic capacitor C1 is an electrical component for noise suppression that prevents low-frequency noise as compared with bypass capacitors C10 and C11. The input terminal (IN) of the three-terminal capacitor 85a serves as an input portion of the filter circuit 131a, and a DC 12V power supply voltage VDD2 is supplied. The output terminal (OUT) of the three-terminal capacitor 85a serves as an output unit of the filter circuit 131a, and supplies a DC 12V power supply voltage VDS with a stabilized voltage. The ground terminal (GND) of the three-terminal capacitor 85a is grounded (connected to the ground line). A 0.1 μF bypass capacitor C10, a 47 μF bypass capacitor C11, and a 1000 μF electrolytic capacitor C1 are connected between the output terminal and the ground terminal of the three-terminal capacitor 85a.

The filter circuit 131b shown in FIG. 14B may be configured by using a three-terminal capacitor 85b, bypass capacitors C12 and C13, and an electrolytic capacitor C2. The bypass capacitors C12 and C13 are electrical components for noise suppression that prevent high-frequency noise as compared with the electrolytic capacitor C2. The electrolytic capacitor C2 is an electrical component for noise suppression that prevents low-frequency noise as compared with bypass capacitors C12 and C13. The input terminal (IN) of the three-terminal capacitor 85b serves as an input portion of the filter circuit 131b, and a DC 5V power supply voltage VCS2 is supplied. The output terminal (OUT) of the three-terminal capacitor 85b serves as an output unit of the filter circuit 131b, and supplies a DC 5V power supply voltage VCS whose voltage is stabilized. The ground terminal (GND) of the three-terminal capacitor 85b is grounded (connected to the ground line). A 0.1 μF bypass capacitor C12, a 47 μF bypass capacitor C13, and a 1000 μF electrolytic capacitor C2 are connected between the output terminal and the ground terminal of the three-terminal capacitor 85b.

The filter circuit 131c shown in FIG. 14C may be configured by using the three-terminal capacitor 85c, the bypass capacitor C14, and the electrolytic capacitor C3. The bypass capacitor C14 is an electrical component for noise suppression that prevents high-frequency noise as compared with the electrolytic capacitor C3. The electrolytic capacitor C3 is an electrical component for noise suppression that prevents low-frequency noise as compared with the bypass capacitor C14. The input terminal (IN) of the three-terminal capacitor 85c serves as an input unit of the filter circuit 131c, and a DC 12V power supply voltage VDD3 is supplied. The output terminal (OUT) of the three-terminal capacitor 85c serves as an output unit of the filter circuit 131c, and supplies a DC 12V power supply voltage VDC with a stabilized voltage. The ground terminal (GND) of the three-terminal capacitor 85c is grounded (connected to the ground line). A 0.1 μF bypass capacitor C14 and a 1000 μF electrolytic capacitor C3 are connected between the output terminal and the ground terminal of the three-terminal capacitor 85c.

The filter circuits 131a to 131c function as stabilizing circuits for stabilizing the voltage of each power supply path. For example, the filter circuit 131a stabilizes the DC 12V power supply voltage VDS supplied by the power supply line LDS. The filter circuit 131b stabilizes the DC 5V power supply voltage VCS supplied by the power supply line LCC. The filter circuit 131c stabilizes the DC 12V power supply voltage supplied by the power supply line LDC. In addition to the filter circuits 131a to 131c, the effect control board 12 may be provided with a noise prevention circuit for preventing the generation of noise at various power supply voltages.

FIG. 15 shows a configuration example of a noise prevention circuit provided on the effect control board 12. FIG. 15A shows a configuration example of the noise prevention circuit 135a corresponding to the LED DC 12V (DC 12V) called the power supply voltage VDC. FIG. 15B shows a configuration example of the noise prevention circuit 135b corresponding to the LED / motor DC5V (DC5V) of the power supply voltage VCL. FIG. 15C shows a configuration example of a noise prevention circuit 135c corresponding to an IC DC 5V (DC 5V) having a power supply voltage VCS and an IC DC 3.3V (DC 3.3V) having a power supply voltage of DC 3.3V. ing.

The noise prevention circuit 135a shown in FIG. 15A is configured by using a capacitor C20 and a resistor R20 connected in series, a capacitor C21 and a resistor R21 connected in series, and a capacitor C22 and a resistor R22 connected in series. I just need to be there. All of these configurations may be connected to the power supply line LDL that supplies the power supply voltage VDC and the ground line that provides the ground voltage. The capacitors C20, C21, and C22 may all be 0.1 μF bypass capacitors. The resistors R20, R21, and R22 may all have a resistance value of 22Ω.

The noise prevention circuit 135b shown in FIG. 15B may be configured by using the capacitor C23 and the resistor R23 connected in series and the capacitor C24 and the resistor R24 connected in series. All of these configurations may be connected to the power supply line LCL that supplies the power supply voltage VCL and the ground terminal (ground line) that provides the ground voltage. Both the capacitors C23 and C24 may be 0.1 μF bypass capacitors. The resistors R23 and R24 may both have a resistance value of 22Ω.

The noise prevention circuit 135c shown in FIG. 15C may be configured by using capacitors C25 to C28. The capacitor C25 may be connected to the power supply line LCC that supplies the power supply voltage VCS and the ground terminal (ground line) that provides the ground voltage. The capacitors C26, C27, and C28 may all be connected to a power supply line L33 that supplies a power supply voltage of 3.3 V DC and a ground terminal (ground line) that provides a ground voltage. The capacitors C25 to C28 may be any bypass capacitor of 0.1 μF.

In the noise prevention circuit 135a shown in FIG. 15A, resistors R20, R21, and R22 are used in addition to the capacitors C20, C21, and C22. In the noise prevention circuit 135b shown in FIG. 15B, resistors R23 and R24 are used in addition to the capacitors C23 and C24. On the other hand, in the noise prevention circuit 135c shown in FIG. 15C, capacitors C25 to C28 are used, and resistors are not used. As described above, in the noise prevention circuits 135a and 135b, resistors R20, R21 and R22 and resistors R23 and R24 are used as circuit elements different from the noise prevention circuit 135c.

The power supply voltage VDC stabilized by the noise prevention circuit 135a shown in FIG. 15A is used to drive a specific electric component such as a specific LED included in the effect LED 61. The power supply line LDL supplies a power supply voltage VDC for driving a specific electrical component, for example, a specific LED included in the effect LED 61. The power supply voltage VCL stabilized by the noise prevention circuit 135b shown in FIG. 15B drives specific electric components such as a specific motor included in the effect motor 60 and a specific LED included in the effect LED 61. Used to do. The power supply line LCL supplies a power supply voltage VCL for driving a specific electric component such as a specific motor included in the effect motor 60 or a specific LED included in the effect LED 61. The power supply voltage VCC and the power supply voltage of DC 3.3V stabilized by the noise prevention circuit 135c shown in FIG. 15C are specified, for example, the effect control CPU 120, the ROM 121, or the image data memory included in the display control unit 123. It is used to drive an electric circuit including a control circuit of. The power supply line LCC supplies a power supply voltage VCS for driving an electric circuit including a specific control circuit, for example, an effect control CPU 120. The power supply line L33 supplies a DC 3.3V power supply voltage for driving an electric circuit including a specific control circuit, such as a ROM 121 or an image data memory of a display control unit 123. In this way, in the noise prevention circuits 135a and 135b corresponding to the power supply voltage for driving a specific electric component such as a motor and an LED, noise prevention corresponding to the power supply voltage for driving a specific electric circuit such as a CPU or ROM is provided. Resistors R20, R21, R22 and resistors R23, R24 are used as circuit elements different from the circuit 135c.

In a load circuit using a current-driven circuit element such as a specific motor included in the effect motor 60 or a specific LED included in the effect LED 61, an excessive inrush current is generated due to a transient phenomenon of the load circuit. , There is a risk of damage to electrical parts. Therefore, in the noise prevention circuit 135a, the resistor R20 is connected in series to the capacitor C20, the resistor R21 is connected in series to the capacitor C21, and the resistor R22 is connected in series to the capacitor C22. Further, in the noise prevention circuit 135b, the resistor R23 is connected in series to the capacitor C23, and the resistor R24 is connected in series to the capacitor C24. When the power supply voltage VDC is stable, the capacitors C20, C21, and C22 are in a charged state, and the resistors R20, R21, and R22 are in a non-conducting state, so that the occurrence of power loss can be prevented. When the power supply voltage VCL is stable, the capacitors C23 and C24 are in a charged state, and the resistors R23 and R24 are in a non-conducting state, so that the occurrence of power loss can be prevented. On the other hand, in semiconductor integrated circuits such as the effect control CPU 120 and ROM 121 or the image data memory of the display control unit 123, voltage-driven circuit elements such as CMOS circuits are used, and the input impedance becomes relatively large. Therefore, an inrush current due to a transient phenomenon of the circuit is unlikely to occur. Therefore, in the noise prevention circuit 135c, while the capacitors C25 to C28 are used, it is not necessary to use a resistor. In this way, by constructing a noise prevention circuit using different circuit elements according to the characteristics of the circuit to which the power supply voltage is supplied and the characteristics of the electric component, noise is prevented while preventing an increase in the substrate volume and an increase in the manufacturing cost. Appropriate board configuration to prevent the occurrence becomes possible.

FIG. 16 shows a power supply monitoring circuit 140 using a power supply voltage VDC. In the effect control board 12, the power supply voltage VDC is used to monitor the occurrence of power failure. The power supply monitoring circuit 140 is a circuit that is configured by using, for example, a power failure monitoring reset module IC and realizes a power supply monitoring means capable of outputting a power supply cutoff signal. For example, the power supply monitoring circuit 140 outputs a power supply cutoff signal in an off state (high level) when the power supply voltage VDC exceeds a predetermined value (for example, 10V). On the other hand, when the period in which the power supply voltage VDC becomes equal to or lower than a predetermined value continues for a predetermined standby time or longer, the power supply cutoff signal in the on state (low level) is output. The power supply cutoff signal output from the power supply monitoring circuit 140 is transmitted to the effect control CPU 120.

The power supply voltage VDC to be monitored for outputting the power supply cutoff signal is used to generate a power supply voltage of DC 1.05 V, a power supply voltage of DC 3.3 V, and a power supply voltage of DC 1.5 V. The DC 1.05V power supply voltage is used to drive a predetermined electric circuit, for example, a graphics processor included in the display control unit 123. The DC 3.3V power supply voltage is used to drive a predetermined electric circuit such as the ROM 121 or the image data memory included in the display control unit 123. The DC 1.5V power supply voltage is used to drive a predetermined electrical circuit, such as the RAM 122. By monitoring the power supply voltage VDC used to generate the power supply voltage supplied to such an electric circuit, a power supply cutoff signal is output (turned on) before the operating state of the electric circuit becomes unstable. Therefore, it is possible to prevent malfunctions in various electric circuits.

In the effect control board 12, the power supply voltage VDD3 supplied by the terminals TA27 and TA28 of the receptacle KRE2 is stabilized by the filter circuit 131c and then input to the buck converter circuit 132. The buck converter circuit 132 uses the input voltage to generate a DC 1.05 V power supply voltage and a DC 3.3 V power supply voltage higher than the DC 1.05 V. The DC 3.3V power supply voltage is input to the regulator circuit 133. The regulator circuit 133 uses the input voltage to generate a DC 1.5V power supply voltage. The power supply voltage of DC 1.5V is higher than DC 1.05V but lower than DC 3.3V. Thus, using the step-down converter circuit 132 and the regulator circuit 133, the DC 1.05V power supply voltage, the DC 1.5V power supply voltage higher than the DC 1.05V, and the DC 3 higher than the DC 1.5V A power supply voltage of .3V can be generated, and the buck converter circuit 132 outputs a power supply voltage of 1.05V DC and a power supply voltage of 3.3V DC, while the regulator circuit 133 outputs a DC 1. Outputs a 5V power supply voltage.

After stabilizing the power supply voltage VDD3 by the filter circuit 131c, the branched DC 12V power supply voltage VDC is supplied to the power supply monitoring circuit 140 that monitors the occurrence of power failure. Therefore, the input voltage of the buck converter circuit 132 is common to the DC 12V power supply voltage VDC, and the input voltage of the buck converter circuit 132 is monitored by the power supply monitoring circuit 140. After branching the power supply voltage VDC, a bypass capacitor having a predetermined capacitance (for example, 47 μF) may be connected to the input side of the buck converter circuit 132.

Among the power supply voltages generated by using the buck converter circuit 132 and the regulator circuit 133, the power supply voltage of DC 1.05 V, which is the lowest voltage with the smallest voltage value, is a specific power supply voltage such as a graphics processor of the display control unit 123. Supplied to the microprocessor. The DC 1.05V power supply voltage is not limited to that supplied to the graphics processor of the display control unit 123, and may be supplied to any microprocessor such as the effect control CPU 120 or the like.

Of the power supply voltages generated by the buck converter circuit 132 and the regulator circuit 133, the DC 3.3V power supply voltage, which has the largest voltage value and is the highest voltage, is stored in, for example, the ROM 121 or the image data memory of the display control unit 123. Be supplied. The ROM 121 may be started as long as it can be started before the electric components driven by the power supply voltage of DC 1.5V.

Of the power supply voltages generated by using the buck converter circuit 132 and the regulator circuit 133, the power supply voltage of DC 1.5V, which is higher than DC 1.05V and lower than DC 3.3V, is supplied to, for example, the RAM 122. The RAM 122 is a temporary storage memory that can be stored and read by, for example, a DDR (Double Data Rate) method, and functions as a memory module such as a SIMM (Single In-line Memory Module) or a DIMM (Dual In-line Memory Module). Configure the board. The substrate constituting such a RAM 122 may be configured as a separate substrate that can be detachably connected to the effect control substrate 12. In this case, the DC 1.5V power supply voltage is supplied to a board different from the effect control board 12.

When a 1-input 3-output buck converter circuit is used instead of the buck converter circuit 132 and the regulator circuit 133, a special dedicated circuit is required, which may increase the manufacturing cost. In addition, the amount of heat generated in a single circuit may increase, and the electric circuit may be damaged. Therefore, in the buck converter circuit 132, the power supply voltage VDD3 stabilized by the filter circuit 131c (the same applies to the power supply voltage VDC) is input, and the power supply voltage of DC 1.05V and the power supply voltage of DC 3.3V are output. .. In the regulator circuit 133, a DC 3.3V power supply voltage is input, and a DC 1.5V power supply voltage is output. This prevents an increase in manufacturing cost and enables an appropriate substrate configuration to disperse heat generation in the electric circuit.

A power supply voltage VDC that is the same as or substantially the same as the voltage supplied to the buck converter circuit 132 is supplied to the power supply monitoring circuit 140, and the occurrence of a power failure is monitored. In this way, the power supply voltage VDC used for generating various power supply voltages by the buck converter circuit 132 and the regulator circuit 133 is monitored by the power supply monitoring circuit 140. Therefore, the pachinko gaming machine 1 such as the graphics processor of the display control unit 123, for example. It is possible to configure an appropriate board to detect the occurrence of a power failure before the operating state of the electric circuit, which is important for executing the effect in the above, becomes unstable.

The DC 1.05V power supply voltage output from the buck converter circuit 132 is supplied to a specific microprocessor such as the graphics processor of the display control unit 123. By outputting a power supply voltage of 1.05 V DC from the buck converter circuit 132, when a power failure occurs, the power supply voltage of 1.05 V DC is output until a longer time elapses than the configuration output from the regulator circuit 133. Can be maintained. As a result, when a power failure occurs, an appropriate board configuration for continuing the operation of an electric circuit important for executing the effect in the pachinko gaming machine 1, such as the graphics processor of the display control unit 123, as much as possible can be obtained. It will be possible.

The DC 3.3V power supply voltage output from the buck converter circuit 132 is supplied to the ROM 121, for example, and starts before the electrical components such as the RAM 122 driven by the DC 1.5V power supply voltage output from the regulator circuit 133. It will be possible. As a result, when the power is turned on, for example, the effect control CPU 120 enables an appropriate board configuration that can immediately read the stored data of the ROM 121.

The DC 1.5V power supply voltage output from the regulator circuit 133 may be supplied to a board configured as a board different from the effect control board 12, such as the RAM 122. In this way, by outputting the DC 1.5V power supply voltage supplied to the board different from the effect control board 12 from the regulator circuit 133 different from the buck converter circuit 132, it is possible to prevent an increase in manufacturing cost and prevent an increase in manufacturing cost. It enables an appropriate board configuration to disperse the heat generated in the electric circuit.

(Explanation of feature 30AK)
FIG. 17 shows a configuration example of a portion of the main substrate 11 in which a wiring pattern for connecting the CPU 103 and the RAM 102 is formed on one substrate surface (surface) of the feature portion 30AK of the present embodiment. In the main board 11, in order to connect a plurality of electric components such as a RAM 102 and a CPU 103 by a plurality of signal wirings, a wiring pattern constituting the plurality of signal wirings is formed. The CPU 103 is an electric component configured to be able to execute a predetermined process with respect to the control of the game in the pachinko gaming machine 1, and the RAM 102 is an electric component configured to be able to store information related to the execution of the process by the CPU 103.

One or a plurality of ground conductors are arranged in a region around the wiring patterns constituting the plurality of signal wirings or between the signal wirings. The ground conductor functions as a reference ground and a ground for adjusting the characteristic impedance, and is maintained at the ground voltage. In the configuration example shown in FIG. 17, as the plurality of ground conductors, the ground conductor 30AK10G and the ground conductor 30AK11G are arranged in the area around the plurality of signal wirings, and the ground conductor 30AK20G is arranged in the area between the plurality of signal wirings. .. As described above, one or a plurality of ground conductors may be provided in the airspace portion which is a blank area where the wiring patterns constituting the plurality of signal wirings are not provided. This makes it possible to prevent or suppress electromagnetic wave noise radiated from a plurality of signal wirings and electromagnetic interference due to electromagnetic wave noise between signal wirings.

Note that the ground conductor is not limited to the one in which a plurality of ground conductors are arranged in both areas around the plurality of signal wirings and between the signal wirings, and the ground conductor is provided only in one area around the plurality of signal wirings or between the signal wirings. It may be arranged. Alternatively, such a ground conductor may not be arranged.

FIG. 18 shows a region or a section for explaining the wiring pattern constituting the plurality of signal wirings shown in FIG. 17 in more detail. The area 30AK01R shown in FIG. 18 is an area at the end on the side where a plurality of signal wirings are connected to the CPU 103. The region 30AK10R shown in FIG. 18 is a region in which a plurality of signal wirings are all linear or substantially linear and have a first shape parallel to or substantially parallel to each other, and the region 30AK11R and the region 30AK12R shown in FIG. 18 are at least one. This is a region in which the signal wiring of the portion has a shape different from the linear shape and the substantially linear shape and has a second shape parallel to and not substantially parallel to other signal wiring. In the section 30AK0SC shown in FIG. 18, a short-distance pattern in which some signal wirings of a plurality of signal wirings are connected at the shortest or substantially the shortest distance and a signal wiring not included in the short-distance pattern are longer distances than the short-distance pattern. A long-distance pattern connected by is arranged.

FIG. 19 is an enlarged view of the region 30AK01R shown in FIG. In the region 30AK01R shown in FIG. 19, the wiring patterns constituting the plurality of signal wirings include patterns 30AK10D to 30AK13D, patterns 30AK10CK, patterns 30AK10CS, patterns 30AK10RS, and patterns 30AK10A to 30AK14A.

FIG. 20 shows a setting example regarding the signal type, the presence / absence of signal synchronization, and the presence / absence of a meandering shape corresponding to the wiring pattern shown in FIG. The signal type shown in FIG. 20 indicates the content (use) of the electric signal transmitted by the signal wiring formed by each wiring pattern. The signal synchronization shown in FIG. 20 indicates the presence or absence of synchronization with respect to an electric signal transmitted by another signal wiring. The meandering shape shown in FIG. 20 indicates whether or not each wiring pattern connecting the RAM 102 and the CPU 103 is provided with a portion having a meandering shape different from the linear shape and the substantially linear shape. The meandering shape is also called a meander shape, a zigzag shape, or a folded shape, and is formed in a direction orthogonal to or substantially orthogonal to the extending direction, for example, by repeatedly bending the signal wiring with respect to the extending direction of the signal wiring in a predetermined section. Any shape may be used as long as it folds back and forth.

In the setting example shown in FIG. 20, the wiring patterns 30AK10D to 30AK13D all constitute signal wiring for transmitting a data signal. The data signal transmitted by each signal wiring is transmitted in synchronization with a signal transmitted by another signal wiring, for example, a clock signal and a data signal transmitted by another signal wiring. The wiring pattern 30AK10CK constitutes a signal wiring for transmitting a clock signal. The clock signal is transmitted in synchronization with signals transmitted by other signal wiring, such as a data signal, an address signal, and a chip select signal. The wiring pattern 30AK10CS constitutes a signal wiring for transmitting a chip select signal. The chip select signal is transmitted in synchronization with a signal transmitted by another signal wiring, for example, a clock signal. The wiring pattern 30AK10RS constitutes a signal wiring for transmitting a reset signal. The reset signal is transmitted asynchronously, which is not synchronized with the signals transmitted by other signal wirings. The wiring patterns 30AK10A to 30AK14A all constitute signal wiring for transmitting an address signal. The address signal transmitted by each signal wiring is transmitted in synchronization with a signal transmitted by another signal wiring, for example, a clock signal and an address signal transmitted by another signal wiring.

Of the data signals, clock signals, chip select signals, and address signals transmitted in synchronization with the signals transmitted by other signal wirings, the wiring patterns 30AK10D to 30AK13D constituting the signal wiring for transmitting the data signals , A wiring pattern 30AK10D without a serpentine shape is included. Wiring pattern The wiring pattern that constitutes the signal wiring for transmitting data signals, clock signals, chip select signals, and address signals that are different from the data signals transmitted by the signal wiring configured by 30AK10D has at least a linear shape. And it has a meandering shape as a shape different from the substantially linear shape.

Wiring pattern The signal wiring for transmitting the data signal configured by 30AK10D is between the connection terminals in the RAM 102 and the CPU 103 as compared with the signal wiring for transmitting other data signals, clock signals, chip select signals, and address signals. The distance is getting longer. Therefore, at least a part of the wiring pattern constituting the signal wiring for transmitting the data signal, the clock signal, the chip select signal, and the address signal different from the data signal transmitted by the signal wiring configured by the wiring pattern 30AK10D is. Due to the meandering shape, the wiring length of each signal wiring is the same or substantially the same. On the other hand, it is not necessary to provide a meandering shape in the wiring pattern 30AK10D.

In this way, among the signal wirings for transmitting synchronous signals, the signal wirings in which the distance between the connection terminals of a plurality of electrical components is longer than the distance between the other connection terminalss are, for example, a wiring portion having a meandering shape. , The wiring pattern may be formed so as not to include the wiring portion having a shape different from the linear shape and the substantially linear shape. Conversely, a signal wiring composed of a linear shape such as a serpentine shape and a wiring pattern that does not include a shape different from the substantially linear shape while having a shape such as a linear shape or a substantially linear shape is like a serpentine shape. The distance between the connection terminals in a plurality of electrical components is longer than that of the signal wiring formed by the wiring pattern including the straight line shape and the shape different from the substantially straight line shape. Alternatively, among the signal wirings for transmitting the synchronization signal, the signal wiring in which the distance between the connection terminals in a plurality of electrical components is longer than the distance between the other connection terminals is, for example, a wiring portion having a meandering shape. It is sufficient that the wiring pattern is formed so as not to include a wiring portion having a shape different from the shape parallel to and substantially parallel to the signal wiring of. Conversely, a signal wiring having a wiring pattern that is parallel to or substantially parallel to other signal wiring but does not include a shape different from parallel and substantially parallel shapes such as a meandering shape is a meandering shape. The distance between the connection terminals in a plurality of electrical components is longer than that of the signal wiring formed by the wiring pattern including the shape different from the shape parallel to and substantially parallel to other signal wiring such as. As a result, the wiring length of each signal wiring can be made the same or substantially the same, and it is possible to prevent or suppress the occurrence of a delay time difference (skew) of signals transmitted by a plurality of signal wirings. By reducing the delay time difference of the signals transmitted by the plurality of signal wirings, the reliability of the signals transmitted by the plurality of signal wirings can be improved.

The wiring pattern 30AK10RS is not provided with a meandering shape. The wiring pattern 30AK10RS constitutes a signal wiring for transmitting a reset signal which is an asynchronous signal. When transmitting an asynchronous signal such as a reset signal, it is not necessary to consider the delay time difference from the signal transmitted by other signal wiring. Therefore, unlike the wiring pattern 30AK10RS that constitutes the signal wiring for transmitting the reset signal, the wiring pattern that constitutes the signal wiring for transmitting the asynchronous signal is not provided with a meandering shape. If the wiring pattern is not provided with a meandering shape, an increase in the board area on which the wiring pattern is arranged can be suppressed, and the size of the board can be reduced.

As a wiring pattern that does not have a meandering shape, a wiring pattern that constitutes a dummy wiring maintained at the ground voltage may be arranged. For example, in the signal wiring configured by the wiring pattern 30AK10RS, the reset signal may be maintained at the ground voltage instead of being transmitted. The wiring pattern 30AK10RS is a wiring pattern 30AK10D to 30AK13D constituting a signal wiring for transmitting a data signal, a wiring pattern 30AK10CK constituting a signal wiring for transmitting a clock signal, and a chip select signal for transmitting a chip select signal. It is arranged between a group of patterns composed of the wiring patterns 30AK10CS constituting the signal wiring and a group of patterns composed of the wiring patterns 30AK10A to 30AK14A constituting the signal wiring for transmitting the address signal. There is. Wiring pattern By using a signal wiring arranged between other signal wirings such as 30AK10RS as a dummy wiring maintained at the ground voltage, it is possible to prevent or suppress electromagnetic interference due to electromagnetic noise in a plurality of signal wirings. .. As the wiring pattern without the meandering shape, a wiring pattern maintained at the power supply voltage may be arranged instead of the dummy wiring maintained at the ground voltage or together with the dummy wiring maintained at the ground voltage. For example, in the signal wiring configured by the wiring pattern 30AK10RS, the reset signal may be maintained at the power supply voltage instead of being transmitted. If the wiring pattern maintained at the power supply voltage is arranged close to the wiring patterns constituting other signal wirings, electromagnetic noise may occur due to electromagnetic coupling between the respective signal wirings. Therefore, when arranging the wiring pattern maintained at the power supply voltage, the distance from the signal wiring is longer than that at the case of arranging the wiring pattern maintained at the ground voltage. A pattern may be formed. As a result, electromagnetic interference due to electromagnetic noise in the signal wiring can be prevented or suppressed.

FIG. 21 is an enlarged view of the region 30AK10R shown in FIG. Wiring patterns 30AK10CK, 30AK10CS, 30AK10RS, and 30AK10A to 14A are formed in the region 30AK10R. These wiring patterns are formed in the region 30AK10R so that the plurality of signal wirings are all linear or substantially linear and parallel or substantially parallel to each other. As described above, in the region 30AK10R, the wiring patterns constituting the plurality of signal wirings are all formed to have a linear shape or a substantially linear shape, and the plurality of signal wirings have a shape parallel to or substantially parallel to each other. A wiring pattern is formed.

FIG. 22 is an enlarged view of the region 30AK11R shown in FIG. Similar to the area 30AK10R, the wiring patterns 30AK10CK, 30AK10CS, 30AK10RS, and 30AK10A to 14A are formed in the area 30AK11R. These wiring patterns are formed so that at least one signal wiring has a linear shape or a substantially linear shape in the region 30AK11R, while the other signal wiring has a shape different from the linear shape and the substantially linear shape. It is formed to be. In the region 30AK11R shown in FIG. 22, for example, the wiring pattern 30AK10CK constituting the signal wiring for transmitting the clock signal and the wiring pattern 30AK10CS constituting the signal wiring for transmitting the chip select signal have a plurality of bent portions. Although they are included, they are all formed to have a linear shape or a substantially linear shape. Further, in the region 30AK11R shown in FIG. 22, the wiring pattern 30AK10RS constituting the signal wiring for transmitting the reset signal is formed so as to have a linear shape or a substantially linear shape not including a bent portion. On the other hand, in the region 30AK11R shown in FIG. 22, the wiring patterns 30AK10A to 30AK14A constituting the signal wiring for transmitting the address signal have a meandering shape formed by a plurality of bent portions, and have a linear shape and a substantially linear shape. Are formed to have different shapes.

In the portion where the meandering shape is formed, the signal wiring may be bent in a direction orthogonal to the original extension direction, for example, by passing through a plurality of bent portions. At each bent portion, the signal wiring may be bent so as to form an angle (obtuse angle) larger than a right angle, so that a wiring pattern in which the extension direction of the signal wiring is changed may be formed. In this case, the signal wiring is bent so that the bending amount at each bent portion is smaller than the right angle. In the portion where the meandering shape is formed, the signal wiring can be extended in the first extension direction and the second extension direction orthogonal to or substantially orthogonal to the first extension direction, and the first extension is possible. A plurality of bent portions may be provided between the wiring pattern constituting the signal wiring in the direction and the wiring pattern constituting the signal wiring in the second extension direction. In this way, the extension direction of the signal wiring is changed through the plurality of bent portions in which the bending amount of the signal wiring is smaller than the predetermined angle. By reducing the amount of bending, it is possible to prevent the pattern width of the wiring at the bending part from changing significantly, prevent the characteristic impedance of the transmission line from suddenly changing, and electromagnetic waves due to electromagnetic noise in multiple signal wirings. Interference can be prevented or suppressed.

In each signal wiring, a plurality of bent portions may be arranged so that the position of the bent portion is a distance longer than a predetermined length from the position of the bent portion in the other signal wiring. The predetermined length may be a predetermined length from the viewpoint of substrate design, for example, a constant length included in the range of 2 mm to 5 mm. Electromagnetic noise is likely to occur at the bent portion of the signal wiring due to changes in the characteristic impedance or the like. The bent portion formed by the wiring pattern forming one signal wiring included in the plurality of signal wiring is close to the bent portion formed by the wiring pattern forming the other signal wiring included in the plurality of signal wiring. If arranged, the signal transmitted by each signal wiring may be easily affected by electromagnetic noise. Therefore, a bent portion formed by a wiring pattern forming one signal wiring included in a plurality of signal wirings and a bent portion formed by a wiring pattern forming another signal wiring included in the plurality of signal wirings are formed. By arranging them at intervals so as to be longer than a predetermined length, it is possible to prevent or suppress electromagnetic interference due to electromagnetic noise in a plurality of signal wirings.

Further, in the region 30AK11R, at least one signal wiring is formed so as to have a shape different from parallel and substantially parallel. In the region 30AK11R shown in FIG. 22, for example, the wiring pattern 30AK10CK constituting the signal wiring for transmitting the clock signal and the wiring pattern 30AK10CS constituting the signal wiring for transmitting the chip select signal are both plurality. The signal wirings are formed to be parallel or substantially parallel to each other through the bent portion as a whole. On the other hand, in the region 30AK11R shown in FIG. 22, the wiring patterns 30AK10A to 30AK14A constituting the signal wiring for transmitting the address signal have a meandering shape formed by a plurality of bent portions, and therefore, as a whole, they are mutually exclusive. The signal wiring is formed so as to have a shape different from parallel or substantially parallel.

In the region 30AK11R shown in FIG. 22, at least one of the plurality of signal wirings has a shape such as a meandering shape different from the parallel and substantially parallel shapes. In this region 30AK11R, the space region 30AK0SP close to the wiring pattern constituting the signal wiring is not provided with a conductor at least on the same substrate as the signal wiring. The space region 30AK0SP is close to, for example, the wiring patterns 30AK10A to 30AK13A in which the meandering shape is provided in the region 30AK11R among the wiring patterns 30AK10A to 30AK14A constituting the signal wiring for transmitting the address signal. Since the space region 30AK0SP is not provided with a conductor, it is possible to prevent or suppress electromagnetic interference due to electromagnetic noise in a plurality of signal wirings. If a conductor is provided in a region close to the meandering wiring pattern, electromagnetic waves may be radiated from the signal wiring, and electromagnetic noise is generated due to electromagnetic coupling between the signal wiring and the conductor. There is a risk of Therefore, by not providing a conductor in a region close to the wiring pattern provided with a meandering shape, for example, in the space region 30AK0SP, it is possible to prevent or suppress electromagnetic interference due to electromagnetic noise in a plurality of signal wirings. Be done.

FIG. 23 is a cross-sectional view showing a configuration example of the main board 11 formed as the multilayer wiring board. The main substrate 11 shown in FIG. 23 has a multi-layer structure formed by stacking synthetic resins, and various wiring patterns can be formed on the surface or inner layer of each layer. A plurality of electronic components such as the RAM 102 and the CPU 103 are electrically connected via a wiring pattern formed on the main board 11 having such a multi-layer structure. The multilayer structure of the main substrate 11 shown in FIG. 23 includes a front surface layer 30AK1S, a ground layer 30AK1L, a power supply layer 30AK2L, a wiring layer 30AK3L, a power supply layer 30AK4L, and a back surface layer 30AK2S.

A surface layer 30AK1S is provided on the surface of the main substrate 11 which is one of the substrate surfaces, and a wiring pattern 30AK10P and a pattern 30AK11P constituting the signal wiring are formed. A back surface layer 30AK2S is provided on the back surface of the main substrate 11 which is the other substrate surface, and a wiring pattern 30AK20P constituting the signal wiring is formed. The wiring pattern 30AK10P formed on the front surface layer 30AK1S of the main substrate 11 has a wiring pattern 30AK20P formed on the back surface layer 30AK2S via the through holes 30AK1H penetrating the front surface layer 30AK1S and the back surface layer 30AK2S of the main substrate 11. It is electrically connected. The wiring pattern 30AK11P formed on the front surface layer 30AK1S of the main substrate 11 has a wiring pattern 30AK20P formed on the back surface layer 30AK2S via the through holes 30AK2H penetrating the front surface layer 30AK1S and the back surface layer 30AK2S of the main substrate 11. It is electrically connected. As described above, the main substrate 11 is provided with the wiring patterns 30AK10P and 30AK11P forming the signal wiring in the surface layer 30AK1S provided on the surface to be one substrate surface, and the back surface to be the other substrate surface. Through holes 30AK1H and through holes 30AK2H are provided so that the wiring pattern 30AK20P constituting the signal wiring in the back surface layer 30AK2S can be electrically connected.

The wiring length of each signal wiring included in the plurality of signal wirings connecting the RAM 102 and the CPU 103 shown in FIG. 23 is that of the wiring patterns 30AK10P and 30AK11P formed on the front surface layer 30AK1S and the wirings formed on the back surface layer 30AK2S. Not only the wiring length of the signal wiring formed by the pattern 30AK20P, but also the lengths of the through hole 30AK1H and the through hole 30AK2H are the same or substantially the same. In the main board 11 having the multilayer structure shown in FIG. 23, the wiring lengths of the respective signal wirings are the same or substantially the same, including the lengths of the through holes 30AK1H and the through holes 30AK2H, and the signals transmitted by the plurality of signal wirings are used. It is possible to prevent or suppress the occurrence of a delay time difference. By reducing the delay time difference of the signals transmitted by the plurality of signal wirings in the multilayer wiring board such as the main board 11, the reliability of the signals transmitted by the plurality of signal wirings can be improved.

In the main substrate 11 having a multilayer structure shown in FIG. 23, a ground layer 30AK1L is provided as a conductor layer adjacent to the surface layer 30AK1S. One or more ground conductors are arranged in the ground layer 30AK1L, and the ground conductors are maintained at the ground voltage. In the surface layer 30AK1S, the wiring patterns 30AK10P and the pattern 30AK11P constituting the signal wiring have a shape different from the linear shape and the substantially linear shape such as a meandering shape in at least one of the patterns, and a plurality of signal wirings are parallel and substantially parallel. It suffices if it is formed so as to include a region having a shape different from that of the normal shape. No signal is transmitted in the ground layer 30AK1L as a conductor layer adjacent to the surface layer 30AK1S. Since the signal is not transmitted in the conductor layer adjacent to the surface layer 30AK1S on which the wiring pattern 30AK10P and the pattern 30AK11P are formed, the signal transmitted by the plurality of signal wirings composed of the wiring pattern 30AK10P and the pattern 30AK11P is an electromagnetic wave. It becomes less susceptible to noise, and it is possible to prevent or suppress the influence of electromagnetic noise on other signal wiring.

The wiring pattern 30AK20P constituting the signal wiring in the back surface layer 30AK2S of the main substrate 11 having the multilayer structure shown in FIG. 23 has a shape different from the linear shape and the substantially linear shape such as a meandering shape, and a plurality of signal wirings are parallel and omitted. It may be formed so as to include a region having a shape different from the parallel shape. No signal is transmitted in the power supply layer 30AK4L as the conductor layer adjacent to the back surface layer 30AK2S. One or more power conductors are arranged in the power layer 30AK4L, and the power conductors are maintained at the power supply voltage. Since the signal is not transmitted in the conductor layer adjacent to the back surface layer 30AK2S on which the wiring pattern 30AK20P is formed, the signals transmitted by the plurality of signal wirings constituting the wiring pattern 30AK20P are less likely to be affected by electromagnetic noise. Therefore, it is possible to prevent or suppress the influence of electromagnetic noise on other signal wirings. In a multilayer wiring board such as the main board 11, signals are not transmitted in a conductor layer adjacent to a layer in which a plurality of signal wirings are provided, so that electromagnetic interference due to electromagnetic noise in the plurality of signal wirings can be prevented or suppressed. It is planned.

In the wiring layer 30AK3L of the main board 11 having the multilayer structure shown in FIG. 23, the wiring pattern constituting the signal wiring is a shape different from the linear shape and the substantially linear shape such as a meandering shape, and a plurality of signal wirings are parallel and substantially parallel. It may be formed so as to include a region having a shape different from that of the normal shape. No signal is transmitted in the power supply layer 30AK2L or the power supply layer 30AK4L as the conductor layer adjacent to the wiring layer 30AK3L. In a multilayer wiring board such as the main board 11, signals are not transmitted in the conductor layer adjacent to the wiring layer 30AK3L in which a plurality of signal wirings are provided, so that electromagnetic interference due to electromagnetic noise in the plurality of signal wirings can be prevented or Suppression is achieved. However, if the wiring layer 30AK3L, which is the inner conductor layer provided on the multilayer wiring board, is formed so that the wiring pattern constituting the signal wiring includes a region having a shape such as a meandering shape, the signal wiring When a failure occurs due to disconnection or the like, it may be difficult to confirm the state of the signal wiring in the wiring layer 30AK3L from the outside of the substrate. On the other hand, a region such as the front surface layer 30AK1S and the back surface layer 30AK2S of the main substrate 11 in which the wiring pattern constituting the signal wiring on one substrate surface or the other substrate surface of the main substrate 11 has a meandering shape or the like. When it is formed so as to include, an appropriate board configuration that makes it easy to check the state of signal wiring in the front surface layer 30AK1S and the back surface layer 30AK2S from the outside of the board is possible in the event of a failure due to disconnection of the signal wiring or the like. Become.

The through holes penetrating the front surface layer 30AK1S and the back surface layer 30AK2S of the main substrate 11 are not limited to the through holes 30AK1H and the through holes 30AK2H shown in FIG. It may be used to make the wiring length of the wiring the same or substantially the same. Among the wiring patterns constituting the plurality of signal wirings, the signal wirings are arranged only in the surface layer 30AK1S of the main board 11, for example, without passing through the through holes such as the through holes 30AK1H and the through holes 30AK2H. The formed pattern may be included. Wiring pattern Signal wiring for transmitting data signals configured by 30AK10D, such as signal wiring for transmitting data signals composed of 30AK10D, is signal wiring in which the distance between connection terminals in a plurality of electrical components is longer than the distance between other connection terminals. The signal wiring may be arranged only in the surface layer 30AK1S of the main substrate 11 without passing through a through hole such as the hole 30AK2H. Conversely, the signal wiring formed by the wiring pattern formed by one conductor layer such as the front surface layer 30AK1S without passing through the through hole is a through hole in a plurality of conductor layers such as the front surface layer 30AK1S and the back surface layer 30AK2S. The distance between the connection terminals in a plurality of electrical components is longer than that of the signal wiring formed by the wiring pattern formed so as to be electrically connectable via the wire.

When a plurality of signal wirings are provided adjacent to each other, a small blank area is formed as in the space area 30AK0SP shown in FIG. It is also conceivable to provide a through hole in this blank region and have a through hole electrode in which a conductive material such as copper is embedded so as to be electrically connected to another conductor layer such as the ground layer 30AK1L. In a configuration in which a conductor such as a through-hole electrode is provided in the blank region, for example, a large number of through-hole electrodes may be arranged in order to stabilize the electric field distribution in the blank region. In this case, not only the front surface layer 30AK1S of the main substrate 11 but also the back surface layer 30AK2S is arranged with a structure corresponding to the through-hole electrode such as a bump, which restricts the design of the wiring pattern on the substrate. Inconvenience may occur. Further, in the ground layer 30AK1L, the power supply layer 30AK2L, 30AK4L, etc., which are the inner conductor layers provided on the multilayer wiring board, when the through-hole electrodes are provided, the pattern of the conductor layer is removed around the through-hole electrodes. As a result, the pattern in the inner conductor layer such as the ground layer 30AK1L, the power supply layer 30AK2L, and 30AK4L may be divided, which may make it difficult to design the pattern in the conductor layer. Further, in a configuration in which a conductor such as a dummy pad is provided in a blank region instead of the through-hole electrode and is not connected to another conductor layer, this conductor may be affected by external electromagnetic noise or may be affected by external electromagnetic noise. This conductor may affect a plurality of signal wirings by electromagnetic noise, which may cause an adverse effect such as electromagnetic interference. On the other hand, since the conductor is not provided in the space region 30AK0SP close to the wiring pattern constituting the signal wiring, it is possible to prevent or suppress the occurrence of these inconveniences.

In addition, as in the space area 30AK0SP shown in FIG. 22, the blank area formed when a plurality of signal wirings are provided adjacent to each other is different from the constituent material of the board, for example, a screw hole for fixing the board. The structure in which the material is used may not be provided. When screw holes for fixing the board are provided, when the board is fixed by screwing, the constituent materials of the screws are affected by electromagnetic noise from the outside, and other signal wiring is also adversely affected by electromagnetic interference. May cause inconvenience. Further, a structure using a synthetic resin or a dielectric material having a dielectric constant different from that of the insulating layer contained in the substrate, or a structure using a synthetic resin or a metal material having an electric conductivity different from that of the conductor layer contained in the substrate. , When provided in a blank area close to a plurality of signal wirings, these structures are affected by electromagnetic wave noise from the outside, or these structures affect a plurality of signal wirings by electromagnetic wave noise. This may cause inconveniences such as electromagnetic interference. On the other hand, these inconveniences occur because a structure using a material different from the constituent material of the substrate is not provided in the blank region such as the space region 30AK0SP close to the wiring pattern constituting the signal wiring. This can be prevented or suppressed.

In the section 30AK0SC shown in FIG. 18, the pattern 30AK13D of one of the wiring patterns 30AK10D to 30AK13D forming a plurality of signal wirings for transmitting a data signal has a shape different from the linear shape and the substantially linear shape such as a meandering shape. It is formed so as to include a portion of the signal wiring having a shape different from the shape parallel to and substantially parallel to the other signal wiring. On the other hand, at least the pattern 30AK10D and the pattern 30AK11D are formed in the section 30AK0SC so that the signal wirings are parallel or substantially parallel to each other in a linear shape or a substantially linear shape without including a meandering shape. .. Therefore, the pattern 30AK10D and the pattern 30AK11D are patterns in which the signal wiring connects the section 30AK0SC in the shortest or substantially the shortest. On the other hand, the pattern 30AK12D and the pattern 30AK13D are patterns in which the signal wiring connects the section 30AK0SC at a longer distance than the pattern 30AK10D and the pattern 30AK11D.

In the section 30AK0SC, where the signal wiring formed by the pattern 30AK13D has a linear shape such as a meandering shape or a shape different from the substantially linear shape, the signal wiring formed by the other patterns 30AK10D to 30AK12D has a linear shape or It is formed so as to have a substantially linear shape. In this way, in the portion where the signal wiring composed of one wiring pattern among the wiring patterns constituting the plurality of signal wirings has a shape different from the linear shape such as a meandering shape and the substantially linear shape, the other The signal wiring formed by the wiring pattern of the above may be formed so as to have a linear shape or a substantially linear shape. In the part where the signal wiring composed of the wiring pattern of 1 has a shape different from the linear shape such as a meandering shape and the substantially linear shape, the signal wiring composed of the other wiring patterns has a linear shape or a substantially linear shape. It may be formed so as not to overlap with the portion. By forming a wiring pattern so that the linear shape such as a meandering shape and the portion having a shape different from the substantially linear shape do not overlap with each other for a plurality of signal wirings, an increase in the board area on which the wiring pattern is arranged is suppressed. Therefore, the size of the substrate can be reduced.

FIG. 24 shows another formation example of a wiring pattern in which the portions of the plurality of signal wirings having a meandering shape do not overlap. Even in the region 30AK20R shown in FIG. 24, in the portion where the signal wiring composed of one wiring pattern among the wiring patterns constituting the plurality of signal wirings has a meandering shape, the signal composed of other wiring patterns The wiring is formed so as to have a linear shape or a substantially linear shape. Then, when the first meandering portion, which is a portion in which the first signal wiring formed of the first wiring pattern has a meandering shape, is completed, the second wiring pattern formed of a second wiring pattern different from the first wiring pattern is formed. A wiring pattern forming a plurality of signal wirings is formed so that a second meandering portion, which is a portion of the signal wiring having a meandering shape, is started. In the first meandering portion, as the wiring pattern constituting the signal wiring other than the first signal wiring, the wiring pattern including the pattern of the second wiring constituting the second signal wiring is the signal wiring composed of each pattern. It suffices that they are formed so as to have a parallel or substantially parallel shape. In the second meandering portion, as the wiring pattern constituting the signal wiring other than the second signal wiring, the wiring pattern including the pattern of the first wiring constituting the first signal wiring is the signal wiring composed of each pattern. It suffices that they are formed so as to have a parallel or substantially parallel shape. Since the second meandering portion is started after the first meandering portion is completed, the first meandering portion is arranged so as not to overlap with the second meandering portion. As a result, even when a large number of signal wirings are provided with a portion having a linear shape such as a meandering shape or a shape different from the substantially linear shape, an increase in the substrate area for arranging the wiring pattern is suppressed as much as possible. The size of the substrate can be reduced.

The wiring pattern in which the portions of the plurality of signal wirings having a meandering shape do not overlap is formed so that the wiring lengths of the respective signal wirings are the same or substantially the same. In the first signal wiring composed of the first wiring pattern among the wiring patterns constituting the plurality of signal wirings, the second signal wiring composed of the second wiring pattern has a linear shape or a substantially linear shape. Includes a first meandering portion that has a meandering shape corresponding to the second straight portion. Further, in the second signal wiring composed of the second wiring pattern among the wiring patterns constituting the plurality of signal wirings, the first signal wiring composed of the first wiring pattern has a linear shape or a substantially linear shape. Includes a second meandering portion that has a meandering shape corresponding to the first straight portion. By including the first meandering portion and the second meandering portion in this way, it is possible to suppress an increase in the substrate area on which the wiring pattern is arranged, and to reduce the size of the substrate.

Alternatively, the first meandering portion in which the first signal wiring formed by the pattern of the first wiring has a meandering shape is different from the second meandering portion in which the second signal wiring formed by the pattern of the second wiring has a meandering shape. The signal wiring may meander in the direction. By meandering the signal wiring in this way, it is possible to suppress an increase in the area of the substrate on which the wiring pattern is arranged, and to reduce the size of the substrate.

Alternatively, the wiring pattern in which the plurality of signal wirings have a meandering shape may include a pattern of the first wiring in which the wiring width of the signal wiring is narrow and a pattern of the second wiring in which the wiring width of the signal wiring is wide. By forming the wiring pattern in this way, for example, a signal wiring having appropriate transmission path characteristics is configured according to the type of signal transmitted by the plurality of signal wirings, and the signal wiring is transmitted by the plurality of signal wirings. The reliability of the signal can be improved.

Alternatively, the wiring so that some or all of the signal wirings of the plurality of signal wirings have a shape different from the linear shape and the substantially linear shape, such as a meandering shape, and are parallel or substantially parallel to each other. A parallel meandering portion on which a pattern is formed may be provided. By providing the parallel meandering portion, it is possible to suppress an increase in the area of the substrate on which the wiring pattern is arranged, and to reduce the size of the substrate.

Alternatively, one signal wiring and another signal wiring are formed in a non-linear portion in which a part or all of the signal wirings of the plurality of signal wirings have a shape different from the linear shape and the substantially linear shape, for example, a meandering shape. Wiring patterns may be formed so that the electrical components connected to are mounted. By mounting the electric components in this way, it is possible to suppress an increase in the wiring pattern and the board area on which the electric parts are arranged, and to reduce the size of the board.

Alternatively, when a part or all of the signal wirings of the plurality of signal wirings include a non-linear portion having a shape different from the linear shape and the substantially linear shape such as a meandering shape, the shape is different from the non-linear portion. A wiring pattern may be formed so that each signal wiring is connected to an electric component at a portion thereof. By connecting to the electric components in this way, it is possible to suppress an increase in the wiring pattern and the board area on which the electric parts and the like are arranged, and to reduce the size of the board.

A wiring pattern in which at least one of the plurality of signal wirings has a shape different from the linear shape and the substantially linear shape, or at least one signal wiring is parallel to and substantially parallel to the other signal wirings. The wiring pattern formed so as to have a shape different from the shape is formed so that the wiring length of each signal wiring is the same or substantially the same. Among the wiring patterns constituting the plurality of signal wirings, the first signal wiring composed of the first wiring pattern has a linear shape and a substantially linear shape of the second signal wiring composed of the second wiring pattern. It may be a linear shape or a substantially linear shape corresponding to a portion having a different shape or a portion having a shape different from the shape in which the second signal wiring is parallel to and substantially parallel to the first signal wiring. Then, a test point is formed in a portion where the second signal wiring has a shape different from the linear shape and the substantially linear shape, or a portion where the second signal wiring has a shape different from the shape parallel to and substantially parallel to the first signal wiring. A specific conductor portion may be provided. The test point may be a specific conductor portion configured so that a probe for inspecting an electrical connection state by a signal wiring or an electric component can be brought into contact with the test point. By providing the test points in this way, it is possible to appropriately arrange the wiring pattern and appropriately arrange various structures, suppress the increase in the substrate area, and reduce the size of the substrate.

Alternatively, the specific conductor portion such as the test point may be formed by using a metal material such as solder or copper foil and may have a shape larger than the wiring width of the signal wiring. By forming test points and the like in this way, it is possible to appropriately arrange wiring patterns and appropriately arrange various structures to suppress an increase in the substrate area and reduce the size of the substrate. it can.

Alternatively, the specific conductor portion such as the test point has a through hole provided in the multilayer wiring board, so that the conductor layer is different from the layer in which the plurality of signal wirings and the test points are provided among the plurality of layers included in the multilayer wiring board. , May be electrically connected. By forming test points and the like in this way, it is possible to appropriately arrange wiring patterns and appropriately arrange various structures to suppress an increase in the substrate area and reduce the size of the substrate. it can.

A wiring pattern in which at least one of a plurality of signal wirings is formed in a shape different from a linear shape and a substantially linear shape on one substrate surface such as a substrate surface on the front surface side, or at least one signal. The wiring pattern formed so that the wiring has a shape different from the shape parallel to and substantially parallel to the other signal wiring is formed so that the wiring length of each signal wiring is the same or substantially the same. Among the wiring patterns constituting the plurality of signal wirings, the first signal wiring composed of the first wiring pattern has a linear shape and a substantially linear shape of the second signal wiring composed of the second wiring pattern. It may be a linear shape or a substantially linear shape corresponding to a portion having a different shape or a portion having a shape different from the shape in which the second signal wiring is parallel to and substantially parallel to the first signal wiring. Then, a specific conductor portion serving as a test point may be provided on the other substrate surface different from the one substrate surface on which the wiring pattern is formed, for example, the substrate surface on the back surface side. By providing the test points in this way, it is possible to appropriately arrange the wiring pattern and appropriately arrange various structures, suppress the increase in the substrate area, and reduce the size of the substrate.

(Explanation of deformation and application)
The present invention is not limited to the above-described embodiment, and various modifications and applications are possible. For example, the pachinko gaming machine 1 does not have to have all the technical features shown in the above-described embodiment, and is a part described in the above-described embodiment so as to be able to solve at least one problem in the prior art. It may have the structure of. For example, among the features shown in the above-described embodiment, those having at least one feature that enables an appropriate substrate configuration may be used.

In the above embodiment, at least one of the plurality of signal wirings for electrically connecting the plurality of electric components has a shape different from the linear shape and the substantially linear shape, and is parallel to the other signal wirings. It has been described that the shape is different from the substantially parallel shape and includes a portion having a shape called a meandering shape, a meander shape, a zigzag shape, and a folded shape. On the other hand, a shape different from a straight line shape and a substantially straight line shape, or a shape different from a shape parallel to or substantially parallel to other signal wirings is different from a meandering shape such as a curved shape or a spiral shape, and the wiring length of the signal wiring. Any shape that can be extended or adjusted may be used. For at least one signal wiring among a plurality of signal wirings that electrically connect a plurality of electric components, by including a portion having a shape in which the wiring length can be extended, each signal wiring included in the plurality of signal wirings. It suffices if the wiring lengths are the same or substantially the same, and the delay time difference between signals transmitted by a plurality of signal wirings can be prevented or suppressed.

The plurality of electrical components electrically connected by the plurality of signal wirings are not limited to the RAM 102 and the CPU 103 mounted on the main board 11, and may be any electrical components included in the gaming machine such as the pachinko gaming machine 1. .. For example, as a plurality of electrical components, the effect control CPU 120 and the RAM 122 mounted on the effect control board 12 are electrically connected by a plurality of signal wirings, and at least one of the plurality of signal wirings has a linear shape. The wiring pattern may be formed so as to have a shape different from the substantially linear shape and different from the shape parallel to the other signal wiring and the shape substantially parallel to the other signal wiring. In this case, the effect control CPU 120 is an electric component configured to be able to execute a predetermined process with respect to the effect control in the pachinko gaming machine 1, and the RAM 122 can store information regarding the execution of the process by the effect control CPU 120. It is an electrical component configured in. Alternatively, instead of the RAM 102 in the above embodiment, an electric component such as a ROM 101 that can store information regarding the execution of processing by the CPU 103 may be used. Alternatively, it may be an electric component capable of executing processing related to an effect different from that of the effect control CPU 120, such as a graphics processor provided in the display control unit 123 instead of the effect control CPU 120. Further, instead of the RAM 122, an electric component such as a ROM 121 that can store information regarding execution of processing by the effect control CPU 120 may be used. Further, instead of the RAM 122, it may be an electric component that can store information related to execution of processing by the effect control CPU 120 or the graphics processor of the display control unit 123, such as an image data memory.

The effect control board 12 may be configured as a multi-layer wiring board, similarly to the main board 11 in the above embodiment. The plurality of signal wirings in the above embodiment are arranged so that a plurality of processing devices such as an effect control CPU 120 mounted on the effect control board 12 and a graphics processor included in the display control unit 123 are electrically connected. A wiring pattern may be formed. Alternatively, the plurality of signal wirings have a wiring pattern formed so that a plurality of electrical components such as a graphics processor included in the display control unit 123 and an input / output port for a video signal are electrically connected. It may be. A wiring pattern is formed so that an arbitrary electric circuit different from the plurality of electric components, such as a filter circuit and a buffer circuit, intervenes in the plurality of signal wirings to which the plurality of electric components are connected. It may be a thing. In a plurality of signal wirings, for example, for the display colors of R (red), G (green), and B (blue) in the image display device 5, digital video signals indicating the respective levels (RGB values) are transmitted in a parallel signal system. May be done. Alternatively, in the plurality of signal wirings, signals related to game control and effect control may be transmitted by a parallel signal system such as an LVDS (Low Voltage Differential Signal) system. In these parallel signal systems, synchronized signal transmission may be required in a plurality of signal wirings. Therefore, as in the above embodiment, by forming the wiring pattern so that a portion having a shape such as a meandering shape is provided, the wiring length of each signal wiring included in the plurality of signal wirings is the same or abbreviated. It becomes the same, and the delay time difference of the signals transmitted by a plurality of signal wirings can be reduced.

The signal is not limited to the signal transmitted by the parallel signal method, and for example, a video signal supplied to the image display device 5, speakers 8L, 8R, a game effect lamp 9, a production motor 60, and a production LED 61 are used for production. When the control signal supplied to the electric component is transmitted by the serial signal method, the signal wiring for transmitting the clock signal and the signal wiring for transmitting the data signal are a plurality of signal wirings in the above embodiment. It may be included in the signal wiring. Further, when the video signal or the control signal is transmitted by the serial signal method, the signal wiring for transmitting the signal by the differential signal transmission method may be included in the plurality of signal wirings in the above embodiment.

For example, a signal wiring having a longer distance between connection terminals in a plurality of electrical components than other signal wiring, such as the signal wiring configured by the wiring pattern 30AK10D, has a shape different from the linear shape and the substantially linear shape. The wiring pattern may be formed so as to include a portion having a shape different from the shape parallel to and substantially parallel to other signal wiring. Even if the distance between the connection terminals of a plurality of electric components is shorter than that of other signal wiring, the wiring length may be longer than that of other signal wiring depending on the design of the wiring pattern on the board. In such a case, the selection of a signal wiring that includes a portion having a shape such as a meandering shape among a plurality of signal wirings and a signal wiring that does not include such a portion is used for designing a wiring pattern on a substrate. It may be changed arbitrarily accordingly.

The receptacle KRE1 is not limited to the one surface-mounted on the substrate of the effect control substrate 12, and may be surface-mounted on any substrate, for example, on the substrate of the main substrate 11. The various power supply voltages are not limited to those supplied to the effect control board 12, and may be supplied to any control board such as the main board 11 or the payout control board. The various electric circuits and electric components are not limited to those arranged on the effect control board 12, and may be arranged on any control board such as the main board 11 or the payout control board.

The present invention can be applied not only to the pachinko gaming machine 1 but also to slot machines and the like. A slot machine is an arbitrary game machine capable of performing a predetermined game, for example, a variable display of a symbol serving as a plurality of types of identification information, and imparting a predetermined game value based on the game result. A variable display device (a variable display device) that can start a game by setting a predetermined number of bets (number of medals or credits) for one game and variably displays a plurality of types of identification information (designs) that can be identified by each. One game ends when the display results of (for example, multiple reels, etc.) are derived and displayed, and prizes are awarded according to the display results (for example, cherry prize, watermelon prize, bell prize, replay prize, BB prize, RB prize, etc.). Is a gaming machine that can generate. In such a slot machine, the pachinko game shown in the above-described embodiment is achieved by the cooperation of hardware resources including a game control microcomputer for performing game control and software that performs predetermined processing. It suffices that it is configured to have all or a part of the features of the machine 1.

In addition, the device configuration and various operations of the gaming machine can be arbitrarily changed and modified without departing from the spirit of the present invention. In addition, the gaming machine of the present invention is not limited to a pay-out type gaming machine that pays out a predetermined number of gaming media as a prize based on the occurrence of a prize, but a score is scored based on the occurrence of a winning by enclosing the gaming medium. It can also be applied to an enclosed gaming machine that grants. Slot machines are not limited to those in which the number of bets is set using medals and credits as the game value, but only slot machines that set the number of bets using game balls as the game value and credits as the game value. It may be a fully credited slot machine that sets the number of bets using.

(Explanation of problem solving means and effects)
As described above, in a gaming machine such as the pachinko gaming machine 1 according to the present application, in a wiring connection device such as the receptacle KRE1, the terminal TA01 serving as a pair of ground terminals is located at a position sandwiching both sides of the terminal TA02 serving as a signal terminal. , TA03 is surface-mounted on the substrate of the effect control substrate 12, so that an appropriate substrate configuration becomes possible.

The terminals TA01 and TA03 are joined to the dummy pads DP1 and DP2, and the tips of the terminals TA01 to TA03 are covered with the cover member 802 of the substrate case 800, whereby an appropriate substrate configuration becomes possible.

By providing the receptacle KRE1 with fixing metal fittings SS01 and SS02 joined to the dummy pads DP3 and DP4 on the side surface PL2, an appropriate substrate configuration becomes possible.

The distance between the inner peripheral wall surface 836b and the receptacle KRE1 in the opening region 836a is such that the opening width W2 on the side closer to the component accommodating portion 802a is wider than the opening width W1 on the far side, so that an appropriate substrate configuration is possible. Become.

The terminals TA01 to TA03 of the receptacle KRE1 are formed with an exposed portion that is not covered by the cover member 802 of the substrate case 800 and is exposed by the cover member 802 of the substrate case 800 in the opening region 836a, and a covering portion that is covered by the cover member 802 of the substrate case 800 and is not exposed. This enables an appropriate substrate configuration.

The mounting positions where the terminals TA01 to TA03 of the receptacle KRE1 are surface-mounted are covered by the opening peripheral edge portion 840, and the opening peripheral edge portion 840 and the substrate surface of the effect control board 12 form a space SP1 close to the mounting position. Appropriate board configuration is possible.

Alternatively, the effect control board 12 outputs the DC 34V power supply voltage VSL2 as it is as the power supply voltage VSL, and inputs it to the filter circuit 511 on the driver board 19 to stabilize the voltage, whereby an appropriate board configuration becomes possible. ..

By not interposing a filter circuit in the power supply line LSL that supplies the power supply voltage VSL of DC 34V, an appropriate substrate configuration becomes possible.

In the receptacle KRE2, the number of terminals TA15 to TA24, TA27, and TA28 connected to any of the filter circuits 131a to 131c is larger than the number of terminals of the terminals TA13 and TA14 not connected to the filter circuit, which is appropriate. The board configuration becomes possible.

Terminals TA15 to TA24, TA27, and TA28 connected to any of the filter circuits 131a to 131c can supply a plurality of types of power supply voltages, and terminals TA13 and TA14 not connected to the filter circuit on the effect control board 12 are one type. Since the power supply voltage can be supplied and the terminals TA13 and TA14 are arranged outside the terminals TA15 to TA24 and the like, an appropriate substrate configuration becomes possible.

The terminals TA13 to TA24, TA27, and TA28, which are power supply voltage terminals, are arranged between the terminals TA11, TA12, which are ground terminals, and the terminals TA29, TA30, which are ground terminals, so that an appropriate board configuration is possible. become.

In the receptacle KRE2, the terminals TA13 and TA14 included in the second power supply voltage terminal and the terminals TA15 to TA24 included in the first power supply voltage terminal are the terminals TA11 and TA12 included in the first ground terminal and the second ground terminal. The terminals TA27 and TA28 arranged between the terminals TA25 and TA26 included in the first power supply voltage terminal are the terminals TA25 and TA26 included in the second ground terminal and the terminals TA29 included in the third ground terminal. , By arranging it between the TA30 and the TA30, an appropriate substrate configuration becomes possible.

Alternatively, in the effect control board 12, after branching the power supply voltage VDD2 of 1 into a power supply voltage VDC for driving a specific electric component and a power supply voltage VDS for supplying the amplifier circuit 521, the filter circuit 131a is provided. By supplying the power supply voltage VDS stabilized by the use to the amplifier circuit 521, an appropriate substrate configuration becomes possible.

By making the wiring length LL2 from the filter circuit 131a to the amplifier circuit 521 shorter than the wiring length LL1 from the branching of the power supply voltage VDC at the branch point DB1 to the input to the filter circuit 131a, an appropriate board configuration can be obtained. It will be possible.

Alternatively, in the noise prevention circuits 135a and 135b, an appropriate substrate configuration can be made by using a resistor which is a circuit element different from the noise prevention circuit 135c.

The noise prevention circuits 135a and 135b are provided corresponding to the power supply voltage for driving a specific electric component such as a motor or LED, and the noise prevention circuit 135c is used as a power supply voltage for driving a specific electric circuit such as a CPU or ROM. Correspondingly provided, an appropriate board configuration becomes possible.

Alternatively, in the step-down converter circuit 132, the power supply voltage VDD3 stabilized by the filter circuit 131c is input, and the power supply voltage of 1.05 V DC and the power supply voltage of 3.3 V DC are output, and in the regulator circuit 133, the DC power supply voltage is DC. By inputting a power supply voltage of 3.3V and outputting a power supply voltage of DC 1.5V, an appropriate board configuration becomes possible.

The power supply voltage VDC, which is the same as or substantially the same as the voltage supplied to the buck converter circuit 132, is supplied to the power supply monitoring circuit 140 to enable an appropriate board configuration.

The power supply voltage of 1.05 V DC output from the buck converter circuit 132 is supplied to a specific microprocessor such as a graphics processor of the display control unit 123, so that an appropriate board configuration can be made.

The DC 3.3V power supply voltage output from the buck converter circuit 132 is supplied to the ROM 121, for example, and starts before the electric components such as the RAM 122 driven by the DC 1.5V power supply voltage output from the regulator circuit 133. By making it possible, an appropriate substrate configuration is possible.

The DC 1.5V power supply voltage output from the regulator circuit 133 is supplied to a board configured as a board different from the effect control board 12, such as a RAM 122, so that an appropriate board configuration can be achieved.

(Explanation of problem-solving means and effects of feature section 30AK)
For example, a game machine capable of playing a game such as a pachinko game machine 1, for example, as shown in FIG. 17, a pattern constituting a plurality of signal wirings is formed, and a plurality of electric wires such as a RAM 102 and a CPU 103 are formed by the plurality of signal wirings. A substrate such as a main substrate 11 to which components are connected is provided, and a pattern includes a parallel wiring portion having a first shape in which a plurality of signal wirings are parallel or substantially parallel, for example, region 30AK10R, and a plurality of signals such as region 30AK11R. At least one signal wiring of the wiring includes a specific wiring portion having a second shape that is not parallel to the other signal wiring, and the wiring length of each signal wiring included in the plurality of signal wirings is the same or substantially the same. Become. This enables an appropriate board configuration that reduces the delay time difference of signals transmitted by a plurality of signal wirings.

For example, in the signal wiring that does not include the second shape, such as the signal wiring formed by the wiring pattern 30AK10D, the distance between the connection terminals in a plurality of electrical components is the second, for example, the signal wiring formed by the wiring patterns 30AK11D to 30AK13D. It may be longer than the signal wiring including the shape. As a result, an increase in the board area on which the wiring pattern is arranged is suppressed, and an appropriate board configuration for miniaturizing the board becomes possible.

For example, a conductor may not be provided in a predetermined region close to the signal wiring having the second shape, such as the space region 30AK0SP. This enables an appropriate substrate configuration in which electromagnetic interference due to electromagnetic noise in a plurality of signal wirings is prevented or suppressed.

The board is provided with through holes such as through holes 30AK1H and 30AK2H that can electrically connect the signal wiring provided on one surface of the board and the signal wiring provided on the other surface of the board, and a plurality of signal wirings are provided. The wiring length of each signal wiring included in the above may be the same or substantially the same for the signal wiring connected by the through hole, including the length of the through hole. This enables an appropriate board configuration that reduces the delay time difference of signals transmitted by a plurality of signal wirings.

The substrate includes a plurality of layers such as a front surface layer 30AK1S, a ground layer 30AK1L, a power supply layer 30AK2L, a wiring layer 30AK3L, a power supply layer 30AK4L, and a back surface layer 30AK2S, and a signal wiring having a second shape among the plurality of layers is provided. The signal may not be transmitted in the conductor layer such as the ground layer 30AK1L adjacent to the layer. This enables an appropriate substrate configuration in which electromagnetic interference due to electromagnetic noise in a plurality of signal wirings is prevented or suppressed.

As a plurality of electric components, a processing means capable of executing a predetermined process such as a CPU 103 and a storage means capable of storing information related to the execution of the process such as a RAM 102 may be connected. This enables an appropriate substrate configuration that reduces the delay time difference of signals transmitted by a plurality of signal wirings connected to a processing means or a storage means as a plurality of electric components.

Alternatively, for example, a gaming machine capable of playing a game such as a pachinko gaming machine 1, for example, as shown in FIG. 17, a pattern constituting a plurality of signal wirings is formed, and a plurality of RAM 102, CPU 103, etc. are formed by the plurality of signal wirings. A plurality of patterns are provided, such as a parallel wiring portion having a first shape in which a plurality of signal wirings are parallel or substantially parallel, such as a region 30AK10R, and a plurality of patterns such as a region 30AK11R. The signal wiring of the above may include a specific wiring portion having a second shape different from the first shape, and the wiring length of each signal wiring included in the plurality of signal wirings may be the same or substantially the same. This enables an appropriate board configuration that reduces the delay time difference of signals transmitted by a plurality of signal wirings.

Alternatively, it is a game machine capable of playing a game such as a pachinko game machine 1, and as shown in FIG. 17, for example, a pattern constituting a plurality of signal wirings is formed, and a plurality of RAM 102, CPU 103, etc. are formed by the plurality of signal wirings. The pattern includes a substrate such as a main substrate 11 to which the electrical components of the above are connected, and the pattern is a first shape including a linear shape or a substantially linear shape in at least one signal wiring among a plurality of signal wirings such as a wiring pattern 30AK10D. And the second pattern in which other signal wirings that are not included in the first pattern among the plurality of signal wirings, such as wiring patterns 30AK11D to 30AK13D, have a second shape different from the first shape. In the first pattern and the second pattern, the wiring length of each signal wiring included in the plurality of signal wirings may be the same or substantially the same. This enables an appropriate board configuration that reduces the delay time difference of signals transmitted by a plurality of signal wirings.

Alternatively, it is a game machine capable of playing a game such as a pachinko game machine 1, and as shown in FIG. 17, for example, a pattern constituting a plurality of signal wirings is formed, and a plurality of RAM 102, CPU 103, etc. are formed by the plurality of signal wirings. A board such as a main board 11 to which the electrical components of the above are connected is provided, and the pattern is a wiring in which at least one signal wiring among a plurality of signal wirings connects a predetermined section such as the section 30AK0SC at the shortest or substantially the shortest distance. Wiring patterns 30AK12D, 30AK13D, etc., in which the first pattern such as patterns 30AK10D and 30AK11D and other signal wirings that are not included in the first pattern among a plurality of signal wirings connect a predetermined section at a longer distance than the first pattern. In the first pattern and the second pattern, the wiring lengths of the respective signal wirings included in the plurality of signal wirings may be the same or substantially the same. This enables an appropriate board configuration that reduces the delay time difference of signals transmitted by a plurality of signal wirings.

In the first pattern, the distance between the connection terminals in the plurality of electric components may be longer than that in the second pattern. As a result, an increase in the board area on which the wiring pattern is arranged is suppressed, and an appropriate board configuration for miniaturizing the board becomes possible.

For example, a conductor may not be provided in a predetermined region close to the second pattern, such as the space region 30AK0SP. This enables an appropriate substrate configuration in which electromagnetic interference due to electromagnetic noise in a plurality of signal wirings is prevented or suppressed.

The substrate includes a plurality of layers such as a front surface layer 30AK1S, a ground layer 30AK1L, a power supply layer 30AK2L, a wiring layer 30AK3L, a power supply layer 30AK4L, and a back surface layer 30AK2S, and signal wiring included in the second pattern among the plurality of layers is provided. The signal may not be transmitted in the conductor layer such as the ground layer 30AK1L adjacent to the layer. This enables an appropriate substrate configuration in which electromagnetic interference due to electromagnetic noise in a plurality of signal wirings is prevented or suppressed.

1 ... Pachinko game machine 11 ... Main board 12 ... Production control board 13 ... Voice control board 19 ... Driver board 120 ... CPU for production control
121 ... ROM
122 ... RAM
123 ... Display control unit 131a to 131c, 511 ... Filter circuit 132 ... Buck converter circuit 133 ... Regulator circuit 140 ... Power supply monitoring circuit 521 ... Amplifier circuit 800 ... Board case 802 ... Cover members KRE1 to KRE4 ... Receptacles 30AK10G, 30AK11G, 30AK20G ... Ground conductor 30AK01R, 30AK10R, 30AK11R, 30AK12R,
30AK20R ... Area 30AK0SC ... Section 30AK10D to 30AK13D, 30AK10CK, 30AK10CS,
30AK10RS, 30AK10A-30AK14A, 30AK10P,
30AK11P, 30AK20P ... Wiring pattern 30AK1S ... Front layer 30AK2S ... Back layer 30AK1L ... Ground layer 30AK2L, 30AK4L ... Power supply layer 30AK3L ... Wiring layer 30AK1H, 30AK2H ... Through hole

Claims (1)

It is a gaming machine that can play games,
A power supply board that can supply power to electrical components,
A control board that receives power supply voltage from the power supply board is provided.
The control board is
A control circuit that can control the progress of the production,
A generation circuit that can generate the power supply voltage used in the control circuit,
A stabilization circuit that stabilizes the power supply voltage,
An audio circuit that can output audio signals and
Including a monitoring circuit that can monitor the power supply voltage,
The generation circuit generates a predetermined output voltage, which is a voltage lower than the predetermined input voltage, from a predetermined input voltage input to the generation circuit.
The monitoring circuit can monitor the predetermined input voltage and output a specific signal to the control circuit when the voltage value of the predetermined input voltage is lower than the predetermined value.
As supply voltage that will be supplied from the power supply board includes a first power supply voltage, a second power supply voltage different from the said first power supply voltage,
After branching the first power supply voltage into a power supply voltage for driving a specific electric component and a power supply voltage for supplying the voice circuit, the power supply voltage stabilized by the stabilization circuit is transferred to the voice circuit. Supply to
The particular electrical component includes a current driven circuit element.
The power supply voltage for driving a particular electrical component, the power supply path after branching the first supply voltage is connected to the noise reduction circuit,
The wiring from the stabilizing circuit to the audio circuit is shorter than the wiring length from the branches of the first power supply voltage to be input to the stabilization circuit,
The second power supply voltage is not connected to the stabilizing circuit.
A gaming machine characterized by that.

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