JP2006271685A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine which can prevent a fraudulent attempt to make the game machine shift to the special game status advantageous for the players. <P>SOLUTION: The main control board 120 is provided with a voltage converter 124 which converts a 12V power source supplied from a power source circuit 111 of a power source board 110 to a 5V control power source to be supplied to a CPU 123 for controlling the total operation of a pachinko game machine 1 and a RAM 123b for storing the game information changed during the games and a power failure detection circuit 125 which outputs a power failure advance notice detection signal based on the result of the comparison of the voltage value of the 12V power source to be supplied from the power source circuit 111 with a threshold Vs (set value). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a gaming machine, and more particularly to a gaming machine that can prevent fraud.

The pachinko machine has a control board on which a control circuit for operating the pachinko machine according to the game state is mounted (a main control board on which a main control circuit for controlling the entire game operation is arranged, a game ball A payout control board or the like on which a payout control circuit for controlling the payout operation is provided.
As shown in FIG. 7, a main control circuit unit 123 is provided in the main control circuit of the main control board 120. The main control circuit unit 123 includes a CPU 123a that controls the operation of the main control circuit, a RAM 123b that temporarily stores game information that changes during the game (for example, various random numbers for determination, the number of winning balls, a jackpot game state, and the like). ing. Although not particularly shown, the payout control circuit of the payout control board is provided with a payout control circuit unit. The payout control circuit unit is provided with a CPU for controlling the operation of the payout control circuit, a RAM for temporarily storing game information such as game ball payout information, and the like. The main control circuit unit 123 and the payout control circuit unit described above are mainly operated by a control power source such as DC5V.
Further, the main control board 120 is provided with a DC34V use circuit 121 that operates using DC34V and a DC12V use circuit unit 122 that operates using DC12V. As the DC34V use circuit 121, for example, a solenoid drive circuit for operating an opening / closing device of a large winning opening or a starting winning opening is provided. As the DC12V use circuit 121, for example, a sensor for detecting a winning game ball is provided.
Further, the payout control board is provided with a DC34V use circuit unit that operates using DC34V and a DC12V use circuit that operates using DC12V (not shown in particular). As the DC34V use circuit unit, for example, a payout motor drive circuit for paying out game balls is provided. As the DC12V use circuit, for example, a count switch for counting the game balls actually paid out is provided.
Thus, since each control board has a circuit that operates with power supplies of various voltage values, the external power input (AC24V power supply is frequently used) input to the pachinko machine is DC34V, DC12V. , A power supply substrate 110 having a power supply circuit 111 for converting to a power supply of various voltage values such as DC5V (hereinafter, description of DC is omitted and referred to as 34V power supply, 12V power supply, and 5V control power supply) is provided. (See Patent Document 1). The 34V power supply, 12V power supply, and 5V control power converted by the power supply board 110 are supplied to each control board via power supply wiring.

Further, the power supply substrate 110 is provided with a power failure detection circuit 112. The power failure detection circuit 112 outputs a power failure warning detection signal based on the voltage value of the 12V power source of the power circuit 111. That is, when the power failure detection circuit 112 detects that the voltage value of the 12V power supply has decreased to the threshold value (set value) Vs (V) due to a power failure or the like (also see FIG. 8), it outputs a power failure warning detection signal. The power failure notice detection signal is output to the main control board 120 via the signal wiring. In the power supply circuit 111, the voltage value of the 5V control power supplied from the power supply board 110 is provided in the main control board 120 for a predetermined period from when the power failure notice detection signal is output from the power failure detection circuit 112. The CPU 123a is configured to maintain an operable value of 4.75V or higher.
When the power failure notice detection signal is input, the CPU 123a of the main control board 120 performs the power failure process during the predetermined period. Specifically, the sum value of the sum check of the RAM 123b executed by the CPU 123a when the power is restored is calculated and stored in the save area. Note that the RAM 123b is backed up by a backup power source (a capacitor or the like) so that data temporarily stored in the RAM 123b is retained for a set period after a power failure. As a result, the power failure recovery process is performed when the power is restored, and the result of the sum check is OK (the sum value calculated from the data stored in the RAM 123b matches the sum value stored in the save area of the RAM 123b). In this case, the pachinko machine is configured to be able to continue the game state before the power failure.

The power supply substrate 110 is provided with a RAM clear switch 113. When the RAM clear switch 113 is operated, a RAM clear signal is output to the main control board 120 via the signal wiring. When the RAM clear switch 113 is being operated, the CPU 123a of the main control board 120 clears the RAM 123b when the pachinko machine 1 is turned on and the 5V power supply is turned on to start the operation. Thereby, the staff of the game hall can clear and initialize the game state information currently stored in the RAM 123b when the pachinko machine 1 is turned on. For example, in a pachinko machine that has finished in a high probability state when the store is closed, the power failure process described above is performed when the power is turned off. In addition, game information indicating a high probability state is backed up and stored in the RAM 123b of the main control circuit unit 123 for a set period. Then, when the pachinko machine is turned on when the store is opened the next day, a power failure recovery process is performed and if the result of the sum check is OK, it starts in a high probability state. This state can be resolved by operating the switch 113 to turn on the power of the pachinko machine 1.
JP 2001-62046 A

In the conventional pachinko machine, the power failure detection circuit 112 is provided on the power supply board 110, and when a power failure warning detection signal is output from the power failure detection circuit 112, it is output to the main control board 120 via the signal wiring. If this signal wiring is disconnected or short-circuited for some reason, when the output voltage of the 12V power supply drops below the threshold value (set value) Vs (V) due to a power failure or the like, the main control board 120 receives a power failure warning detection signal. Not entered. Therefore, the CPU 123a of the main control board 120 does not perform a power failure process. In this case, since the sum value due to the power failure processing is calculated and not stored, the sum check result of the RAM 123b becomes NG in the power failure recovery processing at the time of power recovery by the CPU 123a (the sum calculated from the data stored in the RAM 123b). The CPU 123a clears and initializes the data in the RAM 123b, and the sum value stored in the save area of the RAM 123b does not match.
In the conventional pachinko machine, the 5V control power converted by the power supply board 110 is supplied to the main control board 120 and the payout control board 130 via the power supply wiring. When the power supply wiring of the 5V control power supply is disconnected or short-circuited for some reason, as shown in FIG. 9, the voltage of the control power supply falls below the operating voltage without the time for the CPU 123a of the main control board 120 to perform power failure processing. . Also in this case, since the sum value due to the power failure processing is calculated and not stored, the sum check result of the RAM 123b becomes NG in the power failure recovery processing at the time of power recovery by the CPU 123a (calculated from the data stored in the RAM 123b). The sum value does not match the sum value stored in the save area of the RAM 123b), and the CPU 123a clears and initializes the data in the RAM 123b.

By the way, in the pachinko machine, a lottery is performed by winning a game ball at the start winning opening, and if the result of the lottery is a win, a special game state (big hit game state) advantageous to the player is started. In this lottery, the CPU 123a of the main control circuit unit 123 uses the value of the jackpot determination random number counter (provided in a predetermined area of the RAM 123b) as the jackpot determination random number at the timing when the game ball wins the start winning opening. This is done by determining whether or not the acquired jackpot determination random number is a preset hit value. As the jackpot determination random number counter, an “initial value update type” random number counter shown in FIG. 10 is frequently used. For example, the random number counter repeatedly counts numerical values from “0” to “299”. If the random number acquired by the CPU 123a is “120”, the winning probability is 1/300.
The random number counter starts from “0” when the RAM 123b is initialized. Then, the initial value of the next cycle is acquired at a predetermined timing until “299” is counted (one cycle). In the example shown in FIG. 10, the initial value “30” of the second cycle is acquired at a predetermined timing of the first cycle. Therefore, if counting up to “299” in the first cycle, the second cycle starts from “30”. Then, after counting up to “299”, it returns to “0”, counts up to “29”, and ends the second cycle. The initial value of the third cycle is acquired at a predetermined timing of the second cycle, and the third cycle starts from the acquired initial value. Similarly, counting is performed while updating the initial value. According to this, the timing at which the value of the random number counter (big hit determination random number) becomes the winning value “120” is not equally spaced, and the timing at which the value of the big number determination random number counter becomes the winning value is predicted. I can't.
However, even if the “initial value update type” random number counter is used as the jackpot determination random number counter, as described above, in the first cycle when the RAM 123b is initialized, the random number for jackpot determination is The timing when the winning value is “120” can be predicted. Therefore, the pachinko machine is in a state in which the power supply wiring of the 5V control power supplied from the power supply board 110 to the main control board 120 is intentionally short-circuited and then restored, or the signal wiring of the power failure warning detection signal is intentionally disconnected or short-circuited. By turning on the input power after shutting off the input power of 1, the RAM 123b is intentionally initialized, and a signal as if the game ball has won the winning opening is input at the timing when the jackpot determination random number becomes a winning value, There has been a risk of fraud in which the pachinko machine 1 is made into a big hit gaming state.
The problem to be solved by the present invention is to provide a gaming machine that can prevent a fraud that makes the gaming machine a special gaming state advantageous to a player.

In order to achieve the above object, the invention according to claim 1 is configured.
According to the first aspect of the present invention, a gaming machine including a power supply board, a power failure detection circuit, and a main control board is configured.
The power supply board is provided with a power supply circuit that supplies power to the main control board.
The power failure detection circuit outputs a power failure warning detection signal based on a comparison result between the voltage value of the power supplied from the power circuit and the set value.
The main control board is provided with a main control circuit for controlling the operation of the entire gaming machine to which control power is supplied and a main memory circuit for storing game information that changes during the game.
This main control circuit generates a judgment information using the game information stored in the main memory circuit and writes it in the main memory circuit when the power failure notice detection signal is output from the power failure detection circuit, and performs control. When the power is restored, it is determined whether or not the game information stored in the main memory circuit is normal based on the determination information written in the main memory circuit, and stored in the main memory circuit based on the determination result. A power failure recovery process for determining the processing method of the game information being performed is performed.
The gaming machine of the present invention has a voltage conversion circuit that converts the voltage value of the power supply supplied from the power supply circuit into the voltage value of the control power supply, and the voltage conversion circuit and the power failure detection circuit are provided on the main control board.
The “power supply circuit” converts, for example, an AC 24V power source into a DC 12V power source.
As the “main control circuit”, a CPU is typically used, and as the “main memory circuit”, a RAM in which data can be rewritten at any time by the CPU is typically used. The “main control circuit” and the “main memory circuit” are integrally configured as a control IC.
“Game information that changes during a game” means at least game information that changes during a game, and includes game information that changes according to a game and game information that changes regardless of the game. As the “game information that changes at the time of game”, for example, game information such as various random numbers including jackpot determination random numbers, jackpot game state occurrence information, output command signals, the number of game media paid out from the payout device, etc. Can do.
As the “determination information”, information that can determine whether or not the game information written in the main memory circuit has changed after the power failure process until the power is restored is used. For example, parity data or a sum value generated based on game information written in the main memory circuit is used. When the parity data generated based on the game information written in the main memory circuit is used as the determination information, for example, the parity data written in the main memory circuit in the power failure recovery process at the time of power recovery is used. The game information written in the main memory circuit is determined according to whether it is a predetermined value, whether the data generated based on the parity data written in the main memory circuit matches the predetermined data, etc. It is determined whether or not the game information is normal, and a game information processing method is determined. Further, when using the thumb value generated based on the game information written in the main memory circuit as the determination information, for example, in the game information written in the main memory circuit in the power failure recovery process at the time of power recovery Whether the game information written in the main memory circuit is normal or not is determined according to whether the sum value generated based on the sum value written in the main memory circuit is the same. Determine the processing method.
As the “game information processing method”, for example, if it is determined that the game information written in the memory circuit is normal, the control circuit uses the game information currently stored in the memory circuit to play a game A method of performing the action is used. If it is determined that the game information written in the memory circuit is not normal, the control circuit uses a method of clearing and initializing the game information currently stored in the memory circuit.
As the “voltage conversion circuit” that converts the voltage value of the power supply voltage supplied from the power supply circuit of the power supply board into the voltage value of the control power supply, for example, a three-terminal regulator that converts DC12V to DC5V is used. And, as a “setting value” for the power failure detection circuit to output a power failure warning detection signal, the main control circuit will be able to During the power failure process, a value is set such that the “voltage conversion circuit” can output a control power supply having a voltage value equal to or higher than the operating voltage of the main control circuit.

In the gaming machine according to the first aspect, a power failure detection circuit is provided on the main control board. Therefore, it is not necessary to provide signal wiring for outputting a power failure notice detection signal between the power supply board and the main control board. As a result, the signal wiring of the power failure warning detection signal can be disconnected or short-circuited, and the illegality of intentionally clearing and initializing the main memory circuit can be prevented.
Further, the control power supply of the main control circuit and the main storage circuit of the main control board is obtained by converting the power supplied from the power supply circuit by a voltage conversion circuit provided on the main control board. Therefore, it is not necessary to provide power supply wiring for supplying control power between the power supply board and the main control board. As a result, the power supply wiring for supplying the control power can be short-circuited to prevent the main memory circuit from being intentionally cleared and initialized.
When the main memory circuit is initialized, the timing at which the lottery result is won can be predicted, and there is a risk that the gaming machine is deliberately put into a big hit gaming state. If the gaming machine of the present invention is used, it is possible to prevent fraud in which the gaming machine is in a special gaming state advantageous to the player.

  According to the present invention, there is provided a gaming machine that can prevent a fraud that intentionally makes a gaming machine a special gaming state advantageous to a player.

(First embodiment)
A first embodiment of the gaming machine of the present invention will be described with reference to FIGS. In the present embodiment, the present invention is configured as a pachinko machine.
In the pachinko machine according to the present embodiment, a control board on which a control circuit is arranged (a main control board on which a main control circuit for controlling the whole game operation is arranged, a payout control circuit for controlling a prize ball operation is provided. DC12V power output from the power supply board is supplied to the payout control board and the like provided. Each control board is provided with a voltage converter, and the voltage converter converts a DC 12V power source into a DC 5V control power source. The DC 5V control power source converted by each voltage converter is used by a CPU or RAM provided in a control circuit section provided on each control board. The main control board is also provided with a power failure detection circuit that detects a power failure state and outputs a power failure warning detection signal.
FIG. 1 is a schematic configuration diagram of a pachinko machine viewed from the back side. FIG. 2 is a block diagram showing wiring between the power supply board and the main control board.

  First, a schematic configuration of the back side of the pachinko machine 1 will be described with reference to FIG. A plurality of control boards are provided on the back side of the pachinko machine 1. In the pachinko machine 1 shown in FIG. 1, a power supply board 110 provided with a power supply circuit for converting an AC 24V input power to a DC 12V and DC 34V power supply, and a main control circuit for controlling the gaming operation of the entire pachinko machine 1 are provided. Main control board 120, payout control board 130 provided with a payout control circuit for controlling the payout operation of the game ball, display control board 140 provided with a display control circuit for controlling the display operation, main control board A sub-control board 150 that outputs a sub-command signal to the display control board 140 based on the main command signal input from 120 is provided.

In each control board, electrical components are mounted mainly on the surface side of the control board, and each electrical component is connected by a wiring pattern of the control board. Each control board is accommodated in a board box in which the accommodated control board can be visually recognized from the outside. In each control board, a connector portion connected to another control board or the like by power supply wiring or signal wiring is provided on the outer peripheral portion of the board box.
The board box in which each control board is accommodated is disposed on the back side of the pachinko machine 1 so that the front side of each control board can be seen. (Actually, as shown in FIG. 1, the substrate box in which the power supply substrate 110 is accommodated is hidden in the substrate box in which the dispensing control substrate 130 is accommodated, so that the dispensing control substrate 130 is accommodated. When the removed board box is removed, it is arranged so that the front side of the power supply board 110 can be seen, and the board box containing the sub-control board 150 is hidden behind the board box containing the main control board 120. Therefore, when the board box in which the main control board 120 is housed is removed, the front side of the sub control board 150 can be seen.)
In the pachinko machine 1 shown in FIG. 1, a board box in which the power supply board 110 is accommodated is disposed at the lower part in the vertical direction on the back side of the pachinko machine 1. Then, the board box in which the payout control board 130 is accommodated overlaps the board box in which the power supply board 110 is accommodated so that the connector portion provided on the left side of the power supply board 110 is exposed on the back side of the pachinko machine 1. It is arranged in a state.
In addition, a substrate box in which the sub-control board 150 is accommodated is disposed in the upper part in the vertical direction of the substrate box in which the power supply substrate 110 is accommodated. Then, the board box in which the main control board 120 is housed is replaced with the board box in which the sub control board 150 is housed so that the connector portion provided on the left side of the sub control board 150 is exposed on the back side of the pachinko machine 1. It is arranged in an overlapping state.
A back cover 200 of the pachinko machine 1 is provided in the upper part in the vertical direction of the substrate box in which the sub control board 150 is accommodated and the substrate box in which the main control board 120 is accommodated, and the display control board 140 is provided in the back cover 200. A substrate box and a liquid crystal display are accommodated.
The “main control board 120” of the present embodiment corresponds to the “main control board” of the present invention. The “power supply board 110” of the present embodiment corresponds to the “power supply board” of the present invention. In addition, the DC12V power supply of the present embodiment corresponds to the “power supply supplied from the power supply circuit” of the present invention.

Next, the configuration of the power supply board 110 and the main control board 120 will be described using the block diagram shown in FIG. Note that the control boards other than the main control board 120 are not related to the gist of the present invention, and thus the description thereof is omitted.
In the power supply board 110, the AC 24V power supplied from the outside of the pachinko machine 1 is converted into DC 12V and DC 34V (hereinafter, “DC” is omitted and referred to as 12V power and 34V power) using the power circuit 111.
Then, the 34V power converted by the power supply board 110 is supplied to the main control circuit of the main control board 120 via the output terminal 11 of the power supply board 110, the power supply wiring L1, and the input terminal 21 of the main control board 120. The 12 V power converted by the power supply board 110 is supplied to the main control circuit of the main control board 120 via the output terminal 12 of the power supply board 110, the power supply wiring L2, and the input terminal 22 of the main control board 120. .

Further, the power supply substrate 110 is provided with a RAM clear switch (memory clear switch) 113 similar to the conventional technology.
The RAM clear switch 113 is disposed at a position where it can be operated from the back side of the pachinko machine 1 in a state where the power supply board 110 is disposed in the pachinko machine 1 as shown in FIG.
When the RAM clear switch 113 is operated, a RAM clear signal (memory clear signal) is output to the main control board 120 via the output terminal 13 of the power supply board 110, the signal wiring L3, and the input terminal 23 of the main control board 120. The

In the main control board 120, the 34V power supplied from the power supply board 110 is supplied to the 34V use circuit unit 121 of the main control circuit. The 34V use circuit unit 121 is provided with a solenoid drive circuit or the like (not shown in particular) for operating the opening / closing device of the special winning opening or the start opening.
The 12V power supplied from the power supply board 110 is supplied to the 12V use circuit unit 122, the voltage converter 124, and the power failure detection circuit 125 of the main control circuit.
The 12V use circuit unit 122 includes a command transmission / reception circuit that transmits / receives a command signal to / from another control board, a ball proximity switch that detects that a pachinko ball has won a prize winning opening or a starting opening, etc. (not particularly shown). ) Is provided.
The voltage converter 124 converts the supplied 12V power source into a 5V control power source. The control power source converted by the voltage converter 124 is supplied to the main control circuit unit 123 including the CPU 123a, the RAM 123b, the backup capacitor 123c, and the like.
When the voltage value of the supplied 12V power supply falls below the threshold value (set value) Vs (when the power supply voltage of the 12V power supply gradually drops due to a power failure or the power supply wiring of the 12V power supply is disconnected or short-circuited, the power failure detection circuit 125 The power failure notice detection signal is output to the main control circuit unit 123.
When a RAM clear signal is input from the power supply substrate 110 via the input terminal 23, the RAM clear signal is input to the main control circuit unit 123. When the RAM clear switch 113 is operated, the CPU 123a of the main control board 120 clears and initializes each RAM 123b when the 5V power supply rises (reaches the operating voltage value) and starts operation.
In addition, the voltage converter 124 is configured such that the voltage value of the 5V control power source output from the voltage converter 124 is operable by the CPU 123a for 7 ms after the power failure warning detection signal is output from the power failure detection circuit 112. .75V or more is held.

With this configuration, the CPU 123a of the main control board 120 performs the power failure process within the above 7 ms when the power failure notice detection signal is input. Specifically, the sum value (check data) of the data stored in the RAM 123b is calculated and stored in a predetermined area (evacuation area) when the power failure notice detection signal is input. The data temporarily stored in the RAM 123b is backed up by the backup capacitor 123c so that it is retained for 3 hours or more after a power failure. When the result of the sum check (check data check) is OK when power is restored (when the sum value calculated from the data stored in the RAM 123b matches the sum value stored in the save area of the RAM 123b). ), The pachinko machine 1 is configured to be able to start the game from the game state before the power failure. On the other hand, when the power failure process has not been performed, or when the RAM data backup time has elapsed, the result of the sum check is NG when the power is restored (the sum value calculated from the data stored in the RAM 123b, The sum value stored in the save area of the RAM 123b becomes inconsistent), and the CPU 123a clears and initializes the RAM 123b.
The “CPU 123a of the main control circuit unit 123” of the present embodiment corresponds to the “main control circuit” of the present invention. The “RAM 123b of the main control circuit unit 123” of the present embodiment corresponds to the “memory circuit” of the present invention. The “threshold value Vs” corresponds to the “set value” in the present embodiment.

In the pachinko machine 1 of the present embodiment, a power failure detection circuit 125 is provided on the main control board 120. Therefore, it is not necessary to provide signal wiring for outputting a power failure notice detection signal between the power supply board 110 and the main control board 120. As a result, in the state in which the signal wiring of the power failure warning detection signal is disconnected or short-circuited, by deliberately turning off the power supply and then returning it, the main memory circuit 123b is cleared and initialized. Can be prevented.
Further, the 12V power supplied from the power supply board 110 is converted into the 5V control power by the voltage converter 124 provided on the main control board. Thereby, it is not necessary to provide the power supply wiring of the 5V control power supply between the power supply board 110 and the main control board 120. Thereby, the power supply wiring of the 5V control power supply can be short-circuited, and illegal use utilizing intentionally initializing the RAM 123b of the main control circuit unit 123 can be prevented.
Therefore, according to the pachinko machine 1 of the present embodiment, the RAM 123b of the main control circuit unit 123 of the main control board 120 is intentionally initialized, thereby predicting the timing at which the lottery result is won, and hitting the pachinko machine 1 with a big hit It is possible to prevent fraud in the state.
Even if the power supply wiring of the 12V power supply is short-circuited, the voltage value of the 5V control power supply supplied from the voltage conversion device 124 is kept at the operating voltage value (4.75V) or more of the CPU 123a during the period during which the power failure process is possible. In addition, a power failure notice detection signal is output from the power failure detection circuit 125 to the main control circuit unit 123. For this reason, CPU123a can perform a power failure process normally. Therefore, there is no problem even if the power supply wiring of the 12V power supply is routed between the substrates.

In the first embodiment, the case where the RAM clear switch 113 is provided on the power supply board 110 has been described, but the RAM clear switch may be provided on the main control board 120 as shown in FIG. Good.
Even in this case, the RAM clear switch is disposed at a position where it can be operated from the back side of the pachinko machine 1 in a state where the main control board 120 is disposed in the pachinko machine 1 as shown in FIG. Since the RAM clear switch is provided on the main control board 120, it is not necessary to provide a signal wiring for the RAM clear signal between the power supply board 110 and the main control board 120. Accordingly, the illegal operation of intentionally initializing the RAM 123b of the main control circuit unit 123 is prevented by turning on the power after the RAM clear signal is illegally input to the signal wiring for the RAM clear signal. be able to. Therefore, the RAM 123b of the main control circuit unit 123 of the main control board 120 is intentionally initialized, thereby more effectively preventing the fraud that makes the pachinko machine 1 a big hit state by predicting the timing when the lottery result is won. Can do.

(Second Embodiment)
Next, a second embodiment of the gaming machine of the present invention will be described with reference to the flowcharts shown in FIGS.
In the present embodiment, in addition to the configuration of the pachinko machine of the first embodiment, when a power failure warning detection signal is output from the power failure detection circuit 125, the CPU 123a performs check data ( Sum check value or parity check parity data is calculated and stored in a predetermined area (save area) of the RAM 123b, and power failure processing information indicating that the power failure processing has been executed is written to the RAM. is doing. When the power is restored, the CPU 123a has a configuration for determining the processing mode of the game information written in the RAM 123b based on the power failure processing information and check data written in the RAM 123b.

First, the power failure process executed when the CPU 123a outputs a power failure notice detection signal from the power failure detection circuit 125 will be described with reference to the flowchart shown in FIG.
When the CPU 123a determines by polling that a power failure notice detection signal has been output from the power failure detection circuit 125, the CPU 123a sets interrupt inhibition in step B1. In the present embodiment, the CPU 123a executes a jackpot determination random number update process, a prize ball control process, and the like shown in FIG. 6 by a timer interrupt process. For this reason, when executing power failure processing, interrupt prohibition is set to prevent the power failure processing from being interrupted by a timer interrupt.
Next, in step B2, when power is turned on (when power is restored), check data is generated (calculated) to determine whether or not the game information written in the RAM 123b is normal, and is stored in the save area of the RAM 123b. Write. As the check data, for example, parity data or a sum value can be used.
When parity data is used, for example, parity data is generated (calculated) by the following method. First, the game information written in the RAM 123b is written in the save area of the RAM 123b, and initial data is written in the save area of the RAM 123b. Then, using the initial data and game information written in the save area of the RAM 123b, exclusive OR operation is sequentially performed to calculate operation data. For example, the operation data is calculated by performing an exclusive OR operation between the initial data written in the save area and the first game information written in the save area, and the calculated data is written to the save area. Calculation data is calculated by performing an exclusive OR operation with the second game information. Then, the calculation data calculated last is written in the parity data area of the RAM 123b.
When using the sum value, for example, the sum value is generated (calculated) by the following method. That is, the game information written in the RAM is written in the save area of the RAM 123b. Then, the sum value of the game information written in the save area of the RAM 123b is calculated, and the calculated sum value is written in the sum value area of the RAM.
Next, in step B3, check data is generated and written in the save area of the RAM 123b, that is, the power failure processing information indicating that the power failure processing has been executed normally (normal power failure processing has been executed) is stored in the RAM 123b. After writing to the power outage processing information area, power outage processing is terminated.
As the power failure processing information, it is possible to use various types of information that can determine that the normal power failure processing has been executed at the time of the power failure and that the normal power failure processing has not been executed at the time of the power failure. For example, when normal power failure processing is not executed, the first value (for example, “0”), and when normal power failure processing is executed, the second value (any value other than “0”) is set. The set power failure processing data can be used. Alternatively, it is possible to use a power failure processing flag that is reset when normal power failure processing is not executed, and that is set when normal power failure processing is executed.

Next, the power-on process (power failure recovery process) executed when the CPU 123a reaches the operating voltage value of the CPU 123a will be described with reference to the flowchart of FIG.
When the voltage value of the control power source of the CPU 123a reaches the operating voltage value of the CPU 123a, an initialization process is performed, and then a RAM clear signal is acquired in step A1. In the initialization process, a timer interrupt described later is prohibited.
In the present embodiment, in order to speed up the processing, when the power is turned on, the CPU 123a displays a lottery result using a design symbol or the like, and a display control circuit (not shown) that controls an effect display device (not shown). Is configured to execute a loop process (a process in steps A2 to A4 described later) that waits until the operation becomes possible. If the operation of the RAM clear switch is canceled during the execution of this loop processing, it cannot be determined that the RAM clear switch has been operated. Therefore, in this embodiment, the RAM clear signal is acquired before the loop process is executed.
Next, in step A2, a loop counter value is set.
Next, [[loop counter value] -1] is calculated in step A3.
In step A4, it is determined whether or not the loop counter value is “0” (step A4). When the loop counter value is not “0”, the process returns to step A3, and when the loop counter value becomes “0”, the process proceeds to step A5.

In step A5, it is determined whether or not the RAM clear signal acquired in step A1 is on (whether or not the RAM clear switch has been operated). If the RAM clear signal is on, it is determined that a pachinko store staff or the like has turned on the power while operating the RAM clear button, and the process proceeds to step A9. On the other hand, when it is not on (it is off), it progresses to step A6.
In step A6, the power failure processing information written in the power failure processing information area of the RAM 123b has been subjected to the normal power failure processing at the previous power failure (the check data has been written to the save area of the RAM 123b at the previous power failure). Is determined. For example, if the normal power failure process is not executed, the first value is set. If the normal power failure process is executed, the second value is set as the power failure process information. Is written, it is determined whether or not the power failure processing information written in the power failure processing information area of the RAM 123b matches the second value. If the normal power failure processing is not executed, the reset is performed. If the normal power failure processing is performed, the power failure processing flag that is set is written as the power failure processing information in the power failure processing information area of the RAM 123b. It is determined whether or not the power failure processing information written in the power failure processing information area is set. When the power failure processing information indicates that the normal power failure processing has been executed, it is determined that the power failure processing has been normally performed at the time of the previous power failure, and the process proceeds to Step A7. On the other hand, when the power failure processing information indicates that the normal power failure processing has not been executed, the power supply wiring pattern of the control power supply (the output wiring pattern of the voltage converter 124 shown in FIG. 2) is illegally short-circuited. It is determined that there is a possibility that the power supply has been restored, or that the control power supply may be turned off after the wiring pattern of the power failure warning detection signal (output wiring pattern of the power failure detection circuit 125 shown in FIG. 2) is improperly short-circuited. Then, the process proceeds to Step A10.

In step A7, the power failure processing information is cleared (power failure processing information indicating that normal power failure processing has not been executed is written), and then the process proceeds to step A8.
In step A8, it is determined whether or not the check data written in the RAM 123b is normal. If the check data written in the RAM 123b is normal, it is determined that the game state before the power failure may be started, and the process proceeds to Step A11. If the check data is not normal (abnormal), the check data is written in the RAM 123b. The game information is judged to have changed, and the process proceeds to step A9.
When parity data is used as check data, for example, it is determined whether the parity data is normal by the following method. That is, using the operation data written in the parity data area of the RAM 123b and the game information written in the save area of the RAM 123b, the exclusive logical operation is performed in the reverse order of calculating the operation data to obtain the operation data. calculate. For example, the operation data is calculated by performing an exclusive OR operation between the operation data written in the parity data area of the RAM 123b and the second game information written in the save area of the RAM 123b. Calculation data is calculated by performing an exclusive OR operation with the first game information written in the save area. And it is discriminate | determined whether the calculation data calculated at the end correspond with the initial data written in the save area | region of RAM123b. When the calculation data calculated last matches the initial data written in the save area of the RAM 123b, it is determined that the check data is normal. When the calculation data does not match, the check data is abnormal. Determine that.
When the sum value is used as the check data, for example, it is determined whether or not the sum value is normal by the following method. That is, the sum value of the game information written in the save area of the RAM 123b is calculated. Then, it is determined whether or not the calculated sum value matches the sum value written in the sum value area of the RAM 123b. When the calculated sum value matches the sum value written in the sum value area of the RAM 123b, it is determined that the check data is normal, and when it does not match, it is determined that the check data is abnormal. To do.

In step A9, the entire area of the RAM 123b is cleared (all game information written in the RAM 123b is cleared), and then the process proceeds to step A11.
By clearing the entire area of the RAM 123b, the count value of the jackpot determination random number counter (the jackpot determination random number) in a predetermined area of the RAM 123b is set to “0”. Therefore, in the first cycle after the power recovery process, the jackpot determination random number counter starts counting from “0” (see FIG. 10).
When the process proceeds from step A8 to step A9, the power failure processing information indicates that the normal power failure processing has been executed, that is, the power failure processing has been normally executed at the time of the previous power failure. In this case, there is no possibility that the previous power failure caused an illegal short circuit of the power supply wiring pattern or the power failure notice detection signal wiring pattern. Therefore, there is no problem even if the count of the jackpot determination random number counter is started from “0” in the first cycle after the power recovery process.
In a pachinko machine that has been finished in a high probability state when the store is closed, when the power is turned off, the game information indicating the high probability state is written in the save area of the RAM 123b by the power outage process described above. In this state, when the pachinko machine is turned on when the store is opened the next day, it starts in a high probability state. Therefore, in such a case, a pachinko store staff or the like turns on the power of the pachinko machine while operating the RAM clear switch. As a result, the RAM 123b is cleared in step A9, and the high probability state is eliminated.
That is, when proceeding from step A5 to step A9, the RAM 123b is cleared by the intention of a pachinko parlor or the like, and therefore the count of the jackpot determination random number counter is set to “0” in the first cycle after the power recovery process. It doesn't matter if you start with "".

In Step A10, after clearing the area other than the area in which the jackpot determination random number (count value of the jackpot determination random number counter) is written in the area of the RAM 123b, the process proceeds to Step A11.
In this case, since the power failure processing information does not indicate that the normal power failure processing has been executed, the previous power failure caused the power supply wiring pattern of the 5V control power supply of the main control board 120 to be short-circuited and restored, There is a risk that the signal wiring pattern of the notice detection signal is improperly short-circuited. Therefore, if the counter value of the jackpot determination random number counter is cleared and set to “0” and the count of the jackpot determination random number counter is started from “0”, the timing at which the jackpot determination random number becomes a hit value is predicted. can do.
Therefore, in this case, the area other than the area where the jackpot determination random number (count value of the jackpot determination random number counter) is written is cleared from the area of the RAM 123b. That is, the game information other than the jackpot determination random number written in the RAM 123b is cleared to “0”.
As a result, in the first cycle after the power recovery process, the jackpot determination random number counter starts counting from an arbitrary value (which may be “0”, but the probability is very low). It becomes difficult to predict the timing that matches the value.
In step A11, after the prohibition of the timer interrupt is canceled, the process proceeds to step A12.

In step A12, it is determined whether or not the power failure notice detection signal output from the power failure detection circuit 11 is on. That is, it is determined whether or not the voltage value of the power source has dropped below a threshold value (power failure voltage detection value) Vs. When the power failure notice detection signal is ON, the power failure process B shown in FIG. 5 is executed. On the other hand, when the power failure warning detection signal is not on (off), update processing C for random numbers other than the jackpot determination random number is executed. As the random numbers other than the jackpot determination random number, for example, a display time of the lottery result, an effect pattern random number for determining the effect pattern for effect display of the lottery result, an effect design random number for determining the effect symbol, and the like are used.
In step A13, it is determined whether or not a timer interrupt has occurred. If a timer interrupt has occurred, the process returns to step A12 after executing the timer interrupt process shown in FIG. On the other hand, if no timer interrupt has occurred, the process returns to step A12. In the present embodiment, the timer interrupt process D is executed every 4 ms.

Next, the outline of the timer interrupt process D will be described with reference to the flowchart of FIG.
In the timer interruption process D shown in FIG. 6, an input signal acquisition process D1, a timer subtraction process D2, a jackpot determination random number update process D3, a prize ball control process D4, a prize ball check process D5, a big prize opening control process D6, a lottery Result output control processing D7 and the like are executed.
In the input signal acquisition processing D1, processing for acquiring input signals such as a start winning detection signal and a winning detection signal is executed.
In the timer subtraction process D2, the execution time subtraction process is executed when the execution time is set such as when a variation pattern is displayed on the lottery result display device or the effect display device.
In the jackpot determination random number update process D3, for example, a process of updating the value of the jackpot determination random number counter written in a predetermined area of the RAM is executed.
In the prize ball control process D4, in response to an input of a detection signal indicating a prize such as a start prize detection signal or a prize detection signal, a prize ball command signal indicating the number of prize balls to be paid out from the payout device 300 is given out. Output to.
In the prize ball check process D5, an abnormal state relating to the payout from the payout device 300 (for example, a state where a big prize winning prize detection signal is output from the big prize winning prize detector despite being not in the big hit gaming state) is checked. Execute the process.
In the big prize opening control process D6, the result of the lottery performed by the input of the start winning detection signal is a win, and when the special gaming state is generated, the opening / closing driving device that drives the opening / closing member that controls the opening / closing of the big prize opening is controlled. A process of outputting a signal is executed.
In the lottery result output control process, a process for outputting a lottery result displayed on the lottery result display device to the lottery result display device for displaying the result of the lottery performed by the input of the start winning detection signal, and displaying the lottery result on the effect display device The process which outputs the subcommand signal for alerting | reporting with the production | presentation using the design symbol, the sound which generate | occur | produces from a speaker, the light emitted from lamps, such as LED, etc. to a sub-control circuit is performed.

As described above, in this embodiment, when a power failure warning detection signal is output from the power failure detection circuit, the power failure processing is performed while the check data is generated and written to the RAM, and the power failure processing is performed. The power failure processing information shown is configured to be written into the RAM.
When the voltage value of the control power supply reaches the operating voltage value of the control circuit when the power is turned on (when power is restored), the RAM is based on the operation state of the RAM clear switch, the check data written in the RAM, and the power failure processing information. The processing mode of the game information written in is determined.
That is, when the RAM clear switch is operated, the entire area of the RAM is cleared. As a result, the entire area of the RAM can be cleared by the operation of the RAM clear switch by an amusement store clerk or the like.
If the RAM clear switch is not operated, but the power failure processing information indicates that the normal power failure processing has not been executed, the jackpot determination random number (the value of the jackpot determination random number counter in the RAM area). ) Clear the area other than the area where is written. As a result, for example, the power supply wiring pattern of the control power supply may be restored after being improperly short-circuited, or the control power supply may be turned off after the power supply wiring pattern of the power failure warning detection signal is improperly short-circuited If there is, the jackpot determination random number is not cleared, and it is difficult to predict the timing when the jackpot determination random number becomes a winning value. Therefore, the special gaming state can be prevented from being illegally generated.
Further, the RAM clear switch is not operated, and the power failure processing information indicates that the normal power failure processing has been executed, but if the check data is abnormal, the entire area of the RAM is cleared. That is, the power failure process is normally executed at the time of the previous power failure, but if the game information written in the RAM changes for some reason during the power failure, the entire area of the RAM is cleared. In this case, since the power failure process is normally executed at the time of the previous power failure, there is no particular problem even if the entire area of the RAM is cleared.
Further, if the RAM clear switch is not operated, indicating that the normal power failure processing has been executed, and the check data is normal, the RAM is not cleared. Thereby, a game can be continued from the game state before a power failure.

In the pachinko machine according to the present embodiment, a power failure detection circuit 125 is provided on the main control board 120. Therefore, it is not necessary to provide signal wiring for outputting a power failure notice detection signal between the power supply board 110 and the main control board 120. As a result, the signal wiring of the power failure warning detection signal can be disconnected or short-circuited, and the intentional clearing and initialization of the main memory circuit 123b can be prevented. The voltage converter 124 on the main control board converts the 12V power supplied from the power board 110 into a 5V control power. Thereby, it is not necessary to provide the power supply wiring of the 5V control power supply between the power supply board 110 and the main control board 120. Therefore, it is possible to prevent an unauthorized act of intentionally initializing the RAM 123b of the main control circuit unit 123 by short-circuiting the power supply wiring of the 5V control power supply.
Further, the CPU 123a could not execute the power failure process by improperly shorting the power supply wiring pattern of the control power supply of the main control board and returning it or improperly shorting the signal wiring pattern of the power failure notice detection signal. In this case, since the power failure processing information indicating that the determination information has been written in the RAM 123b is not written in the RAM 123b, the game information used when determining whether or not to give a privilege to the player at the time of power recovery. It is not cleared. As a result, it is possible to further prevent a fraud in which the game information used when deciding whether or not to give a privilege to the player is cleared, that is, a deliberate intentional initialization of the RAM 123b of the main control circuit unit 123. be able to.
When the RAM 123b is initialized, the timing at which the lottery result is won can be predicted, and there is a risk that the pachinko machine 1 is deliberately put into a big hit gaming state. If the pachinko machine 1 according to the present embodiment is used, it is possible to prevent fraud in which the pachinko machine 1 is in a special gaming state advantageous to the player.

The present invention is not limited to the configuration described in the embodiment, and various changes, additions, and deletions are possible.
In the present embodiment, for convenience of explanation, the CPU and RAM provided in the main control circuit unit 123 are described as being configured separately, but actually the CPU and RAM are integrated as a control IC. It is configured.
In the present embodiment, the case where the present invention is applied to the pachinko machine 1 has been described. However, the present invention can also be applied to other gaming machines such as slots.

The present invention can also be configured as follows.
For example, “(Aspect 1) The gaming machine according to claim 1,
The main control circuit includes:
When a power failure notification signal is output from the power failure detection circuit, the determination information is written to the main memory circuit, and power failure processing information indicating that the determination information is written to the main memory circuit is written to the main memory circuit. writing,
Further, when the control power supply is restored, it is determined whether or not the power failure processing information written in the main memory circuit indicates that determination information has been written in the main memory circuit, and the power failure processing information is If it is determined that the determination information indicates that the main memory circuit has not been written, it is determined whether or not to give a privilege to the player from among the game information written in the main memory circuit. The game information other than the game information used at the time of determination is cleared, the power failure processing information indicates that the determination information is written in the main memory circuit, and the determination information written in the main memory circuit And determining whether or not the game information written in the main memory circuit is normal, and determining that the game information written in the main memory circuit is abnormal, the main memory To clear the game information written on the road,
A gaming machine characterized by that. Can be configured.
As the “game information used when deciding whether or not to give a privilege to a player”, a jackpot determination random number that is read because the game medium has won a start winning opening is typically used. It is done.
Various information can be used as the “power failure processing information”. For example, the first value can be used when the determination information is not written to the main memory circuit, and the second value can be used when the determination information is written to the main memory circuit. In this case, the power failure processing information indicates that the determination information has been written to the main memory circuit by determining whether the power failure processing information is the first value or the second value when the power is restored. It is determined whether or not. Alternatively, reset information can be used when the determination information is not written in the main memory circuit, and flag information that is set when the determination information is written in the main memory circuit can be used. In this case, it is determined whether or not the power failure processing information indicates that the determination information has been written to the main memory circuit by determining whether the power failure processing information is set or reset when the power is restored. To do.
In the process of “clearing game information other than game information used when determining whether or not to give a privilege to a player among the game information written in the memory circuit”, a privilege is given to the player The game information used when determining whether or not the game information may be used as it is or may be set to an arbitrary value other than the value set when the RAM is cleared.
If the gaming machine of this aspect is used, the main control circuit can be turned off by improperly shorting the power supply wiring pattern of the control power supply of the main control board and returning it, or improperly shorting the signal wiring pattern of the power failure warning detection signal. If the process cannot be executed, the power failure processing information indicating that the determination information has been written to the main memory circuit is not written to the main memory circuit, so that a privilege is given to the player when the power is restored. The game information used in determining whether or not is not cleared.
Thereby, it can prevent that the game information used when determining whether a privilege is given to a player is cleared illegally.

Further, “(Aspect 2) is a gaming machine according to Aspect 1,
Start prize opening where game media can win,
A start winning detection circuit that detects that a game medium has won the start winning opening and outputs a start winning detection signal;
The game information written in the main memory circuit includes a jackpot determination random number,
When the start winning detection signal is output from the start winning detection circuit, the main control circuit determines whether or not to give a bonus to the player based on a jackpot determination random number written in the main memory circuit And
Further, when the main control circuit determines that the power failure processing information indicates that the determination information has not been written to the main memory circuit, the main control circuit is used for jackpot determination written in the main memory circuit. Clear game information other than random numbers,
A gaming machine characterized by that. "
In the gaming machine of aspect 2, the main memory circuit is read when a start winning detection signal is output, and game information including a jackpot determination random number used when determining whether or not to give a privilege to the player. Has been written. The main control circuit, when the power failure processing information indicates that the determination information has not been written to the main memory circuit (that the power failure processing has been executed normally at the previous power failure) The game information other than the jackpot determination random number written in the circuit is cleared.
If the gaming machine of aspect 2 is used, a fraud in which the power supply wiring pattern of the control power supply is intentionally short-circuited and restored or a fraud in which the signal wiring pattern of the power failure warning detection signal input to the main control circuit is intentionally short-circuited is performed. If there is a possibility that the big hit determination random number is not cleared, the fraud prevention effect is high.

In addition, “(Aspect 3) is a gaming machine according to any one of claims 1, 1 and 2,
It has a memory clear switch,
The main control circuit clears the game information stored in the main memory circuit when the control power supply is restored while the memory clear switch is operated.
A gaming machine characterized by that. Can be configured.
The timing at which the game information stored in the main memory circuit is cleared by the operation of the memory clear switch is generally set to the operating voltage of the main control circuit while the memory clear switch is being operated. The rising timing is used.
According to the gaming machine of this aspect, the fraud prevention effect can be enhanced while allowing the clear operation of the main memory circuit by the staff of the game hall and the like.

In addition, “(Aspect 4) A gaming machine according to Aspect 3,
The memory clear switch is provided on the main control board,
A gaming machine characterized by that. Can be configured.
According to the gaming machine of aspect 4, there is no need to provide a signal wiring for outputting a memory clear signal between the power supply board and the main control board. As a result, in the state where an invalid memory clear signal is input to the signal wiring that outputs the memory clear signal, the power supply wiring supplied from the power supply board to the main control board is short-circuited, and the main memory circuit is intentionally cleared and initialized. Fraud can be prevented.

It is the figure which looked at the pachinko machine 1 from the back side in the state where the pachinko machine 1 is arranged in the game hall. 2 is a block diagram showing the configuration of a power supply board 110 and a main control board 120. FIG. It is a block diagram when a RAM clear switch is provided on the main control board 120. It is a flowchart figure which shows the process which CPU123a performs in 2nd Embodiment. It is a flowchart figure which shows the process which CPU123a performs in 2nd Embodiment. It is a flowchart figure which shows the process which CPU123a performs in 2nd Embodiment. FIG. 10 is a block diagram showing a configuration of a conventional power supply board 110 and a main control board 120. The timing chart figure which shows the state of 5V control power supply in the case of a power failure is shown. It is a figure explaining the state when the power supply wiring of a 5V control power supply is short-circuited with the conventional game machine. It is a figure explaining an initial value update type random number counter.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pachinko machine 110 Power supply board 111 Power supply circuit 113 RAM clear switch 120 Main control board 123 Main control circuit part 123a CPU
123b RAM
124 Voltage converter 125 Power failure detection circuit L1, L2 Power supply wiring L3 Signal wiring Vs Threshold

Claims (1)

A power supply board provided with a power supply circuit for supplying power to the main control board;
A power failure detection circuit that outputs a power failure warning detection signal based on a comparison result between a voltage value of a power source supplied from the power circuit and a set value;
A main control board provided with a main control circuit for controlling the operation of the entire gaming machine to which control power is supplied and a main memory circuit for storing game information that changes during the game,
When the power failure warning detection signal is output from the power failure detection circuit, the main control circuit generates a determination information using game information stored in the main memory circuit and writes the determination information to the main memory circuit. When the control power supply is restored, it is determined whether or not the game information stored in the main memory circuit is normal based on the determination information written in the main memory circuit, and based on the determination result A power failure recovery process for determining a processing method of game information stored in the main memory circuit,
A voltage conversion circuit that converts a voltage value of a power source supplied from the power supply circuit into a voltage value of the control power source, and the voltage conversion circuit and the power failure detection circuit are provided on the main control board;
A gaming machine characterized by that.

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