JP4797950B2 - Semiconductor device and electronic device using the same - Google Patents

Semiconductor device and electronic device using the same Download PDF

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JP4797950B2
JP4797950B2 JP2006318244A JP2006318244A JP4797950B2 JP 4797950 B2 JP4797950 B2 JP 4797950B2 JP 2006318244 A JP2006318244 A JP 2006318244A JP 2006318244 A JP2006318244 A JP 2006318244A JP 4797950 B2 JP4797950 B2 JP 4797950B2
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semiconductor device
conductor
semiconductor
relay substrate
terminal
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JP2008135428A (en
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潤一 木村
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

本発明は、半導体素子が搭載された半導体装置と、これを用いた電子機器に関するものである。   The present invention relates to a semiconductor device on which a semiconductor element is mounted and an electronic apparatus using the same.

以下、従来の半導体装置１について図面を用いて説明する。図４は従来の半導体装置１が搭載された従来の携帯機器２の断面図であり、図５は、従来の半導体装置１の裏面図である。   Hereinafter, a conventional semiconductor device 1 will be described with reference to the drawings. FIG. 4 is a cross-sectional view of a conventional portable device 2 on which the conventional semiconductor device 1 is mounted, and FIG. 5 is a back view of the conventional semiconductor device 1.

まずは半導体装置１について説明する。図４、図５において、中継基板３は厚みが０．３ｍｍの基板であり、その上面には半導体素子４が接続固定されている。この半導体素子４の下面側には、半導体素子４の外周に沿って、非常に狭い間隔でバンプ５（半導体端子の一例として用いた）が形成されている。そして中継基板３の上面には、バンプ５に対応する位置に導体パッド６が設けられる。ここで、バンプ５と導体パッド６とは圧接により電気的に接続されている。そして中継基板３と半導体素子４は樹脂７によって固定され、バンプ５と導体パッド６との間の接続が維持される。なお中継基板３の下面には、接続端子８が形成される。   First, the semiconductor device 1 will be described. 4 and 5, the relay substrate 3 is a substrate having a thickness of 0.3 mm, and the semiconductor element 4 is connected and fixed to the upper surface thereof. On the lower surface side of the semiconductor element 4, bumps 5 (used as an example of a semiconductor terminal) are formed along the outer periphery of the semiconductor element 4 at a very narrow interval. On the upper surface of the relay substrate 3, conductor pads 6 are provided at positions corresponding to the bumps 5. Here, the bump 5 and the conductor pad 6 are electrically connected by pressure contact. The relay substrate 3 and the semiconductor element 4 are fixed by the resin 7, and the connection between the bump 5 and the conductor pad 6 is maintained. A connection terminal 8 is formed on the lower surface of the relay substrate 3.

図６は、半導体素子４を中継基板３へ接続する工程における半導体装置１の断面図である。図６に示すように、半導体素子４が中継基板３に搭載された状態でプレート１３間に挟まれて加圧保持され、この加圧状態のままで樹脂７が半導体素子４と中継基板３との間に注入、固定されることにより完成する。   FIG. 6 is a cross-sectional view of the semiconductor device 1 in the process of connecting the semiconductor element 4 to the relay substrate 3. As shown in FIG. 6, the semiconductor element 4 is sandwiched between the plates 13 while being mounted on the relay substrate 3, and is held under pressure. Completed by injecting and fixing between.

次に携帯機器２について、図４を用いて説明する。半導体装置１が搭載されるマザー基板９の上面には、接続端子８と対応する位置に接続ランド１０が形成されている。そしてマザー基板９に半導体装置１が搭載され、接続端子８と接続ランド１０とがはんだ１１によって接続されて携帯機器２（電子機器の一例として用いた）が完成する。   Next, the portable device 2 will be described with reference to FIG. A connection land 10 is formed at a position corresponding to the connection terminal 8 on the upper surface of the mother substrate 9 on which the semiconductor device 1 is mounted. Then, the semiconductor device 1 is mounted on the mother substrate 9 and the connection terminals 8 and the connection lands 10 are connected by the solder 11 to complete the portable device 2 (used as an example of an electronic device).

なお、この出願の発明に関連する先行技術文献情報としては、例えば、特許文献１が知られている。
特開２００５−６４４６７号公報 As prior art document information related to the invention of this application, for example, Patent Document 1 is known.
JP 2005-64467 A

しかしながら、樹脂７を注入する工程において、接続端子８が形成されていない場所では、プレート１３と中継基板３との間に隙間１２が生じる。そして図６に示すように、導体パッド６の裏面側に隙間１２が形成されていると、厚みが薄い中継基板３が隙間１２方向へ反ることとなる。これにより、バンプ５と導体パッド６との間での接触圧が不安定となり、最悪接触しない場合も発生するという課題を有している。   However, in the step of injecting the resin 7, a gap 12 is generated between the plate 13 and the relay substrate 3 in a place where the connection terminal 8 is not formed. As shown in FIG. 6, if the gap 12 is formed on the back side of the conductor pad 6, the relay substrate 3 having a small thickness warps in the direction of the gap 12. As a result, the contact pressure between the bump 5 and the conductor pad 6 becomes unstable, and there is a problem that it may occur even when the worst contact does not occur.

そこで本発明は、この問題を解決したもので、半導体素子４と中継基板３とを安定して接続することができる半導体装置を得るものである。   Accordingly, the present invention solves this problem and provides a semiconductor device that can stably connect the semiconductor element 4 and the relay substrate 3.

この目的を達成するために本発明の半導体装置は、中継基板の一方の面に半導体素子がフリップチップ実装された半導体装置において、前記中継基板の一方の面には導体パッドを設けるとともに、前記中継基板の他方の面には前記導体パッドのそれぞれに接続された接続端子を設け、前記半導体素子には前記導体パッドのそれぞれに対応するように設けられた半導体端子を備え、前記中継基板の他方の面において前記導体パッドと対応する位置に、補強導体が設けられこの補強導体には半田接続の為に絶縁膜を設けないものである。これにより所期の目的を達成できる。 In order to achieve this object, a semiconductor device according to the present invention is a semiconductor device in which a semiconductor element is flip-chip mounted on one surface of a relay substrate, and a conductor pad is provided on one surface of the relay substrate, and the relay device A connection terminal connected to each of the conductor pads is provided on the other surface of the substrate, and the semiconductor element includes a semiconductor terminal provided so as to correspond to each of the conductor pads, and the other surface of the relay substrate is provided. A reinforcing conductor is provided at a position corresponding to the conductor pad on the surface, and an insulating film is not provided on the reinforcing conductor for solder connection . This achieves the intended purpose.

以上のように本発明によれば、中継基板の一方の面に半導体素子がフリップチップ実装された半導体装置において、前記中継基板の一方の面には導体パッドを設けるとともに、前記中継基板の他方の面には前記導体パッドのそれぞれに接続された接続端子を設け、前記半導体素子には前記導体パッドのそれぞれに対応するように設けられた半導体端子を備え、前記中継基板の他方の面において、前記導体パッドと対応する位置には、補強導体が設けられこの補強導体には半田接続の為に絶縁膜を設けない半導体装置である。 As described above, according to the present invention, in the semiconductor device in which the semiconductor element is flip-chip mounted on one surface of the relay substrate, the conductor pad is provided on one surface of the relay substrate and the other surface of the relay substrate is provided. The surface is provided with a connection terminal connected to each of the conductor pads, the semiconductor element is provided with a semiconductor terminal provided to correspond to each of the conductor pads, and on the other surface of the relay substrate, In the semiconductor device, a reinforcing conductor is provided at a position corresponding to the conductor pad, and an insulating film is not provided on the reinforcing conductor for solder connection .

これにより、導体パッドの裏側に補強導体が設けられるので、加圧工程において半導体端子に対応する位置で中継基板とプレートとの間に隙間が生じない。従って、中継基板に反りが生じ難くなり、半導体端子と導体パッドとが確りと圧接されるので、半導体素子と中継基板とが安定して接続できるという効果がある。   Thereby, since the reinforcing conductor is provided on the back side of the conductor pad, no gap is generated between the relay substrate and the plate at the position corresponding to the semiconductor terminal in the pressurizing step. Therefore, it is difficult for the relay substrate to be warped, and the semiconductor terminal and the conductor pad are securely pressed against each other, so that there is an effect that the semiconductor element and the relay substrate can be stably connected.

（実施の形態１）
以下、本実施の形態の携帯機器２１について、図面を用いて説明する。図１は本実施の形態における携帯機器２１の要部断面図であり、図２は同、半導体装置２０の下面図である。なお図１、図２において図４、図５と同じものには同じ番号を用いて、その説明は簡略化している。 (Embodiment 1)
Hereinafter, the portable device 21 of the present embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a main part of a portable device 21 in the present embodiment, and FIG. 2 is a bottom view of the semiconductor device 20. In FIGS. 1 and 2, the same components as those in FIGS. 4 and 5 are denoted by the same reference numerals, and the description thereof is simplified.

図１、図２において、半導体素子４の下面側には、半導体素子４の外周に沿って多くの金属製のバンプ５（半導体端子の一例として用いた）がロの字形状に配置されている。なおこれらバンプ５の間隔は非常に狭い間隔であり、本実施の形態では約０．１ｍｍの間隔で配置されている。   1 and 2, many metal bumps 5 (used as an example of a semiconductor terminal) are arranged in a square shape along the outer periphery of the semiconductor element 4 on the lower surface side of the semiconductor element 4. . The intervals between the bumps 5 are very narrow. In the present embodiment, the intervals are about 0.1 mm.

このような狭いピッチのバンプ５の半導体素子４をはんだ付けなどによって直接マザー基板２３へはんだ付け接続することは、非常に困難である。そこで、半導体素子４は中継基板２２を介してマザー基板２３に接続される。なお、本実施の形態の中継基板２２は厚みが０．２ｍｍの多層基板を用いている。   It is very difficult to solder and connect the semiconductor elements 4 of the bumps 5 having such a narrow pitch directly to the mother board 23 by soldering or the like. Therefore, the semiconductor element 4 is connected to the mother substrate 23 via the relay substrate 22. Note that the relay substrate 22 of the present embodiment uses a multilayer substrate having a thickness of 0.2 mm.

そのために、中継基板２２の上面には、バンプ５に対応する位置に導体パッド２４が設けられる。そしてこの中継基板２２の下面には、導体パッド２４とスルーホールを介して接続された接続端子２５が形成されている。この接続端子２５は、マザー基板２３へはんだ１１によって接続が可能な広いピッチで配置されている。本実施の形態では接続端子２５間のピッチは、０．４ｍｍとし、接続端子２５の形状は一辺が０．２ｍｍの正方形としている。   For this purpose, conductor pads 24 are provided on the upper surface of the relay substrate 22 at positions corresponding to the bumps 5. A connection terminal 25 connected to the conductor pad 24 through a through hole is formed on the lower surface of the relay substrate 22. The connection terminals 25 are arranged at a wide pitch that can be connected to the mother board 23 by the solder 11. In this embodiment, the pitch between the connection terminals 25 is 0.4 mm, and the shape of the connection terminals 25 is a square having a side of 0.2 mm.

ここで半導体素子４は、フェイスダウンにて中継基板２２にフリップチップ実装される。本実施の形態において半導体素子４の実装は、いわゆるＮＣＰ（非導電性ペースト）による実装を用いている。具体的には、バンプ５と導体パッド２４とは圧接されることによって、電気的に導通するものである。そして、中継基板２２と半導体素子４は非導電性の樹脂７によって固定されることで、バンプ５と導体パッド２４との間の接続が維持される。なお本実施の形態においては、ＮＣＰ実装を用いたが、これはＡＣＰ（異方性導電ペースト）やＡＣＦ（異方性導電フィルム）を用いた実装としても良い。   Here, the semiconductor element 4 is flip-chip mounted on the relay substrate 22 face down. In the present embodiment, the semiconductor element 4 is mounted by using a so-called NCP (non-conductive paste). Specifically, the bump 5 and the conductor pad 24 are brought into electrical conduction by being pressed against each other. The relay substrate 22 and the semiconductor element 4 are fixed by the non-conductive resin 7 so that the connection between the bump 5 and the conductor pad 24 is maintained. In this embodiment, NCP mounting is used, but this may be mounting using ACP (anisotropic conductive paste) or ACF (anisotropic conductive film).

中継基板２２の下面において、導体パッド２４と対応する位置には、補強導体２６が形成されている。なお中継基板２２の裏面側には絶縁膜は形成せず、接続端子２５や補強導体２６には金メッキが施されている。本実施の形態において補強導体２６同士は、補強導体２６と等しい幅で連結されている。これによって、補強導体２６はロの字型となるので、中継基板２２自体の強度を大きくできる。   A reinforcing conductor 26 is formed on the lower surface of the relay substrate 22 at a position corresponding to the conductor pad 24. Note that no insulating film is formed on the back side of the relay substrate 22, and the connection terminals 25 and the reinforcing conductors 26 are plated with gold. In the present embodiment, the reinforcing conductors 26 are connected with the same width as the reinforcing conductor 26. As a result, the reinforcing conductor 26 has a square shape, so that the strength of the relay substrate 22 itself can be increased.

さらにロの字型に補強導体２６を形成することによって、接続端子２５は補強導体２６に囲まれた領域と、補強導体２６の外側とにそれぞれ配置されることとなる。そして、この補強導体２６を半導体装置２０のグランド端子として用いることで、例えば補強導体２６に囲まれた接続端子２５ａと、補強導体２６の外側の接続端子２５ｂ、２５ｃとはグランドを跨いで配置される。また接続端子２５ｂと接続端子２５ｃは少なくとも２本の補強導体２６を跨いで配置される。従って、接続端子２５ａと接続端子２５ｂあるいは接続端子２５ｃとの間や、接続端子２５ｂと接続端子２５ｃとの間で信号同士が干渉し難くなる。   Further, by forming the reinforcing conductors 26 in a square shape, the connection terminals 25 are respectively disposed in a region surrounded by the reinforcing conductors 26 and outside the reinforcing conductors 26. By using this reinforcing conductor 26 as the ground terminal of the semiconductor device 20, for example, the connection terminal 25a surrounded by the reinforcing conductor 26 and the connection terminals 25b and 25c outside the reinforcing conductor 26 are arranged across the ground. The Further, the connection terminal 25 b and the connection terminal 25 c are disposed across at least two reinforcing conductors 26. Therefore, it is difficult for signals to interfere with each other between the connection terminal 25a and the connection terminal 25b or the connection terminal 25c, or between the connection terminal 25b and the connection terminal 25c.

なお本実施の形態ではすべての補強導体２６を連結することで、ロの字型としたが、これは分離すべき接続端子２５の配置によって、例えばＬ型やＨ型あるいはＩ字型に連結しても良い。   In this embodiment, all the reinforcing conductors 26 are connected to form a square shape, but this is connected to, for example, an L shape, an H shape, or an I shape depending on the arrangement of the connection terminals 25 to be separated. May be.

次に携帯機器２１について説明する。半導体装置２０が搭載されるマザー基板２３の上面には、接続端子２５と対応する位置に接続ランド１０が形成されている。さらに、補強導体２６に対応する位置に接続ランド２７が形成されている。ここで、接続ランド２７は、マザー基板２３のグランドと接続されている。そしてマザー基板２３の上面に半導体装置２０が搭載され、接続端子２５と接続ランド１０ならびに、補強導体２６と接続ランド２７とがそれぞれはんだ１１によって接続されて携帯機器２１（電子機器の一例として用いた）が完成する。   Next, the portable device 21 will be described. A connection land 10 is formed at a position corresponding to the connection terminal 25 on the upper surface of the mother substrate 23 on which the semiconductor device 20 is mounted. Further, a connection land 27 is formed at a position corresponding to the reinforcing conductor 26. Here, the connection land 27 is connected to the ground of the mother board 23. Then, the semiconductor device 20 is mounted on the upper surface of the mother substrate 23, and the connection terminals 25 and the connection lands 10 and the reinforcing conductors 26 and the connection lands 27 are connected by the solder 11, respectively. ) Is completed.

これによって、接続端子２５ａはグランドに囲まれることとなるので、確りとシールドできる。また、接続端子２５ａと接続端子２５ｂとの間や、接続端子２５ａと接続端子２５ｃとの間にもグランドが介在することとなるので、これらの接続端子２５同士でアイソレーションを取れる（高周波的に分離できる）。従ってそれらの接続端子２５同士で信号が干渉を起こし難くできる。   As a result, the connection terminal 25a is surrounded by the ground, so that it can be reliably shielded. Further, since the ground is also interposed between the connection terminal 25a and the connection terminal 25b or between the connection terminal 25a and the connection terminal 25c, the connection terminals 25 can be isolated from each other (in terms of high frequency). Can be separated). Therefore, it is possible to make it difficult for signals to interfere with each other between the connection terminals 25.

さらに、補強導体２６は接続ランド２７とはんだ１１で接続されるので、半導体素子４はマザー基板２３へ確りと固定される。従って、落下などによる衝撃力や曲げに対し、半導体装置２０がマザー基板２３から外れたりし難くなる。また、落下や曲げなどの力に対し、中継基板２２の変形も小さくできるので、半導体素子４と中継基板２２間の接続信頼性を高くできる。   Further, since the reinforcing conductor 26 is connected to the connection land 27 by the solder 11, the semiconductor element 4 is securely fixed to the mother substrate 23. Accordingly, it is difficult for the semiconductor device 20 to be detached from the mother substrate 23 due to impact force or bending due to dropping or the like. Moreover, since the deformation of the relay substrate 22 can be reduced with respect to a force such as dropping or bending, the connection reliability between the semiconductor element 4 and the relay substrate 22 can be increased.

次に、本実施の形態における半導体装置２０の製造方法を説明する。半導体素子４は中継基板２２の所定の位置に搭載される。この状態にて、図６と同様にプレート１３間に挟まれて図示矢印方向に加圧保持される。この加圧によりバンプ５と導体パッド２４とが圧接される。そしてこの加圧状態で半導体素子４と中継基板２２との間の隙間１２へ樹脂７が注入され、加熱によって樹脂７を硬化する。このようにすることにより、半導体素子４が中継基板２２上に固定され、半導体装置２０が完成する。つまりバンプ５が導体パッド２４へ圧接された状態のままで、半導体素子４が中継基板２２へ固定されるので、半導体素子４と中継基板２２との間の電気的接続が維持できる。   Next, a method for manufacturing the semiconductor device 20 in the present embodiment will be described. The semiconductor element 4 is mounted at a predetermined position on the relay substrate 22. In this state, it is sandwiched between the plates 13 as in FIG. By this pressurization, the bump 5 and the conductor pad 24 are brought into pressure contact. In this pressurized state, the resin 7 is injected into the gap 12 between the semiconductor element 4 and the relay substrate 22, and the resin 7 is cured by heating. In this way, the semiconductor element 4 is fixed on the relay substrate 22 and the semiconductor device 20 is completed. That is, since the semiconductor element 4 is fixed to the relay substrate 22 while the bumps 5 are pressed against the conductor pads 24, the electrical connection between the semiconductor element 4 and the relay substrate 22 can be maintained.

以上の構成によって、中継基板２２の導体パッド２４と対応する位置に補強導体２６を設けているので、加圧工程においてバンプ５に対応する位置で中継基板２２とプレート１３（図６に示す）との間に隙間が生じない。従って、中継基板２２の厚みが薄くても、中継基板２２に反りが生じ難くなる。これにより、導体パッド２４に対しバンプ５が確りと圧接されるので、半導体素子４と中継基板２２とを安定して接続することができる。さらに、中継基板２２の厚みを薄くできるので、高さの低い半導体装置２０を実現できる。   With the above configuration, since the reinforcing conductor 26 is provided at a position corresponding to the conductor pad 24 of the relay substrate 22, the relay substrate 22 and the plate 13 (shown in FIG. 6) are positioned at a position corresponding to the bump 5 in the pressing process. There is no gap between them. Therefore, even if the thickness of the relay board 22 is thin, the relay board 22 is hardly warped. As a result, the bumps 5 are securely pressed against the conductor pads 24, so that the semiconductor element 4 and the relay substrate 22 can be stably connected. Furthermore, since the thickness of the relay substrate 22 can be reduced, the semiconductor device 20 having a low height can be realized.

なお、本実施の形態では中継基板２２の下面側は絶縁膜を形成していない。これは、絶縁膜により中継基板２２の裏面に凹凸を生じないようにするためである。これにより、プレート１３は補強導体２６に密着するので、加圧中に中継基板２２に反りが生じ難い。   In the present embodiment, an insulating film is not formed on the lower surface side of the relay substrate 22. This is to prevent the back surface of the relay substrate 22 from being uneven due to the insulating film. Thereby, since the plate 13 is in close contact with the reinforcing conductor 26, the relay substrate 22 is hardly warped during pressurization.

ここで、携帯機器２１はテレビ放送用のチューナ３１を内蔵した携帯電話であり、本実施の形態では、このチューナ３１を構成する高周波回路の一部が半導体素子４上に形成されている。図３は、本実施の形態におけるチューナの回路ブロック図である。なお図３において、図１や図２と同じものは同じ番号を用いて、その説明は簡略化している。   Here, the mobile device 21 is a mobile phone incorporating a tuner 31 for television broadcasting. In the present embodiment, a part of the high-frequency circuit constituting the tuner 31 is formed on the semiconductor element 4. FIG. 3 is a circuit block diagram of the tuner according to the present embodiment. In FIG. 3, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and the description thereof is simplified.

図３において、アンテナ３２には、約５０〜９００ＭＨｚの高周波信号が入力される。このアンテナ３２に入力された高周波信号は、チューナ３１の入力端子３１ａを介してバンドパスフィルタ３３へ供給される。バンドパスフィルタ３３の出力は、半導体装置２０の入力端子である接続端子２５ｂへ接続される。増幅器３４は半導体素子４上で形成される。従ってバンドパスフィルタ３３の出力は、中継基板２２を介して増幅器３４へ供給されることとなる。   In FIG. 3, a high frequency signal of about 50 to 900 MHz is input to the antenna 32. The high frequency signal input to the antenna 32 is supplied to the band pass filter 33 via the input terminal 31 a of the tuner 31. The output of the band pass filter 33 is connected to a connection terminal 25 b that is an input terminal of the semiconductor device 20. The amplifier 34 is formed on the semiconductor element 4. Therefore, the output of the band pass filter 33 is supplied to the amplifier 34 via the relay substrate 22.

混合器３５の一方の入力には増幅器３４の出力が供給され、他方の入力には局部発振器３６の出力が供給される。そして混合器３５の出力は、半導体装置２０の出力端子である接続端子２５ｃを介して、マザー基板上に構成されたバンドパスフィルタ３７へ供給され、このバンドパスフィルタ３７で不要な成分の信号が除去されてチューナ３１の出力端子３１ｂより出力される。   The output of the amplifier 34 is supplied to one input of the mixer 35 and the output of the local oscillator 36 is supplied to the other input. The output of the mixer 35 is supplied to a band-pass filter 37 formed on the mother substrate via a connection terminal 25 c that is an output terminal of the semiconductor device 20, and an unnecessary component signal is output from the band-pass filter 37. It is removed and output from the output terminal 31 b of the tuner 31.

ここで、局部発振器３６にはＰＬＬ回路３８がループ接続されており、このＰＬＬ回路３８は半導体装置２０の接続端子２５ａと接続される。ＰＬＬ回路３８は、この接続端子２５ａを介して、マザー基板２３上に設けられたＣＰＵからチャンネルデータを入力する。   Here, a PLL circuit 38 is loop-connected to the local oscillator 36, and the PLL circuit 38 is connected to the connection terminal 25 a of the semiconductor device 20. The PLL circuit 38 inputs channel data from a CPU provided on the mother board 23 via the connection terminal 25a.

なお、本実施の形態では、増幅器３４、混合器３５、局部発振器３６とＰＬＬ回路３８とを含む高周波回路が半導体素子４上に形成されている。そしてこのように構成された半導体素子４でテレビ放送を良好に受信しようとする場合、増幅器３４への入力信号と混合器３５の出力信号や、ＰＬＬ回路３８へ入力されるチャンネルデータ信号と増幅器３４への入力信号あるいは混合器３５の出力信号とは十分にアイソレーションが取れていることが必要である。ここで一般に半導体素子４単体では、これらのアイソレーションが取れるように設計される。そこでこのような半導体素子４を中継基板２２へ実装した場合には、その中継基板２２においても各信号のアイソレーションを確保できるようにしておくことが重要となる。   In the present embodiment, a high frequency circuit including an amplifier 34, a mixer 35, a local oscillator 36 and a PLL circuit 38 is formed on the semiconductor element 4. When the semiconductor device 4 configured as described above is to receive a television broadcast satisfactorily, the input signal to the amplifier 34 and the output signal of the mixer 35, the channel data signal input to the PLL circuit 38, and the amplifier 34 are used. It is necessary that the input signal to the output signal or the output signal of the mixer 35 be sufficiently isolated. Here, in general, the semiconductor element 4 alone is designed so that these isolations can be obtained. Therefore, when such a semiconductor element 4 is mounted on the relay substrate 22, it is important to ensure isolation of each signal also on the relay substrate 22.

そこで、本実施の形態では、半導体装置２０の補強導体２６をグランド端子とし、マザー基板２３のグランドと接続された接続ランド２７とを接続する。これにより、接続端子２５ａと接続端子２５ｂとの間、接続端子２５ａと接続端子２５ｃ、さらに接続端子２５ｂと接続端子２５ｃの間はそれぞれにアイソレーションを確保することができる。   Therefore, in the present embodiment, the reinforcing conductor 26 of the semiconductor device 20 is used as a ground terminal, and the connection land 27 connected to the ground of the mother substrate 23 is connected. Accordingly, it is possible to ensure isolation between the connection terminal 25a and the connection terminal 25b, between the connection terminal 25a and the connection terminal 25c, and between the connection terminal 25b and the connection terminal 25c.

従って、ＰＬＬ回路３８に対しＣＰＵからのバスラインを経由して進入するＣＰＵのクロック信号などによる妨害の影響を受け難くできる。また増幅器３４へ入力される信号に対し、混合器３５の出力信号が飛び込み難くなる。   Therefore, the PLL circuit 38 can be hardly affected by the interference caused by the CPU clock signal entering via the bus line from the CPU. Further, the output signal of the mixer 35 is less likely to jump into the signal input to the amplifier 34.

本発明にかかる半導体装置は、薄い厚みの中継基板を用いることができるという効果を有し、特に薄型化が要求されるような機器等に用いると有用である。   The semiconductor device according to the present invention has an effect that a relay substrate having a small thickness can be used, and is particularly useful when used in a device or the like that is required to be thin.

本発明の一実施の形態における携帯機器の要部断面図Sectional drawing of the principal part of the portable apparatus in one embodiment of this invention 本発明の一実施の形態における半導体装置の下面図The bottom view of the semiconductor device in one embodiment of the present invention 本実施の形態におけるチューナの回路ブロック図Circuit block diagram of tuner in the present embodiment 従来の携帯機器の要部断面図Sectional view of the main parts of a conventional portable device 従来の半導体装置の下面図Bottom view of conventional semiconductor device 従来の半導体装置において樹脂を注入する工程における半導体装置の要部断面図Sectional view of the main part of the semiconductor device in the process of injecting resin in the conventional semiconductor device

符号の説明Explanation of symbols

４ 半導体素子
５ バンプ
２０ 半導体装置
２２ 中継基板
２４ 導体パッド
２５ 接続端子
２６ 補強導体 4 Semiconductor Element 5 Bump 20 Semiconductor Device 22 Relay Board 24 Conductor Pad 25 Connection Terminal 26 Reinforcing Conductor

Claims (5)

中継基板の一方の面に半導体素子がフリップチップ実装された半導体装置において、前記中継基板の一方の面には導体パッドを設けるとともに、前記中継基板の他方の面には前記導体パッドのそれぞれに接続された接続端子を設け、前記半導体素子には前記導体パッドのそれぞれに対応するように設けられた半導体端子を備え、前記中継基板の他方の面において前記導体パッドと対応する位置には、補強導体が設けられこの補強導体には半田接続の為に絶縁膜を設けない半導体装置。 In a semiconductor device in which a semiconductor element is flip-chip mounted on one surface of a relay substrate, a conductor pad is provided on one surface of the relay substrate and connected to each of the conductor pads on the other surface of the relay substrate The semiconductor element is provided with a semiconductor terminal provided so as to correspond to each of the conductor pads, and a reinforcing conductor is provided at a position corresponding to the conductor pad on the other surface of the relay substrate. A semiconductor device in which the reinforcing conductor is not provided with an insulating film for solder connection . 中継基板の一方の面に半導体素子がフリップチップ実装された半導体装置において、前記中継基板の一方の面には導体パッドを設けるとともに、前記中継基板の他方の面には前記導体パッドのそれぞれに接続された接続端子を設け、前記半導体素子には前記導体パッドのそれぞれに対応するように設けられた半導体端子を備え、前記中継基板の他方の面において前記導体パッドと対応する位置には、補強導体が設けられた半導体装置において、前記半導体素子には高周波回路が形成され、前記半導体端子には前記高周波回路に接続されるとともに、互いに高周波的に分離すべき第１の半導体端子と第２の半導体端子とを設け、接続端子には前記第１と第２の半導体端子のそれぞれに接続された第１の接続端子と第２の接続端子とを設け、前記第１の接続端子と第２の接続端子との間に挟まれた補強導体は少なくともグランド端子とした半導体装置。 In a semiconductor device in which a semiconductor element is flip-chip mounted on one surface of a relay substrate, a conductor pad is provided on one surface of the relay substrate and connected to each of the conductor pads on the other surface of the relay substrate The semiconductor element is provided with a semiconductor terminal provided so as to correspond to each of the conductor pads, and a reinforcing conductor is provided at a position corresponding to the conductor pad on the other surface of the relay substrate. in the semiconductor device provided with, said semiconductor element high-frequency circuit is formed, said is connected to said high frequency circuit on the semiconductor terminal, a first semiconductor terminal and the second semiconductor to be RF isolated from one another And a connection terminal is provided with a first connection terminal and a second connection terminal connected to each of the first and second semiconductor terminals, First connection terminal and a semi-conductor device reinforcing conductors sandwiched that at least the ground terminals between the second connection terminal. マザー基板と、このマザー基板の一方の面に装着される半導体装置とを有した電子機器において、半導体装置には請求項１に記載の半導体装置を用い、前記マザー基板には前記半導体装置の接続端子側が前記マザー基板と対向するように装着され、前記マザー基板の一方の面には、前記接続端子と接続された第１の接続ランドと、補強導体と接続された第２の接続ランドとを設けた電子機器。 In an electronic apparatus having a mother substrate and a semiconductor device mounted on one surface of the mother substrate, the semiconductor device according to claim 1 is used as the semiconductor device, and the semiconductor device is connected to the mother substrate. A terminal side is mounted so as to face the mother board, and a first connection land connected to the connection terminal and a second connection land connected to a reinforcing conductor are provided on one surface of the mother board. Electronic equipment provided. マザー基板と、このマザー基板の一方の面に装着される半導体装置とを有した電子機器において、半導体装置には請求項２に記載の半導体装置を用い、前記マザー基板には前記半導体装置の第１および第２の接続端子側が前記マザー基板と対向するように装着され、前記マザー基板の一方の面には、前記第１と第２の接続端子のそれぞれに接続された第１と第２の接続ランドとを設けるとともに、グランド端子は前記マザー基板のグランドと接続された電子機器。 In an electronic apparatus having a mother substrate and a semiconductor device mounted on one surface of the mother substrate, the semiconductor device according to claim 2 is used as the semiconductor device, and the mother substrate includes a second of the semiconductor device. The first and second connection terminal sides are mounted so as to face the mother board, and the first and second connection terminals connected to the first and second connection terminals on one surface of the mother board, respectively. An electronic device having a connection land and a ground terminal connected to the ground of the mother board. マザー基板において補強導体と対応する位置には、グランドパターンが形成された請求項４に記載の電子機器。 The electronic device according to claim 4 , wherein a ground pattern is formed at a position corresponding to the reinforcing conductor on the mother board.
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