JP4430419B2 - Electronic circuit using parallel conductive circuit sheet and method for manufacturing the same - Google Patents

Electronic circuit using parallel conductive circuit sheet and method for manufacturing the same Download PDF

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JP4430419B2
JP4430419B2 JP2004021382A JP2004021382A JP4430419B2 JP 4430419 B2 JP4430419 B2 JP 4430419B2 JP 2004021382 A JP2004021382 A JP 2004021382A JP 2004021382 A JP2004021382 A JP 2004021382A JP 4430419 B2 JP4430419 B2 JP 4430419B2
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conductive
wiring
circuit
conductive circuit
sheet
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JP2005217146A (en
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裕史 稲谷
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Fujikura Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Non-Insulated Conductors (AREA)
  • Insulated Conductors (AREA)

Description

本発明は、あらゆる電子機器に使用される両面・多層プリント基板の配線同士、又はプリント基板の配線と電子部品の端子を接続する平行導電回路シートに関し、特に、高精度な配線実装能力が必要な微細配線の接続を容易に行うことができる平行導電回路シート及び平行導電回路シートを用いた電子回路に関する。   The present invention relates to a parallel conductive circuit sheet for connecting wirings of a double-sided / multi-layered printed circuit board used in any electronic device, or wiring of a printed circuit board and terminals of an electronic component, and particularly requires a highly accurate wiring mounting capability. The present invention relates to a parallel conductive circuit sheet capable of easily connecting fine wiring and an electronic circuit using the parallel conductive circuit sheet.

近年の電子機器の小型化・高機能化に伴い、プリント基板上に電子部品を高密度実装する技術の開発が進められている。なかでもIC部品の実装は、QFP、SOPに代表される表面実装型から、実装端子間に金線を用いるWire Bonnding、或いはプリント基板に直接半導体チップを実装するフリップチップ実装(FC実装)等の実装方法に変化してきている。   With recent miniaturization and higher functionality of electronic devices, development of technology for mounting electronic components on a printed circuit board at high density has been underway. In particular, IC components can be mounted from surface mount types such as QFP and SOP, to wire bonding using gold wires between mounting terminals, or to flip chip mounting (FC mounting) where a semiconductor chip is directly mounted on a printed circuit board. The implementation method has changed.

ここでFC実装とは、半導体チップ側にバンプを形成し、このバンプを介してプリント基板に半導体チップを直接実装する技術である。このプリント基板への実装方法には、はんだ接続、ACF接続、金・金接続等の3つの接続方法があるが、特にプリント基板同士の接続には異方性導電膜(ACF)が用いられる。ACFとは、熱硬化性樹脂に金属粉末の導電性フィラーを練り込ませた接着性フィルムである。   Here, FC mounting is a technique in which bumps are formed on the semiconductor chip side and the semiconductor chips are directly mounted on the printed circuit board via the bumps. There are three connection methods, such as solder connection, ACF connection, and gold / gold connection, for mounting on the printed circuit board. In particular, an anisotropic conductive film (ACF) is used for connection between printed circuit boards. ACF is an adhesive film in which a conductive filler of metal powder is kneaded into a thermosetting resin.

ここで図7を参照して、ACF接続方法を説明する。まず図7(a)に示すように、配線109が形成された基板107を用意し、この基板107及び配線109の上面にACF103を配置させる。次いで図7(b)に示すように、このACF103上に半導体チップ111を配置し、熱と共に荷重をかける。すると図7(c)に示すように、導電性フィラー105を押し潰す方向に導電性フィラー105が固まり、押し潰した方向での導通が得られる。尚、半導体チップ111の隣り合う端子113間は導電性フィラー105が押し潰されないので絶縁性が保たれる。この状態で熱硬化性樹脂が硬化し、接続強度が確保される。
「月間Semiconductor World」、1998年9月号、p157−158、「2.ACF接続」
Here, the ACF connection method will be described with reference to FIG. First, as shown in FIG. 7A, a substrate 107 on which a wiring 109 is formed is prepared, and an ACF 103 is disposed on the upper surface of the substrate 107 and the wiring 109. Next, as shown in FIG. 7B, a semiconductor chip 111 is placed on the ACF 103, and a load is applied together with heat. Then, as shown in FIG.7 (c), the conductive filler 105 hardens | solidifies in the direction which crushes the conductive filler 105, and conduction | electrical_connection in the crushed direction is obtained. In addition, since the conductive filler 105 is not crushed between the adjacent terminals 113 of the semiconductor chip 111, insulation is maintained. In this state, the thermosetting resin is cured and the connection strength is secured.
“Monthly Semiconductor World”, September 1998, p157-158, “2. ACF Connection”

ところで、上述したACFは接続対象物同士を低温接続することができ、且つ端子間の絶縁性が確実に得られ、更に導通の信頼性が高いという利点を有するが、その一方で導電性フィラー105のサイズが大きいために、隣り合う配線又はIC端子間がショートすることがあるという問題がある。   By the way, the above-mentioned ACF has the advantage that the objects to be connected can be connected to each other at low temperature, the insulation between the terminals can be surely obtained, and the reliability of conduction is high. Due to the large size, there is a problem that adjacent wirings or IC terminals may be short-circuited.

この導電性フィラー105のサイズには大小様々な大きさが存在するが、小さいサイズの導電性フィラー105は作製技術に高度なテクニックが必要であり、それゆえ価格も高価である。製品に使用できる価格で導電性フィラー105のサイズを選択するとフィラーのサイズはφ=5nm程度が限界となることから、絶縁性を考慮すると自ずとプリント基板の配線回路間のピッチも40μmが限界となっていた。上記問題を解消するために、導電性フィラー105の混入密度を疎化させる方法も考えられるが、これでは正常な電気的接続が得られない場合がある。しかし上記したように、電子機器の高密度実装が進められている現状からは、この限界ピッチを超える狭幅接続が望まれている。またこのような問題がある一方で、現在IC実装技術においては、より微細で高精度な実装能力が常に求められているが、微細配線の高精度実装は熟練作業者の能力に頼らざるを得ないという問題がある。   There are various sizes of the conductive filler 105, but the small size of the conductive filler 105 requires advanced techniques in the manufacturing technique, and is therefore expensive. When the size of the conductive filler 105 is selected at a price that can be used for a product, the filler size is limited to about φ = 5 nm. Therefore, when considering the insulation, the pitch between the printed circuit boards is naturally limited to 40 μm. It was. In order to solve the above problem, a method of reducing the mixing density of the conductive filler 105 is also conceivable. However, in this case, normal electrical connection may not be obtained. However, as described above, a narrow-width connection exceeding this limit pitch is desired from the current situation where high-density mounting of electronic devices is being promoted. On the other hand, there is a problem like this, but the current IC packaging technology always demands a finer and more accurate mounting capability. However, high-precision mounting of fine wiring has to rely on the skills of skilled workers. There is no problem.

本発明は、上記課題を鑑みてなされたもので、その目的は、従来より狭幅な配線接続を可能とすると共に、微細で高精度な実装を容易に行うことができる平行導電回路シート及び平行導電回路シートを用いた電子回路を提供することにある。   The present invention has been made in view of the above problems, and its object is to enable parallel wiring connection with a narrower width than in the prior art and a parallel conductive circuit sheet capable of easily performing fine and highly accurate mounting, and a parallel conductive circuit sheet. An object of the present invention is to provide an electronic circuit using a conductive circuit sheet.

上記課題を解決するために請求項1記載の本発明に係る電子回路は、所定の間隔で形成された複数本の導電配線を有する基板と、前記基板に設けられ、前記導電配線の配線方向と同じ方向に前記導電配線と対向して所定の間隔で形成された複数本の端子を有する電子部品と、シート状の絶縁層の一方の面上に平行且つ複数本形成された導電回路を有し、前記導電配線と前記端子とを連結接続するために前記基板に設けられた平行導電回路シートと、を備え、前記平行導電回路シートにおける前記導電回路の幅と間隔とは、前記導電配線の配線間隔以下及び前記電子部品の端子間隔以下であり、前記導電回路の長手方向における一端側の絶縁層が除去され、前記平行導電回路シートは、導電回路側を前記基板の導電配線側に向けて配置され、前記平行導電回路シートの前記導電回路における長手方向の一端側は、前記絶縁層が除去されて露出した導電回路上に前記電子部品の端子がフリップチップ実装され、前記平行導電回路シートの前記導電回路における長手方向の他端側は、前記導電回路と前記導電配線とが接続されることを要旨とする。 In order to solve the above problems, an electronic circuit according to the present invention according to claim 1 includes a substrate having a plurality of conductive wirings formed at a predetermined interval, and a wiring direction of the conductive wirings provided on the substrate. An electronic component having a plurality of terminals formed at a predetermined interval facing the conductive wiring in the same direction, and a conductive circuit formed in parallel and on one surface of a sheet-like insulating layer A parallel conductive circuit sheet provided on the substrate for connecting and connecting the conductive wiring and the terminal, and the width and interval of the conductive circuit in the parallel conductive circuit sheet is the wiring of the conductive wiring The insulating layer on one end side in the longitudinal direction of the conductive circuit is removed, and the parallel conductive circuit sheet is disposed with the conductive circuit side facing the conductive wiring side of the substrate. Before One end side in the longitudinal direction of the parallel conductive circuit sheet in the conductive circuit is flip-chip mounted on the conductive circuit exposed by removing the insulating layer, and the parallel conductive circuit sheet in the conductive circuit The other end side in the longitudinal direction is characterized in that the conductive circuit and the conductive wiring are connected.

請求項2記載の本発明は、請求項1に記載の電子回路であって、前記導電配線は、上面幅が下面幅より狭く形成され、前記平行導電回路シートの他端側は、前記導電配線の上面及び側面に貼り付けられていることを要旨とする。 The present invention according to claim 2 is the electronic circuit according to claim 1, wherein the conductive wiring is formed such that an upper surface width is narrower than a lower surface width, and the other end side of the parallel conductive circuit sheet is the conductive wiring. The gist is that it is affixed to the upper surface and the side surface.

請求項3記載の本発明は、請求項1または2に記載の電子回路であって、前記導電回路の幅は、前記基板における導電配線の配線間隔の1/2以下及び前記電子部品における端子の端子間隔の1/2以下であることを要旨とする。 A third aspect of the present invention is the electronic circuit according to the first or second aspect, wherein the width of the conductive circuit is equal to or less than a half of a wiring interval of the conductive wiring in the substrate and a terminal of the electronic component. The gist is that it is 1/2 or less of the terminal interval.

請求項4記載の本発明は、電子回路の製造方法であって、所定の配線間隔で形成された複数本の導電配線を有する基板と、所定の端子間隔で形成された複数本の端子を有する電子部品と、シート状の絶縁層の一方の面上に平行且つ複数本形成された導電回路を有し、前記導電回路の幅及び間隔が前記導電配線の配線間隔以下及び前記電子部品の端子の端子間隔以下である平行導電回路シートと、を用意し、前記平行導電回路シートは、前記導電回路の長手方向における一端側の絶縁層が除去され、前記平行導電回路シートの導電回路側を前記導電配線側に向けて前記基板に配置され、前記平行導電回路シートの前記導電回路における長手方向の他端側を、前記導電配線の配線方向と前記導電回路における長手方向とを一致させて前記導電配線に重ねて配置し、前記電子部品を、前記絶縁層が除去されて露出した導電回路上に前記電子部品の端子方向を前記導電回路における長手方向と一致させて配置し、前記導電配線と前記導電回路とを接続し、前記導電回路と前記端子とをフリップチップ実装することを要旨とする。請求項5記載の本発明は、請求項4に記載の電子回路の製造方法であって、前記導電配線は、上面幅が下面幅より狭く形成され、前記平行導電回路シートの他端を、前記導電配線の上面及び側面に貼り付けて前記導電配線と前記導電回路とを接続することを要旨とする。 The present invention according to claim 4 is a method of manufacturing an electronic circuit, comprising a substrate having a plurality of conductive wirings formed at a predetermined wiring interval and a plurality of terminals formed at a predetermined terminal interval. An electronic component and a plurality of conductive circuits formed in parallel on one surface of the sheet-like insulating layer, the width and interval of the conductive circuit being equal to or less than the wiring interval of the conductive wiring and the terminals of the electronic component; A parallel conductive circuit sheet having a terminal interval or less, wherein the insulating layer on one end side in the longitudinal direction of the conductive circuit is removed, and the conductive circuit side of the parallel conductive circuit sheet is connected to the conductive circuit side. The conductive wiring is disposed on the substrate toward the wiring side, and the other end side in the longitudinal direction of the conductive circuit of the parallel conductive circuit sheet is aligned with the wiring direction of the conductive wiring and the longitudinal direction of the conductive circuit. The electronic component is arranged in an overlapping manner on the conductive circuit exposed by removing the insulating layer, the terminal direction of the electronic component being aligned with the longitudinal direction of the conductive circuit, and the conductive wiring and the conductive circuit And the conductive circuit and the terminal are flip-chip mounted. The present invention according to claim 5 is the electronic circuit manufacturing method according to claim 4, wherein the conductive wiring is formed such that an upper surface width is narrower than a lower surface width, and the other end of the parallel conductive circuit sheet is connected to the other end of the parallel conductive circuit sheet. The gist is that the conductive wiring and the conductive circuit are connected to each other by being attached to an upper surface and a side surface of the conductive wiring.

本発明によれば、一様な厚さを有するシート状の絶縁層と、この絶縁層の面上に形成される導電性材料からなる導電回路とで構成される平行導電回路シートであって、この導電回路を平行に複数本配置すると共に、導電回路の間隔を少なくとも接続対象であるプリント基板の配線間隔以下、若しくはIC部品端子の端子間隔以下とすることで、プリント基板又はIC部品の端子1本に対して複数本の導電回路を接続する。これにより狭幅な配線接続を可能とし、更にこれまで高精度な実装能力が求められていた微細な配線接続及びIC実装を容易に行うことができるようになる。   According to the present invention, a parallel conductive circuit sheet comprising a sheet-like insulating layer having a uniform thickness and a conductive circuit made of a conductive material formed on the surface of the insulating layer, A plurality of the conductive circuits are arranged in parallel, and at least the interval between the conductive circuits is set to be equal to or smaller than the wiring interval of the printed circuit board to be connected or the terminal interval of the IC component terminals. A plurality of conductive circuits are connected to the book. As a result, a narrow wiring connection can be achieved, and further, fine wiring connection and IC mounting, which have been required to have high-precision mounting capability, can be easily performed.

また、この平行導電回路シートにおいて、導電回路の配線幅をプリント基板の配線間隔の1/2以下、又はIC部品の端子間隔の1/2以下にすることで、微細な配線接続及びIC実装をより容易に行うことができるようになる。   Moreover, in this parallel conductive circuit sheet, the wiring width of the conductive circuit is set to 1/2 or less of the wiring interval of the printed circuit board or 1/2 or less of the terminal interval of the IC component, thereby enabling fine wiring connection and IC mounting. It becomes possible to carry out more easily.

以下、図面を参照して、本発明の実施の形態を説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図1は、本発明の実施の形態に係る平行導電回路シート1の構成を示す図である。ここで図1(a)は平行導電回路シート1を上面から見た図であり、図1(b)は平行導電回路シート1のA−A断面図である。   FIG. 1 is a diagram showing a configuration of a parallel conductive circuit sheet 1 according to an embodiment of the present invention. Here, FIG. 1A is a view of the parallel conductive circuit sheet 1 as viewed from above, and FIG. 1B is a cross-sectional view taken along line AA of the parallel conductive circuit sheet 1.

図1(a),(b)に示すようにこの平行導電回路シート1は、一様な厚さを有するシート状の絶縁層5と、この絶縁層5の面上に形成される導電性材料からなる導電回路3とで構成され、この導電回路3が複数本、平行に配置形成されている。この導電回路3の幅Dは、少なくとも接続対象であるプリント基板の配線間隔da以下、若しくはIC部品端子の端子間隔db以下とし、望ましくは配線間隔da(又は端子間隔db)の1/2以下とする。また、より好ましくは1/3以下とする。これにより、より確実に高精度実装が可能になり、更には、高精度実装作業を容易に行うことができるようになる。   As shown in FIGS. 1A and 1B, the parallel conductive circuit sheet 1 includes a sheet-like insulating layer 5 having a uniform thickness and a conductive material formed on the surface of the insulating layer 5. The conductive circuit 3 is composed of a plurality of conductive circuits 3 arranged in parallel. The width D of the conductive circuit 3 is at least the wiring interval da of the printed circuit board to be connected, or the terminal interval db of the IC component terminals, and is preferably 1/2 or less of the wiring interval da (or the terminal interval db). To do. More preferably, it is 1/3 or less. As a result, high-accuracy mounting can be more reliably performed, and furthermore, high-precision mounting work can be easily performed.

ここで導電回路3は、望ましくは金、銅、錫等の何れかで形成されるか、若しくは銅メッキ後に金メッキが施される、或いは銅メッキ後に錫メッキが施された構成を有している。このように予め銅メッキを施すことにより配線材料コストを抑制させることができる。これに限らず、導電回路3を必要に応じて1μmの金メッキで作製するようにしてもよい。   Here, the conductive circuit 3 is preferably formed of gold, copper, tin, or the like, or has a configuration in which gold plating is performed after copper plating, or tin plating is performed after copper plating. . Thus, the wiring material cost can be suppressed by performing copper plating in advance. However, the present invention is not limited to this, and the conductive circuit 3 may be fabricated by 1 μm gold plating as necessary.

一方、絶縁層5は、例えばポリイミド等の熱硬化性樹脂、又は接着剤の代わりに使用するならばエポキシ系又はアクリル系の絶縁樹脂材料を使用する。これら何れかの樹脂材料又は何れかの樹脂材料を混合させた材料を適用しても良い。また絶縁層5は一様の厚さを有するシート状又はフィルム状に加工したものが好ましい。絶縁層5の材料は上記材料に限らず絶縁性を有する材料であれば他材料でも適用可能である。   On the other hand, the insulating layer 5 uses, for example, a thermosetting resin such as polyimide, or an epoxy or acrylic insulating resin material if used instead of an adhesive. Any one of these resin materials or a material in which any resin material is mixed may be applied. The insulating layer 5 is preferably processed into a sheet or film having a uniform thickness. The material of the insulating layer 5 is not limited to the above material, and any other material can be used as long as it is an insulating material.

また、この絶縁層5上に形成される導電回路3の作製方法はアディティブ法を用いるものとする。アディティブ法を用いることにより金属微細配線を容易に作製することができる。即ち、アディティブ法を用いることにより、5μm幅の狭幅配線を作製することが可能となる。尚、この配線作製方法はサブトラクティブ法を用いることでも実現できるが、作業工程と微細加工の精度の観点からはアディティブ法を用いることが好ましい。   In addition, an additive method is used as a method for manufacturing the conductive circuit 3 formed on the insulating layer 5. By using the additive method, metal fine wiring can be easily produced. That is, by using the additive method, a narrow wiring having a width of 5 μm can be manufactured. This wiring manufacturing method can also be realized by using a subtractive method, but it is preferable to use the additive method from the viewpoint of work process and precision of microfabrication.

次に図2、図3を参照して、本発明の実施の形態に係る平行導電回路シート1の作製方法及び作用を説明する。   Next, with reference to FIG. 2, FIG. 3, the production method and effect | action of the parallel conductive circuit sheet 1 which concern on embodiment of this invention are demonstrated.

図2は、接続前の平行導電回路シート1と接続対象であるプリント基板の配置構成を示す図である。また図3(a)は、接続後の平行導電回路シート1とプリント基板7a,7bの配置構成を示す図であり、図3(b)は、図3(a)の上面図である。   FIG. 2 is a diagram showing an arrangement configuration of the parallel conductive circuit sheet 1 before connection and the printed circuit board to be connected. FIG. 3A is a diagram showing an arrangement configuration of the parallel conductive circuit sheet 1 and the printed boards 7a and 7b after connection, and FIG. 3B is a top view of FIG. 3A.

まず図2に示すように、接続対象であるプリント基板7a,7bを用意し、このプリント基板7a,7bに形成されている導電配線9の配線方向を一致させることで、接続対象であるプリント基板7a,7bの配線が同一線上に並ぶように位置調節する。   First, as shown in FIG. 2, printed circuit boards 7a and 7b to be connected are prepared, and the wiring directions of the conductive wirings 9 formed on the printed circuit boards 7a and 7b are made to coincide with each other, so that the printed circuit boards to be connected. The positions are adjusted so that the wirings 7a and 7b are aligned on the same line.

次いで、図3(a)に示すように、平行導電回路シート1をプリント基板7a,7b上に降下させ、プリント基板7a,7bの導電配線9の端と導電回路3の端とを接触後、平行導電回路シート1の上方から一定圧力を加えてプリント基板7a,7bと平行導電回路シート1を接合させる。この接合により2枚のプリント基板7a,7bを平行導電回路シート1を介して導通可能に接続することができる。   Next, as shown in FIG. 3A, the parallel conductive circuit sheet 1 is lowered onto the printed circuit boards 7a and 7b, and after contacting the ends of the conductive wiring 9 and the conductive circuit 3 on the printed circuit boards 7a and 7b, The printed circuit boards 7a and 7b and the parallel conductive circuit sheet 1 are joined by applying a constant pressure from above the parallel conductive circuit sheet 1. By this joining, the two printed circuit boards 7a and 7b can be connected through the parallel conductive circuit sheet 1 so as to be conductive.

尚、ここで導電回路3が金メッキで形成され、接続対象であるプリント基板7a,7bの導電配線9も金メッキで形成された場合には超音波拡散接合で接合する。一方、導電回路3が錫メッキで形成され、接続対象であるプリント基板7a,7bの導電配線9が金メッキで形成された場合には加圧及び加熱により両配線を接合する(金錫結合ともいう)。   Here, when the conductive circuit 3 is formed by gold plating and the conductive wiring 9 of the printed boards 7a and 7b to be connected is also formed by gold plating, they are bonded by ultrasonic diffusion bonding. On the other hand, when the conductive circuit 3 is formed by tin plating and the conductive wiring 9 of the printed circuit boards 7a and 7b to be connected is formed by gold plating, both wirings are joined by pressurization and heating (also called gold-tin bonding). ).

ここで平行導電回路シート1に形成された導電回路3の幅Dは、プリント基板7a,7bの導電配線9の幅より狭く、具体的には1/2以下、望ましくは1/3以下とする。そのため平行導電回路シート1の基板面(X−Y面)のアライメントが取れれば、基板面に垂直方向(θ方向)のアライメントのみでプリント基板上に平行に平行導電回路シート1を接合させることができる。その結果、簡単な設定のみで実装できるので従来のように高精度な実装能力がなくとも微細配線同士を容易に接続することができる。   Here, the width D of the conductive circuit 3 formed on the parallel conductive circuit sheet 1 is narrower than the width of the conductive wiring 9 of the printed circuit boards 7a and 7b, specifically 1/2 or less, preferably 1/3 or less. . Therefore, if the substrate surface (XY plane) of the parallel conductive circuit sheet 1 is aligned, the parallel conductive circuit sheet 1 can be joined in parallel on the printed circuit board only by alignment in the direction perpendicular to the substrate surface (θ direction). it can. As a result, since it can be mounted only with simple settings, it is possible to easily connect the fine wirings without the high-precision mounting capability as in the prior art.

また図3(b)に示すように、プリント基板7a,7bの導電配線9の配線間隔daより導電回路3の幅Dが十分狭いので、1本の導電配線9に対し複数本の導電回路3が同時に接続されることになる。これにより配線間隔daが非常に狭くても、導電回路3の配線幅Dがより狭幅を有しているので平行導電回路シート1の導電回路3とプリント基板の導電配線がショートしない。   Further, as shown in FIG. 3B, since the width D of the conductive circuit 3 is sufficiently narrower than the wiring interval da of the conductive wiring 9 of the printed circuit boards 7a and 7b, a plurality of conductive circuits 3 are provided for one conductive wiring 9. Will be connected at the same time. Thereby, even if the wiring interval da is very narrow, the conductive circuit 3 of the parallel conductive circuit sheet 1 and the conductive wiring of the printed circuit board do not short-circuit because the wiring width D of the conductive circuit 3 is narrower.

即ち、従来は導電配線9が幅広で導電配線間隔daが幅狭であると、導電回路3が隣の導電配線9にまたがって接続される恐れがあったが、本発明の導電回路3によれば導電配線間隔daよりも十分に狭幅の導電回路3が平行に複数本配置されているので、多少の位置ずれが生じても導電回路3と導電配線9をショートさせることなく、高精度配線を容易に実現することができる。   That is, conventionally, when the conductive wiring 9 is wide and the conductive wiring interval da is narrow, the conductive circuit 3 may be connected across the adjacent conductive wiring 9. For example, a plurality of conductive circuits 3 that are sufficiently narrower than the conductive wiring interval da are arranged in parallel, so that even if a slight misalignment occurs, the conductive circuit 3 and the conductive wiring 9 are not short-circuited, and high-precision wiring is achieved. Can be easily realized.

また更に、前述の問題点として挙げたように、従来のFPC(フレキシブル基板)とRPC(リジット基板)間の接続ではACFが使用されており、その接続の特性上配線ピッチは40μm程度が限界であったが、本発明の平行導電回路シート1を適用することにより接続回路間のピッチを40μmピッチ以下で接続することが可能になる。   Furthermore, as mentioned above, ACF is used for the connection between the conventional FPC (flexible substrate) and RPC (rigid substrate), and the wiring pitch is limited to about 40 μm due to the characteristics of the connection. However, by applying the parallel conductive circuit sheet 1 of the present invention, it becomes possible to connect the connection circuits with a pitch of 40 μm or less.

また本発明の平行導電回路シート1は、単純な平行回路構造を有しているため、通常のFPCによるシートの製造も可能である。また、より精密なピッチを有する平行導電回路シート1を作製する場合はアディティブ法を積極的に適用する。アディティブ法を適用することにより、本実施の形態で示した同一の平行回路構造を作製する際に容易に高精度な配線を大量生産することが可能となり、コストパフォーマンス性にも優れた効果を発揮する。   In addition, since the parallel conductive circuit sheet 1 of the present invention has a simple parallel circuit structure, it is possible to manufacture a sheet by ordinary FPC. Moreover, when producing the parallel conductive circuit sheet 1 having a more precise pitch, the additive method is positively applied. By applying the additive method, high-precision wiring can be easily mass-produced when producing the same parallel circuit structure shown in this embodiment, and the cost performance is excellent. To do.

導電配線9が狭幅で形成されたプリント基板同士の配線間接続、及びこのようなプリント基板とIC端子間の導通接続において、本発明の平行導電回路シート1を用いることで、その実現が容易となる。図4〜図6を参照して、本発明の平行導電回路シート1を用いた具体的な接合例を説明する。   The parallel conductive circuit sheet 1 according to the present invention can be easily used in the connection between wirings of the printed boards in which the conductive wiring 9 is formed with a narrow width and in the conductive connection between the printed board and the IC terminal. It becomes. With reference to FIGS. 4-6, the specific joining example using the parallel conductive circuit sheet 1 of this invention is demonstrated.

まず図4を参照して、本発明の平行導電回路シート1を、プリント基板7aとIC部品のFC実装におけるインターポーザ(IC部品間や半導体チップの層間の接続配線を形成する中継用基板)として使用する例を説明する。   First, referring to FIG. 4, the parallel conductive circuit sheet 1 of the present invention is used as an interposer (relay substrate for forming connection wiring between IC components and between semiconductor chips) in the FC mounting of the printed circuit board 7a and the IC components. An example will be described.

図4は、IC部品をプリント基板に実装する接続構成を示す図であり、図4(a)は、接続前の構成図、図4(b)は、接続後の構成図、図4(c)は、図4(b)のB−B断面図を示している。   4A and 4B are diagrams showing a connection configuration in which an IC component is mounted on a printed circuit board. FIG. 4A is a configuration diagram before connection, FIG. 4B is a configuration diagram after connection, and FIG. ) Shows a BB cross-sectional view of FIG.

まず図4(a)に示すように、接続対象であるプリント基板7aと、平行導電回路シート1と、ICを用意する。ここで平行導電回路シート1の一端の絶縁層5はエッチング等により除去し複数本の導電回路3が露出するように加工されている。このような加工が施された平行導電回路シート1の面方向をプリント基板7aの面方向と平行になるように配置調節を行い、更に導電回路3と導電配線9の配線方向が一致するようにX−Y面方向の調節を行う。   First, as shown to Fig.4 (a), the printed circuit board 7a which is a connection object, the parallel conductive circuit sheet 1, and IC are prepared. Here, the insulating layer 5 at one end of the parallel conductive circuit sheet 1 is removed by etching or the like so that a plurality of conductive circuits 3 are exposed. Placement adjustment is performed so that the surface direction of the parallel conductive circuit sheet 1 subjected to such processing is parallel to the surface direction of the printed circuit board 7a, and further, the wiring directions of the conductive circuit 3 and the conductive wiring 9 are matched. Adjust the XY plane direction.

次いで図4(b)に示すように、導電配線9上に導電回路3を配置設定した後、露出している導電回路3上にIC部品の端子が配置されるように位置合わせ調節を行い、この調節完了後にFC実装を行う。その具体的な接続方法は、本例のように接合対象がIC部品の場合は、IC端子を金、或いは半田バンプとし、加圧と加熱により接続する。   Next, as shown in FIG. 4B, after setting the conductive circuit 3 on the conductive wiring 9, alignment adjustment is performed so that the terminal of the IC component is arranged on the exposed conductive circuit 3, After this adjustment is completed, FC mounting is performed. As a specific connection method, when an object to be joined is an IC component as in this example, the IC terminal is made of gold or a solder bump and is connected by pressurization and heating.

次に図5を参照して、他の接合例を説明する。図5は、プリント基板間の一接続例であるが、第1の実施の形態(図2)と異なる点は、プリント基板7cに形成された導電配線の幅が、一方の導電配線13aは幅広であり、他方の導電配線13bはこれよりも幅狭である点にある。   Next, another joining example will be described with reference to FIG. FIG. 5 shows an example of connection between printed circuit boards. The difference from the first embodiment (FIG. 2) is that the width of the conductive wiring formed on the printed circuit board 7c is wide and one conductive wiring 13a is wide. The other conductive wiring 13b is narrower than this.

このように導電配線13a,13bの幅が異なる場合であっても、幅広の配線幅方向内に幅狭の配線幅が収まる導電配線13a,13bが設計されている場合は、本発明の平行導電回路シート1を用いることで両導電配線13a、13bを接続することができる。また導電配線13a,13bの配線間隔daが共に同一であれば、本発明の平行導電回路シート1を用いることで両導電配線13a、13bを接続することができる。   Even when the conductive wirings 13a and 13b have different widths as described above, when the conductive wirings 13a and 13b in which the narrow wiring width is accommodated in the wide wiring width direction are designed, the parallel conductive of the present invention is used. By using the circuit sheet 1, both conductive wirings 13a and 13b can be connected. Further, if the wiring spacing da of the conductive wirings 13a and 13b is the same, the conductive wirings 13a and 13b can be connected by using the parallel conductive circuit sheet 1 of the present invention.

次に図6を参照して、更に他の接合例を説明する。図6(a)は、プリント基板上に形成された導電配線9端部を拡大した図であり、図6(b)は、導電配線9と平行導電回路シート1の接続例を示す図である。   Next, still another joining example will be described with reference to FIG. 6A is an enlarged view of the end portion of the conductive wiring 9 formed on the printed circuit board, and FIG. 6B is a diagram illustrating a connection example of the conductive wiring 9 and the parallel conductive circuit sheet 1. .

まずここで、従来のFPC等のサブトラクティブ法で作製されたプリント基板の導電配線9は、図6に示すように、回路上面幅(トップ)が回路下面幅(ボトム)より狭い。即ち、回路上面幅が約15〜16μmに対し回路下面幅が20μmの台形状の断面を有している。しかしIC部品の実装は回路上面に実装するため、回路上面幅をある程度確保しなければ高信頼性を有するIC部品実装は困難である。従って幅広の回路上面を形成すれば、プリント基板の微細化は困難となるという問題点があった。   First, here, the conductive wiring 9 of the printed circuit board manufactured by a subtractive method such as a conventional FPC has a circuit upper surface width (top) narrower than a circuit lower surface width (bottom) as shown in FIG. That is, it has a trapezoidal cross section in which the circuit upper surface width is about 15-16 μm and the circuit lower surface width is 20 μm. However, since the IC component is mounted on the upper surface of the circuit, it is difficult to mount the IC component with high reliability unless the circuit upper surface width is secured to some extent. Therefore, if a wide circuit upper surface is formed, it is difficult to miniaturize the printed circuit board.

しかし本発明の平行導電回路シート1をアディティブ法を用いて作製し、これを図6(b)に示すように、導電配線9の回路上面及び回路側面を覆うように貼り付けることで、貼り付けられた導電回路3の延長線上に幅広の実装有効幅を得ることができる。   However, the parallel conductive circuit sheet 1 of the present invention is produced by using the additive method, and as shown in FIG. 6 (b), it is attached by covering the circuit upper surface and the circuit side surface of the conductive wiring 9. A wide mounting effective width can be obtained on the extended line of the conductive circuit 3 formed.

従って、本発明の平行導電回路シート1をインターポーザとして使用することにより、従来の幅狭の回路上面を利用して十分な実装有効幅を得ることができる。その結果、プリント基板側の回路形状を考慮して実装する必要がなくなる。   Therefore, by using the parallel conductive circuit sheet 1 of the present invention as an interposer, a sufficient mounting effective width can be obtained using the conventional narrow circuit upper surface. As a result, it is not necessary to mount in consideration of the circuit shape on the printed circuit board side.

本発明の実施の形態に係る平行導電回路シート1の構成図であり、(a)は平行導電回路シート1の上面図、(b)は平行導電回路シート1のA−A断面図である。It is a lineblock diagram of parallel conductive circuit sheet 1 concerning an embodiment of the invention, (a) is a top view of parallel conductive circuit sheet 1, and (b) is an AA sectional view of parallel conductive circuit sheet 1. 接続前の平行導電回路シート1とプリント基板7a,7bの配置構成図である。It is arrangement | positioning block diagram of the parallel conductive circuit sheet 1 and printed circuit board 7a, 7b before a connection. 平行導電回路シート1とプリント基板7a,7bの配置構成図であって、(a)は接続後の配置構成図、(b)は、(a)の上面図である。FIG. 2 is an arrangement configuration diagram of the parallel conductive circuit sheet 1 and the printed boards 7a and 7b, in which (a) is an arrangement configuration diagram after connection, and (b) is a top view of (a). 本発明の実施の形態に係る平行導電回路シート1を用いた接合例を示す実施例1の構成図である。It is a block diagram of Example 1 which shows the example of joining using the parallel conductive circuit sheet 1 which concerns on embodiment of this invention. 本発明の実施の形態に係る平行導電回路シート1を用いた接合例を示す実施例2の構成図である。It is a block diagram of Example 2 which shows the example of joining using the parallel conductive circuit sheet 1 which concerns on embodiment of this invention. 本発明の実施の形態に係る平行導電回路シート1を用いた接合例を示す実施例3の構成図である。It is a block diagram of Example 3 which shows the example of joining using the parallel conductive circuit sheet 1 which concerns on embodiment of this invention. 従来のプリント基板とIC部品の接続構成を示す図である。It is a figure which shows the connection structure of the conventional printed circuit board and IC components.

符号の説明Explanation of symbols

1…平行導電回路シート
3…導電回路
5…絶縁層
7a,7b…プリント基板
9…導電配線
13a,13b…導電配線
103…ACF
105…導電性フィラー
107…基板
109…配線
111…半導体チップ
113…端子
DESCRIPTION OF SYMBOLS 1 ... Parallel conductive circuit sheet 3 ... Conductive circuit 5 ... Insulating layer 7a, 7b ... Printed circuit board 9 ... Conductive wiring 13a, 13b ... Conductive wiring 103 ... ACF
105 ... Conductive filler 107 ... Substrate 109 ... Wiring 111 ... Semiconductor chip 113 ... Terminal

Claims (5)

所定の間隔で形成された複数本の導電配線を有する基板と、A substrate having a plurality of conductive wirings formed at predetermined intervals;
前記基板に設けられ、前記導電配線の配線方向と同じ方向に前記導電配線と対向して所定の間隔で形成された複数本の端子を有する電子部品と、An electronic component provided on the substrate and having a plurality of terminals formed at a predetermined interval facing the conductive wiring in the same direction as the wiring direction of the conductive wiring;
シート状の絶縁層の一方の面上に平行且つ複数本形成された導電回路を有し、前記導電配線と前記端子とを連結接続するために前記基板に設けられた平行導電回路シートと、A parallel conductive circuit sheet provided on the substrate for connecting and connecting the conductive wiring and the terminal, the conductive circuit having a plurality of conductive circuits formed in parallel on one surface of the sheet-like insulating layer;
を備え、With
前記平行導電回路シートにおける前記導電回路の幅と間隔とは、前記導電配線の配線間隔以下及び前記電子部品の端子間隔以下であり、前記導電回路の長手方向における一端側の絶縁層が除去され、The width and interval of the conductive circuit in the parallel conductive circuit sheet are not more than the wiring interval of the conductive wiring and the terminal interval of the electronic component, and the insulating layer on one end side in the longitudinal direction of the conductive circuit is removed,
前記平行導電回路シートは、導電回路側を前記基板の導電配線側に向けて配置され、The parallel conductive circuit sheet is disposed with the conductive circuit side facing the conductive wiring side of the substrate,
前記平行導電回路シートの前記導電回路における長手方向の一端側は、前記絶縁層が除去されて露出した導電回路上に前記電子部品の端子がフリップチップ実装され、One end side in the longitudinal direction of the conductive circuit of the parallel conductive circuit sheet is flip-chip mounted on the conductive circuit exposed by removing the insulating layer,
前記平行導電回路シートの前記導電回路における長手方向の他端側は、前記導電回路と前記導電配線とが接続されることを特徴とする電子回路。The electronic circuit, wherein the conductive circuit and the conductive wiring are connected to the other end side in the longitudinal direction of the parallel conductive circuit sheet in the conductive circuit.
請求項1に記載の電子回路であって、The electronic circuit according to claim 1,
前記導電配線は、上面幅が下面幅より狭く形成され、The conductive wiring is formed such that the upper surface width is narrower than the lower surface width,
前記平行導電回路シートの他端側は、前記導電配線の上面及び側面に貼り付けられていることを特徴とする電子回路。The other end side of the said parallel conductive circuit sheet is affixed on the upper surface and side surface of the said conductive wiring, The electronic circuit characterized by the above-mentioned.
請求項1または2に記載の電子回路であって、An electronic circuit according to claim 1 or 2,
前記導電回路の幅は、前記基板における導電配線の配線間隔の1/2以下及び前記電子部品における端子の端子間隔の1/2以下であることを特徴とする電子回路。The width of the said conductive circuit is 1/2 or less of the wiring space | interval of the conductive wiring in the said board | substrate, and 1/2 or less of the terminal space | interval of the terminal in the said electronic component, The electronic circuit characterized by the above-mentioned.
電子回路の製造方法であって、An electronic circuit manufacturing method comprising:
所定の配線間隔で形成された複数本の導電配線を有する基板と、A substrate having a plurality of conductive wirings formed at a predetermined wiring interval;
所定の端子間隔で形成された複数本の端子を有する電子部品と、An electronic component having a plurality of terminals formed at predetermined terminal intervals;
シート状の絶縁層の一方の面上に平行且つ複数本形成された導電回路を有し、前記導電回路の幅及び間隔が前記導電配線の配線間隔以下及び前記電子部品の端子の端子間隔以下である平行導電回路シートと、を用意し、A plurality of conductive circuits formed in parallel and on one surface of the sheet-like insulating layer, wherein the width and interval of the conductive circuit are less than or equal to the interval between the conductive wires and less than the interval between the terminals of the electronic component; Prepare a parallel conductive circuit sheet,
前記平行導電回路シートは、前記導電回路の長手方向における一端側の絶縁層が除去され、前記平行導電回路シートの導電回路側を前記導電配線側に向けて前記基板に配置され、前記平行導電回路シートの前記導電回路における長手方向の他端側を、前記導電配線の配線方向と前記導電回路における長手方向とを一致させて前記導電配線に重ねて配置し、The parallel conductive circuit sheet is disposed on the substrate with an insulating layer on one end side in the longitudinal direction of the conductive circuit removed, and the parallel conductive circuit sheet is disposed on the substrate with the conductive circuit side of the parallel conductive circuit sheet facing the conductive wiring side. The other end side in the longitudinal direction of the conductive circuit of the sheet is arranged to overlap the conductive wiring so that the wiring direction of the conductive wiring and the longitudinal direction of the conductive circuit coincide with each other,
前記電子部品を、前記絶縁層が除去されて露出した導電回路上に前記電子部品の端子方向を前記導電回路における長手方向と一致させて配置し、The electronic component is disposed on the conductive circuit exposed by removing the insulating layer so that the terminal direction of the electronic component coincides with the longitudinal direction of the conductive circuit,
前記導電配線と前記導電回路とを接続し、前記導電回路と前記端子とをフリップチップ実装することを特徴とする電子回路の製造方法。A method of manufacturing an electronic circuit, wherein the conductive wiring and the conductive circuit are connected, and the conductive circuit and the terminal are flip-chip mounted.
請求項4に記載の電子回路の製造方法であって、A method of manufacturing an electronic circuit according to claim 4,
前記導電配線は、上面幅が下面幅より狭く形成され、The conductive wiring is formed such that the upper surface width is narrower than the lower surface width,
前記平行導電回路シートの他端を、前記導電配線の上面及び側面に貼り付けて前記導電配線と前記導電回路とを接続することを特徴とする電子回路の製造方法。A method for manufacturing an electronic circuit, comprising: bonding the other end of the parallel conductive circuit sheet to an upper surface and a side surface of the conductive wiring to connect the conductive wiring and the conductive circuit.
JP2004021382A 2004-01-29 2004-01-29 Electronic circuit using parallel conductive circuit sheet and method for manufacturing the same Expired - Fee Related JP4430419B2 (en)

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