JP4155080B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP4155080B2
JP4155080B2 JP2003097450A JP2003097450A JP4155080B2 JP 4155080 B2 JP4155080 B2 JP 4155080B2 JP 2003097450 A JP2003097450 A JP 2003097450A JP 2003097450 A JP2003097450 A JP 2003097450A JP 4155080 B2 JP4155080 B2 JP 4155080B2
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bump
semiconductor chip
electrode pattern
circuit board
center
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JP2004304082A (en
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隆雄 西村
光久 渡部
史彦 安藤
昌典 夏秋
晃 高島
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置の製造方法に係り、特に半導体チップを回路基板上に高密度実装する方法に関する。
近年、携帯電話やデジタルカメラ等の携帯用電子機器の普及に伴って、それらに用いられる電子回路の小型化、低コスト化に対する要求が厳しくなっており、それに応えるため回路パターンの微細化・高集積化による部品数の低減は勿論のこと、回路パターンが形成された半導体チップを低コストで高密度実装する技術の一層の進展が求められている。
【０００２】
【従来の技術】
半導体チップを回路基板に高密度で実装する方法としてフリップチップ方式が知られている。図４(a) 、(b) は従来のフリップチップ方式を説明する断面図である。同図において、半導体チップ１の表面には外部接続用の多数のバンプ２が形成されており、また、回路基板３には半導体チップ１のバンプ２とそれぞれ対応する位置に電極パターン４が形成されている。電子機器の低コスト化を優先させる場合、回路基板３としてはガラスエポキシ等の有機樹脂が用いられる。
【０００３】
まず、図４(a) に示したように、電極パターン４が形成された回路基板３の表面に対し、バンプ２が形成された半導体チップ１の表面を下向きにして対向させ、この状態で半導体チップ１を水平方向に移動させることによりバンプ２と電極パターン４を位置合わせする。位置合わせに際しては、バンプ２と電極パターン４の接触面積が出来るだけ大きくなるように、バンプ２の中心と電極パターン４の中心を一致させる方向に半導体チップ１を移動させる。
【０００４】
ついで、図４(b) に示したように、半導体チップ１に下向きの荷重を印加して矢印方向へ移動させ回路基板３に押圧する。下向きの荷重の他に、必要に応じて加熱、半導体チップ１への超音波印加を行う。これによりバンプ２が電極パターン４と接続されることになる。その後、バンプ２と電極パターン４の接続領域近傍を樹脂で覆った後加熱硬化させることによりバンプ２と電極パターン４との接続を安定なものにする。
【０００５】
以上のように、フリップチップ方式は多数のバンプを電極パターンに一括接続することができるためワイヤボンディング方式に比べて少ない工数で実装可能であり且つ接続点での寄生インダクタンスを小さくすることができる等の利点があり広く用いられている。
半導体チップに形成されるバンプとしては、スタッドバンプあるいはめっきバンプが用いられる。スタッドバンプは半導体チップ上の電極パッドに金あるいは金合金からなるワイヤを用いてワイヤボンディングを行った後、このワイヤを加熱しながら引きちぎって形成される。同一半導体チップに形成されるバンプ数が少ない場合やバンプ間ピッチが比較的大きい場合に主として用いられる。また、めっきバンプは、電極パッド上にレジスト開口パターンを形成し、この開口部内をメッキ材により埋め込んでバンプとするものであり、バンプ径をパターニングにより決めることができるためスタッドバンプに比べて微細化が可能であり、主としてバンプ数が多い場合やバンプ間ピッチが小さい場合に用いられる。
【０００６】
また、上述のフリップチップ方式を簡略化して実装工程の一層の低コスト化を図る試みも行われている( 例えば、特許文献１参照) 。図５(a) 、(b) は従来の簡略化されたフリップチップ方式を説明する断面図である。図５(a) に示したように、回路基板３上に電極パターン４を覆うように予め熱硬化性樹脂５を塗布し、この状態で回路基板３の表面と半導体チップ１の表面を対向させ、図４に述べた例と同様に電極パターン４とバンプ２の位置合わせを行う。そして、図５(b) に示したように、半導体チップ１に下向きの荷重を印加して回路基板３へ押圧すると、バンプ２は熱硬化性樹脂５を押し退けて電極パターン４と接続されることになる。その後、樹脂を加熱硬化させることによりバンプ２と電極パターン４の接続を安定化する。
【０００７】
【特許文献１】
特開平９−９７８１６号公報( 第４−５頁、第２図)
【０００８】
【発明が解決しようとする課題】
以上述べたフリップチップ方式には、多数のバンプを有する半導体チップを少ない工数で実装することができる等の利点がある反面、回路基板材として軟質性のある樹脂を用いた場合に以下のような問題が生じる。
図６は従来のフリップチップ方式の問題点を説明する断面図である。半導体チップ１に下向きの荷重を印加して回路基板３に押圧したとき、押圧の際の応力により回路基板３に局所的なたわみが生じバンプ２が回路基板３へ沈み込む結果、半導体チップ１と回路基板３間のギャップが狭くなる。これにより、同図に見られるように半導体チップ１の表面が電極パターン４に直接接触する恐れが生じる。これは半導体チップ１の表面に形成されている回路パターンを傷つける原因となる。また、前述のように半導体チップ１と回路基板３間のギャップが狭くなると、ギャップ内での樹脂の流動性が低下するため、加熱硬化中樹脂に含まれているガスの排出が充分に行われずギャップ内の樹脂にボイドが残ることになる。あるいは、フリップチップ接続後に樹脂で覆ったとしてもギャップに充填される樹脂の量が少なくなるためバンプと電極パターンの接続強度が低下する。これらの現象は、いずれもフリップチップ方式の信頼性を低下させる原因となる。
【０００９】
フリップチップ実装の際の半導体チップと基板の間のギャップを保持する上で、(1) 半導体チップに印加する下向きの荷重を小さくして回路基板のたわみを抑える方法、(2) 半導体チップに予め背の高いバンプを形成する方法、(3) 回路基板の材料としてたわみの生じ易いガラスエポキシ樹脂に代えて硬質の石英ガラス等を用いる方法が考えられる。しかし、(1) の方法ではバンプと電極パターンとの接触が不十分となって接続強度の低下をもたらす恐れがある。また、(2) の方法においてスタッドバンプを用いる場合、バンプ径をワイヤ径以上に大きくすることが難しいためバンプの微細化によりワイヤ径が小さくなると背の高いバンプを形成することは困難であり、めっきバンプを用いる場合にはめっきを厚くする必要があるため高コストになる。また、(3) の方法では基板コストが高くなるという問題がある。
【００１０】
そこで、本発明は半導体チップを回路基板にフリップチップ接続する際に低コスト且つ簡単な方法で半導体チップと回路基板間のギャップを保持し、フリップチップ接続の信頼性を向上させることを目的とする。
【００１１】
【課題を解決するための手段】
上記課題を解決するため本発明は、複数のバンプの形成された半導体チップを、各バンプに対応した電極パターンの形成された回路基板にフェイスダウンボンディングにより接続する半導体装置の製造方法において、各該バンプと各該電極パターンが向かい合うように該半導体チップと該回路基板を離間して対向させた状態で、上方から見て各該バンプと各該電極パターンが部分的に重なる範囲内で各該バンプの中心と各該電極パターンの中心を水平方向にずらして位置合わせし、ついで、該半導体チップを下方向に移動させて該回路基板に圧接し、各該バンプと各該電極パターンを接触させ、ついで、該半導体チップを、各該バンプの中心と各該電極パターンの中心が一致する方向へ向けて水平に移動させて、各該電極パターンの側面に各該バンプを押圧することにより、各該バンプに塑性変形を生じさせながら各該バンプを各該電極パターンに接続する。
【００１２】
また、上記構成において、該半導体チップを、該バンプの中心と該電極パターンの中心が一致する方向へ向けて斜め下方向へ移動させる。
また、上記構成において、該半導体チップを、該バンプの中心と該電極パターンの中心が一致する方向へ向けて超音波を印加しつつ移動させる。
また、上記構成において、該超音波の振動方向を、該半導体チップの移動方向に対し垂直な方向にする。
【００１３】
また、上記構成において、該半導体チップと該回路基板間に予め樹脂を介在させた状態で、該バンプを該電極パターンに接続する。
【００１４】
【発明の実施の形態】
図１(a) 〜(c) は本発明の実施例を説明する図であり、各図左側には半導体チップ１をガラスエポキシからなる回路基板３と対向して配置したときのＡＡ断面図が示されている。半導体チップ１の表面には金あるいは金合金からなるバンプ２、回路基板３の表面には金めっきされた銅からなる電極パターン４がそれぞれ形成されている。また、各図右側には、上方から見たときのバンプ２と電極パターン４の配置位置を表す平面図が示されている。
【００１５】
まず、図１(a) に見られるように、バンプ２と電極パターン４が向かい合うように半導体チップ１と回路基板３を離間して対向させ、この状態で上方から見てバンプ２と電極パターン４が部分的に重なる範囲内でバンプ２と電極パターン４の中心を水平方向にずらせて位置合わせする。ついで、図１(b) に示したように、半導体チップ１に下向きの荷重を印加して下方へ移動させ回路基板３に押圧する。バンプ２と電極パターン４の中心をずらせているため、押圧時におけるバンプ２と電極パターン４の接触面積は小さく、その結果、回路基板３へ加わる応力が小さくなる。そのため、回路基板３のたわみが小さくなり、従来に比べて半導体チップ１と回路基板３の間のギャップを広くすることができる。
【００１６】
ついで、図１(c) に矢印６で示したように、バンプ２の中心と電極パターン４の中心が一致する方向へ向けて水平方向に半導体チップ１を移動させる。これによりバンプ２が電極パターン４の側面を押圧して塑性変形し電極パターン４との接触面積を増やしながら電極パターン４と接続する。この工程では、回路基板３に対して上方からの応力が殆ど加わらないため回路基板３のたわみが大きくなることはない。
【００１７】
なお、バンプ２と電極パターン４との接続に際して、半導体チップ１と回路基板３の一方、あるいは双方を加熱することによりバンプ２の塑性変形をより容易にしバンプ２と電極パターン４の接続強度を強固にすることができる。
さらに、バンプと電極パターンとの接続強度をより強固にするため、バンプの中心と電極パターンの中心が一致する方向へ向けて水平方向に半導体チップを移動させる際、半導体チップに超音波を印加することができる。超音波振動の振幅は通常０．２μm から２μm 程度の大きさに設定される。径１５μm 程度の微細バンプを有する半導体チップでは、この振動振幅はバンプ径に対して無視できない大きさとなり、バンプと電極パターンの接触面積に対しても大きな影響を与える場合が生じる。この問題は、微細バンプを有する半導体チップに対して図１(c) に矢印７で示したように、超音波振動の振動方向を半導体チップの移動方向６に対して垂直な方向へ設定することにより回避できる。
【００１８】
次に、図２(a) 〜(c) は上述した実施例の変形例を説明する図であり、図１と同一のものには同一番号を付してある。まず、図２(a) に見られるように、バンプ２と電極パターン４が向かい合うように半導体チップ１と回路基板３を離間して対向させ、この状態で上方から見てバンプ２と電極パターン４が部分的に重なる範囲内でバンプ２と電極パターン４の中心を水平方向にずらせて位置合わせする。ついで、図２(b) に示したように、半導体チップ１に下向きの荷重を印加して下方へ移動させ回路基板３に押圧する。ついで、バンプ２の中心と電極パターン４の中心が一致する方向へ向けて斜め下方向に半導体チップ１を移動させバンプ２に塑性変形を生じさせることによりバンプ２と電極パターン４の接触面積を増やしてバンプ２と電極パターン４を接続する。これにより先の実施例と同様な効果を得ることができる。先の実施例と同様に、この実施例においても加熱処理、超音波処理あるいはその両方の処理を行うことにより接続強度をより強固にすることができる。
【００１９】
また、上述したいずれの実施例においても、水平面内において半導体チップを移動させる方向は、以下のように半導体チップのバンプ配列に応じて異なる方向へ設定される。
図３は半導体チップ１と回路基板３を対向させた状態を示す平面図である。バンプ２及び電極パターン４の一部は半導体チップ１を上方から見て透視した状態で示されている。
【００２０】
図３(a) は半導体チップ１の２辺にバンプ２が配列されている場合であり、半導体チップ１を図中示した矢印方向へ移動させることにより全てのバンプの中心をそれぞれ対応する電極パターンの中心に近づけることができる。図３(b) は半導体チップ１の４辺にバンプ２が配列されている場合であり、半導体チップ１を図中矢印で示した斜め上方へ移動させることにより全てのバンプの中心をそれぞれ対応する電極パターンの中心に近づけることができる。
【００２１】
【発明の効果】
以上のように本発明によれば、フリップチップ実装に際してバンプと電極パターンとの接続強度を低下させることなく半導体チップと回路基板間のギャップを保持することができるので、フリップチップ実装の低コスト化を図り且つ信頼性を向上させる上で有益である。
【図面の簡単な説明】
【図１】 本発明の実施例を説明する図(その１) 。
【図２】 本発明の実施例を説明する図(その２)。
【図３】 本発明の実施例を説明する平面図。
【図４】 従来例を説明する断面図(その１) 。
【図５】 従来例を説明する断面図(その２) 。
【図６】 従来例の問題点を説明する断面図。
【符号の説明】
１ 半導体チップ
２ バンプ
３ 回路基板
４ 電極パターン[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for mounting a semiconductor chip on a circuit board at a high density.
In recent years, with the spread of portable electronic devices such as mobile phones and digital cameras, the demand for miniaturization and cost reduction of electronic circuits used in them has become strict. In addition to the reduction in the number of components due to integration, there is a need for further progress in technology for high-density mounting of semiconductor chips on which circuit patterns are formed at low cost.
[0002]
[Prior art]
A flip chip method is known as a method of mounting a semiconductor chip on a circuit board at a high density. 4 (a) and 4 (b) are cross-sectional views for explaining a conventional flip chip method. In the figure, a large number of bumps 2 for external connection are formed on the surface of the semiconductor chip 1, and electrode patterns 4 are formed on the circuit board 3 at positions corresponding to the bumps 2 of the semiconductor chip 1. ing. When giving priority to cost reduction of electronic equipment, an organic resin such as glass epoxy is used as the circuit board 3.
[0003]
First, as shown in FIG. 4A, the surface of the semiconductor chip 1 on which the bumps 2 are formed is opposed to the surface of the circuit board 3 on which the electrode pattern 4 is formed. The bump 2 and the electrode pattern 4 are aligned by moving the chip 1 in the horizontal direction. At the time of alignment, the semiconductor chip 1 is moved in a direction in which the center of the bump 2 and the center of the electrode pattern 4 are aligned so that the contact area between the bump 2 and the electrode pattern 4 is as large as possible.
[0004]
Next, as shown in FIG. 4B, a downward load is applied to the semiconductor chip 1 to move it in the direction of the arrow and press it against the circuit board 3. In addition to the downward load, heating and application of ultrasonic waves to the semiconductor chip 1 are performed as necessary. As a result, the bump 2 is connected to the electrode pattern 4. Then, the connection between the bump 2 and the electrode pattern 4 is stabilized by covering the vicinity of the connection region between the bump 2 and the electrode pattern 4 with a resin and then curing by heating.
[0005]
As described above, since the flip chip method can connect a large number of bumps to the electrode pattern at a time, it can be mounted with fewer man-hours than the wire bonding method, and the parasitic inductance at the connection point can be reduced. Is widely used.
As bumps formed on the semiconductor chip, stud bumps or plated bumps are used. The stud bump is formed by performing wire bonding using a wire made of gold or a gold alloy on an electrode pad on a semiconductor chip and then tearing the wire while heating. This is mainly used when the number of bumps formed on the same semiconductor chip is small or when the pitch between bumps is relatively large. Also, the plating bumps are formed by forming a resist opening pattern on the electrode pad and filling the opening with a plating material to form bumps, and the bump diameter can be determined by patterning, so it is finer than stud bumps. It is mainly used when the number of bumps is large or the pitch between bumps is small.
[0006]
In addition, attempts have been made to further reduce the cost of the mounting process by simplifying the flip chip method described above (see, for example, Patent Document 1). 5 (a) and 5 (b) are cross-sectional views illustrating a conventional simplified flip chip method. As shown in FIG. 5A, a thermosetting resin 5 is applied in advance so as to cover the electrode pattern 4 on the circuit board 3, and the surface of the circuit board 3 and the surface of the semiconductor chip 1 are made to face each other in this state. The electrode pattern 4 and the bump 2 are aligned as in the example described in FIG. Then, as shown in FIG. 5B, when a downward load is applied to the semiconductor chip 1 and pressed against the circuit board 3, the bump 2 pushes away the thermosetting resin 5 and is connected to the electrode pattern 4. become. Thereafter, the connection between the bump 2 and the electrode pattern 4 is stabilized by heat curing the resin.
[0007]
[Patent Document 1]
Japanese Patent Laid-Open No. 9-97816 (page 4-5, FIG. 2)
[0008]
[Problems to be solved by the invention]
The flip chip method described above has an advantage that a semiconductor chip having a large number of bumps can be mounted with a small number of man-hours, but the following is the case when a soft resin is used as a circuit board material. Problems arise.
FIG. 6 is a cross-sectional view for explaining the problems of the conventional flip chip method. When a downward load is applied to the semiconductor chip 1 and pressed against the circuit board 3, local stress occurs in the circuit board 3 due to the stress at the time of pressing, and the bump 2 sinks into the circuit board 3. The gap between the circuit boards 3 is narrowed. As a result, the surface of the semiconductor chip 1 may be in direct contact with the electrode pattern 4 as shown in FIG. This causes damage to the circuit pattern formed on the surface of the semiconductor chip 1. Further, as described above, when the gap between the semiconductor chip 1 and the circuit board 3 is narrowed, the fluidity of the resin in the gap is lowered, so that the gas contained in the resin is not sufficiently discharged during the heat curing. Voids remain in the resin in the gap. Or even if it covers with resin after flip chip connection, since the quantity of resin with which a gap is filled decreases, the connection strength of a bump and an electrode pattern falls. All of these phenomena cause a decrease in the reliability of the flip chip system.
[0009]
In maintaining the gap between the semiconductor chip and the substrate during flip chip mounting, (1) a method of reducing the downward load applied to the semiconductor chip to suppress the deflection of the circuit board, and (2) the semiconductor chip in advance. A method of forming a tall bump, and (3) a method of using hard quartz glass or the like instead of a glass epoxy resin that is easily bent as a material of a circuit board are conceivable. However, in the method (1), the contact between the bump and the electrode pattern is insufficient, and there is a possibility that the connection strength is lowered. In addition, when using stud bumps in the method of (2), it is difficult to make the bump diameter larger than the wire diameter, so it is difficult to form a tall bump when the wire diameter is reduced by miniaturization of the bump, When plating bumps are used, it is necessary to make the plating thicker, resulting in higher costs. Further, the method (3) has a problem that the substrate cost increases.
[0010]
SUMMARY OF THE INVENTION Accordingly, the present invention has an object to improve the reliability of flip chip connection by maintaining a gap between the semiconductor chip and the circuit board by a low-cost and simple method when the semiconductor chip is flip-chip connected to the circuit board. .
[0011]
[Means for Solving the Problems]
The present invention for solving the above problems, a semiconductor chip formed of a plurality of bumps, in the manufacturing method of a semiconductor device to be connected by face-down bonding the formed circuit board electrode pattern corresponding to the bumps, each said The bumps and the electrode patterns are located within a range in which the bumps and the electrode patterns partially overlap each other when viewed from above in a state where the semiconductor chip and the circuit board are spaced apart from each other so that the electrode patterns face each other. the center and the center of each said electrode pattern aligned shifted horizontally, then by moving the semiconductor chip downwardly pressed against the circuit board is brought into contact with each said bump and each said electrode patterns, then, the semiconductor chip, is moved horizontally toward the direction in which the center and the center of each said electrode pattern of each said bump is matched, each on a side surface of each said electrode pattern By pressing the bump, to connect each said bump while causing plastic deformation in each said bump to each said electrode pattern.
[0012]
In the above configuration, the semiconductor chip is moved obliquely downward in a direction in which the center of the bump and the center of the electrode pattern coincide.
In the above configuration, the semiconductor chip is moved while applying an ultrasonic wave in a direction in which the center of the bump and the center of the electrode pattern coincide.
Further, in the above configuration, the vibration direction of the ultrasonic wave is set to a direction perpendicular to the moving direction of the semiconductor chip.
[0013]
In the above configuration, the bump is connected to the electrode pattern in a state where a resin is previously interposed between the semiconductor chip and the circuit board.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
1 (a) to 1 (c) are diagrams for explaining an embodiment of the present invention. On the left side of each figure, there is a cross-sectional view taken along line AA when the semiconductor chip 1 is arranged facing a circuit board 3 made of glass epoxy. It is shown. Bumps 2 made of gold or a gold alloy are formed on the surface of the semiconductor chip 1, and electrode patterns 4 made of gold-plated copper are formed on the surface of the circuit board 3, respectively. Further, on the right side of each figure, a plan view showing the arrangement positions of the bumps 2 and the electrode patterns 4 when viewed from above is shown.
[0015]
First, as seen in FIG. 1 (a), the semiconductor chip 1 and the circuit board 3 are spaced apart from each other so that the bump 2 and the electrode pattern 4 face each other, and in this state, the bump 2 and the electrode pattern 4 are viewed from above. In the range where the two overlap, the centers of the bump 2 and the electrode pattern 4 are shifted in the horizontal direction and aligned. Next, as shown in FIG. 1B, a downward load is applied to the semiconductor chip 1 to move it downward and press it against the circuit board 3. Since the centers of the bump 2 and the electrode pattern 4 are shifted, the contact area between the bump 2 and the electrode pattern 4 at the time of pressing is small, and as a result, the stress applied to the circuit board 3 is small. Therefore, the deflection of the circuit board 3 is reduced, and the gap between the semiconductor chip 1 and the circuit board 3 can be widened as compared with the conventional case.
[0016]
Next, as indicated by an arrow 6 in FIG. 1C, the semiconductor chip 1 is moved in the horizontal direction in a direction in which the center of the bump 2 and the center of the electrode pattern 4 coincide. As a result, the bump 2 presses the side surface of the electrode pattern 4 and plastically deforms to increase the contact area with the electrode pattern 4 and connect to the electrode pattern 4. In this step, since the stress from above is hardly applied to the circuit board 3, the deflection of the circuit board 3 does not increase.
[0017]
When the bump 2 and the electrode pattern 4 are connected, one or both of the semiconductor chip 1 and the circuit board 3 are heated so that the plastic deformation of the bump 2 is facilitated and the connection strength between the bump 2 and the electrode pattern 4 is increased. Can be.
Furthermore, in order to further strengthen the connection strength between the bump and the electrode pattern, ultrasonic waves are applied to the semiconductor chip when the semiconductor chip is moved in the horizontal direction toward the direction in which the center of the bump and the center of the electrode pattern coincide. be able to. The amplitude of the ultrasonic vibration is usually set to about 0.2 μm to 2 μm. In a semiconductor chip having fine bumps with a diameter of about 15 μm, the vibration amplitude is not negligible with respect to the bump diameter, and the contact area between the bump and the electrode pattern may be greatly affected. This problem is that the vibration direction of ultrasonic vibration is set to a direction perpendicular to the moving direction 6 of the semiconductor chip as shown by an arrow 7 in FIG. Can be avoided.
[0018]
Next, FIGS. 2A to 2C are diagrams for explaining modifications of the above-described embodiment, and the same components as those in FIG. 1 are denoted by the same reference numerals. First, as shown in FIG. 2 (a), the semiconductor chip 1 and the circuit board 3 are spaced apart from each other so that the bump 2 and the electrode pattern 4 face each other. In this state, the bump 2 and the electrode pattern 4 are viewed from above. In the range where the two overlap, the centers of the bump 2 and the electrode pattern 4 are shifted in the horizontal direction and aligned. Next, as shown in FIG. 2B, a downward load is applied to the semiconductor chip 1 to move it downward and press it against the circuit board 3. Next, the contact area between the bump 2 and the electrode pattern 4 is increased by moving the semiconductor chip 1 obliquely downward in a direction in which the center of the bump 2 and the center of the electrode pattern 4 coincide with each other to cause plastic deformation of the bump 2. Then, the bump 2 and the electrode pattern 4 are connected. As a result, the same effect as in the previous embodiment can be obtained. As in the previous embodiment, the connection strength can be further strengthened in this embodiment by performing heat treatment, ultrasonic treatment, or both.
[0019]
In any of the above-described embodiments, the direction in which the semiconductor chip is moved in the horizontal plane is set to a different direction according to the bump arrangement of the semiconductor chip as follows.
FIG. 3 is a plan view showing a state in which the semiconductor chip 1 and the circuit board 3 are opposed to each other. A part of the bump 2 and the electrode pattern 4 is shown as seen through the semiconductor chip 1 when viewed from above.
[0020]
FIG. 3 (a) shows a case where bumps 2 are arranged on two sides of the semiconductor chip 1, and by moving the semiconductor chip 1 in the direction of the arrow shown in the figure, the electrode patterns corresponding to the centers of all the bumps are respectively shown. Can be close to the center of FIG. 3B shows a case where bumps 2 are arranged on four sides of the semiconductor chip 1, and the semiconductor chip 1 is moved obliquely upward as indicated by an arrow in the figure to correspond to the centers of all the bumps. It can be brought closer to the center of the electrode pattern.
[0021]
【The invention's effect】
As described above, according to the present invention, since the gap between the semiconductor chip and the circuit board can be maintained without lowering the connection strength between the bump and the electrode pattern in flip chip mounting, the cost of flip chip mounting can be reduced. This is useful for improving reliability and improving reliability.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an embodiment of the present invention (part 1);
FIG. 2 is a diagram for explaining an embodiment of the present invention (part 2);
FIG. 3 is a plan view illustrating an embodiment of the present invention.
FIG. 4 is a cross-sectional view for explaining a conventional example (part 1).
FIG. 5 is a sectional view for explaining a conventional example (part 2).
FIG. 6 is a cross-sectional view illustrating a problem of a conventional example.
[Explanation of symbols]
1 Semiconductor chip 2 Bump 3 Circuit board 4 Electrode pattern

Claims (4)

複数のバンプの形成された半導体チップを、各バンプに対応した電極パターンの形成された回路基板にフェイスダウンボンディングにより接続する半導体装置の製造方法において、
各該バンプと各該電極パターンが向かい合うように該半導体チップと該回路基板を離間して対向させた状態で、上方から見て各該バンプと各該電極パターンが部分的に重なる範囲内で各該バンプの中心と各該電極パターンの中心を水平方向にずらして位置合わせし、
ついで、該半導体チップを下方向に移動させて該回路基板に押圧し、各該バンプと各該電極パターンを接触させ、
ついで、該半導体チップを、各該バンプの中心と各該電極パターンの中心が一致する方向へ向けて水平に移動させて、各該電極パターンの側面に各該バンプを押圧することにより、各該バンプに塑性変形を生じさせながら各該バンプを各該電極パターンに接続することを特徴とする半導体装置の製造方法。 In a semiconductor device manufacturing method of connecting a semiconductor chip formed with a plurality of bumps to a circuit board on which an electrode pattern corresponding to each bump is formed by face-down bonding,
In a state where each of the bumps and the respective said electrode pattern are opposed spaced apart the semiconductor chip and the circuit board so as to face each in each said bump and each said electrode pattern as viewed from above in a range partially overlap The center of the bump and the center of each electrode pattern are shifted and aligned in the horizontal direction,
Then, by moving the semiconductor chip in a downward direction to press the circuit board is brought into contact with each said bump and each said electrode patterns,
Then, the semiconductor chip, by the center is moved horizontally toward the matching direction of the center and each of the electrode pattern of each said bump to press each said bump on the side surface of each of the electrode patterns, each said the method of manufacturing a semiconductor device characterized by connecting each said bump while causing plastic deformation to the bump on each said electrode pattern. 該半導体チップを、各該バンプの中心と各該電極パターンの中心が一致する方向へ向けて超音波を印加しつつ移動させることを特徴とする請求項１に記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip is moved while applying an ultrasonic wave in a direction in which the center of each bump and the center of each electrode pattern coincide with each other. 該超音波の振動方向を、該半導体チップの移動方向に対し垂直な方向にすることを特徴とする請求項２記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 2, wherein the vibration direction of the ultrasonic wave is set to a direction perpendicular to the moving direction of the semiconductor chip. 該半導体チップと該回路基板間に予め樹脂を介在させた状態で、該バンプを該電極パターンに接続することを特徴とする請求項１乃至３のいずれかに記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the bump is connected to the electrode pattern in a state where a resin is previously interposed between the semiconductor chip and the circuit board.
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JP2010118534A (en) * 2008-11-13 2010-05-27 Mitsubishi Electric Corp Semiconductor device and method of manufacturing same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465572A (en) * 2013-09-12 2015-03-25 日月光半导体制造股份有限公司 Packaging structure
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