JP4774248B2 - 半導体装置 - Google Patents
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Description
本発明の他の半導体装置は、電極パッド及びアナログ回路を含む回路ブロックが形成された第1の表面を有する半導体基板と、前記アナログ回路が形成された領域上を覆うように、互いに所定の間隔をあけて配置され、かつ、互いに電気的に接続された複数の帯状の金属薄膜を含むシールド層と、前記シールド層を挟んで前記第1の表面と接着され、前記シールド層を含む前記半導体基板の前記第1の表面を覆う保護層と、前記半導体基板の前記第1の表面側に設けられた前記電極パッドに電気的に接続された外部端子と、を備えている。そして、前記シールド層の前記金属薄膜の幅は180μm以下であり、かつ前記シールド層を構成する前記複数の帯状の金属薄膜の間隔は10〜50μmであることを特徴としている。
この半導体装置は、通常のCSPの製造方法と同じ工程で製造することができる。
この半導体装置は、搭載基板に形成された配線に、半田ボール40を接合することにより、フリップチップ実装して使用される。このとき、シールド部22が接続されたポスト25を、接地電位や電源電位に接続することにより、外部やディジタル回路からのノイズを有効に遮蔽することができる。
(1) 各種の寸法は一例であり、例示した値に限定するものではない。但し、再配線21の線幅と、シールド部22を構成する櫛状の歯の幅は、同一寸法に設定することがパターン設計上及び品質管理上有効である。また、その線幅は、密着性の観点から180μm以下であることが望ましい。
(2) 電源や接地等の再配線21で大きな電流が流れる箇所では、180μm以上の配線幅が必要になる。このような箇所では、例えば配線幅180μm毎に10μm程度のスリットを入れることにより、封止樹脂30との間の密着性を保持することができる。
11 電極パッド
12 アナログ回路
13 パッシベーション膜
15 保護層
21 再配線
22 シールド部
25 ポスト
30 封止樹脂
40 半田ボール
Claims (9)
- 外周部に複数の電極パッドが形成され、内側の回路形成面にアナログ回路を含む回路ブロックが形成されたシリコン基板と、
前記シリコン基板の表面に形成された絶縁層と、
前記絶縁層の表面に形成され、前記電極パッドから外部接続用の所定位置まで電気的接続を行う金属薄膜による複数の再配線と、
前記絶縁層の表面で前記アナログ回路が形成された領域上を覆うように、複数の帯状の金属薄膜を所定の間隔をあけて平行に配置し、これらの帯状の金属薄膜の端部または中央部を接続してその一端を前記外部接続用の所定位置まで延長したシールド部と、
前記外部接続用の所定位置に形成されて前記再配線及び前記シールド部を外部に電気的かつ機械的に接続するための金属ポストと、
前記シールド部を挟んで前記絶縁層と接着され、前記金属ポストの先端を露出し、前記金属ポストの側面と前記絶縁層、前記再配線及び前記シールド部を封止する封止樹脂と、
を備えた半導体装置であって、
前記再配線と前記シールド部の前記金属薄膜の幅は180μm以下であり、かつ前記シールド部を構成する前記複数の帯状の金属薄膜の間隔は10〜50μmであることを特徴とする半導体装置。 - 前記再配線と前記シールド部の金属薄膜は、同一工程で製造したことを特徴とする請求項1記載の半導体装置。
- 電極パッド及びアナログ回路を含む回路ブロックが形成された第1の表面を有する半導体基板と、
前記アナログ回路が形成された領域上を覆うように、互いに所定の間隔をあけて配置され、かつ、互いに電気的に接続された複数の帯状の金属薄膜を含むシールド層と、
前記シールド層を挟んで前記第1の表面と接着され、前記シールド層を含む前記半導体基板の前記第1の表面を覆う保護層と、
前記半導体基板の前記第1の表面側に設けられた前記電極パッドに電気的に接続された外部端子と、
を備えた半導体装置であって、
前記シールド層の前記金属薄膜の幅は180μm以下であり、かつ前記シールド層を構成する前記複数の帯状の金属薄膜の間隔は10〜50μmであることを特徴とする半導体装置。 - 前記保護層は、樹脂であることを特徴とする請求項3記載の半導体装置。
- 前記電極パッドと前記外部端子の間は、前記半導体基板の前記第1の表面側に形成された再配線層を介して接続されていることを特徴とする請求項3または4記載の半導体装置。
- 前記シールド層を構成する前記複数の帯状の金属薄膜は、互いに平行に配置されていることを特徴とする請求項3〜5のいずれか1項に記載の半導体装置。
- 前記シールド層は、接地電位に接続されることを特徴とする請求項3〜6のいずれか1項に記載の半導体装置。
- 前記シールド層は、前記再配線層と同じ材料で形成されていることを特徴とする請求項5〜7のいずれか1項に記載の半導体装置。
- 前記シールド層を構成する前記複数の帯状の金属薄膜は、互いに等間隔に配置されていることを特徴とする請求項6〜8のいずれか1項に記載の半導体装置。
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JP2005212442A JP4774248B2 (ja) | 2005-07-22 | 2005-07-22 | 半導体装置 |
US11/488,190 US7479690B2 (en) | 2005-07-22 | 2006-07-18 | Semiconductor device |
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JP2005212442A JP4774248B2 (ja) | 2005-07-22 | 2005-07-22 | 半導体装置 |
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US6642136B1 (en) | 2001-09-17 | 2003-11-04 | Megic Corporation | Method of making a low fabrication cost, high performance, high reliability chip scale package |
TWI313507B (en) | 2002-10-25 | 2009-08-11 | Megica Corporatio | Method for assembling chips |
US6818545B2 (en) * | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US7902679B2 (en) * | 2001-03-05 | 2011-03-08 | Megica Corporation | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump |
US7099293B2 (en) * | 2002-05-01 | 2006-08-29 | Stmicroelectronics, Inc. | Buffer-less de-skewing for symbol combination in a CDMA demodulator |
TWI245402B (en) * | 2002-01-07 | 2005-12-11 | Megic Corp | Rod soldering structure and manufacturing process thereof |
US7394161B2 (en) * | 2003-12-08 | 2008-07-01 | Megica Corporation | Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto |
US8294279B2 (en) * | 2005-01-25 | 2012-10-23 | Megica Corporation | Chip package with dam bar restricting flow of underfill |
JP5430848B2 (ja) * | 2007-12-21 | 2014-03-05 | ラピスセミコンダクタ株式会社 | 半導体素子、半導体装置、及びそれらの製造方法 |
US7952187B2 (en) * | 2008-03-31 | 2011-05-31 | General Electric Company | System and method of forming a wafer scale package |
JP2010062170A (ja) | 2008-09-01 | 2010-03-18 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP5370217B2 (ja) * | 2010-03-04 | 2013-12-18 | カシオ計算機株式会社 | 半導体装置及び半導体装置の製造方法 |
CN110372086B (zh) | 2013-10-22 | 2022-12-06 | 那沃达有限责任公司 | 使用天然产生的生物生长培养基减少被污染流体中的物质 |
US10163661B2 (en) * | 2015-06-30 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor devices and methods of forming same |
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JP2767843B2 (ja) * | 1988-12-15 | 1998-06-18 | 日本電気株式会社 | アナログ・ディジタル混在集積回路 |
JP3287346B2 (ja) * | 1999-11-29 | 2002-06-04 | カシオ計算機株式会社 | 半導体装置 |
JP3792635B2 (ja) * | 2001-12-14 | 2006-07-05 | 富士通株式会社 | 電子装置 |
JP2004031790A (ja) * | 2002-06-27 | 2004-01-29 | Hitachi Maxell Ltd | 半導体チップ |
JP2004214561A (ja) * | 2003-01-08 | 2004-07-29 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP3973624B2 (ja) * | 2003-12-24 | 2007-09-12 | 富士通株式会社 | 高周波デバイス |
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2005
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US7479690B2 (en) | 2009-01-20 |
JP2007035686A (ja) | 2007-02-08 |
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