JP4767856B2 - 電界効果トランジスタの製造方法 - Google Patents
電界効果トランジスタの製造方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/464—Lateral top-gate IGFETs comprising only a single gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Crystallography & Structural Chemistry (AREA)
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- Manufacturing & Machinery (AREA)
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- Theoretical Computer Science (AREA)
- Thin Film Transistor (AREA)
Description
以下、本発明のFETの例について説明する。図1A〜図1Dは、本発明のFETの代表的な例を模式的に示す断面図である。図1A〜Dに示すように、本発明のFETには様々な構成が存在する。図1A〜図1DのFET100a〜100dは、基板11、ゲート電極12、ゲート絶縁層13、半導体層14、ソース電極15、およびドレイン電極16を備える。半導体層14の一部はチャネル領域として機能する。ソース電極15およびドレイン電極16は、通常、半導体層14に直接接触しているが、両者の界面に、接続抵抗を低減するための層などが配置されていてもよい。
以下に、図1BのFET100bの製造方法の一例について説明する。まず、ポリエチレンテレフタレート(PET)からなる基板11(厚みがたとえば100μm)上に、マスク蒸着によってNiからなるゲート電極12(厚みがたとえば100nm)を形成する。次に、ポリビニルアルコールの水溶液をスピンコート法によって塗布したのち乾燥させ、ゲート絶縁層13(厚みがたとえば500nm)を形成する。次に、ゲート絶縁層13上に、マスク蒸着によって、Auからなるソース電極15およびドレイン電極16(それぞれ厚みがたとえば100nm)を形成する。
以下に、図1DのFET100dの製造方法の一例について説明する。まず、シリコン基板の表面に酸化シリコン層を形成したのち、ソース電極およびドレイン電極を形成する。これらの電極は、たとえばチタンで形成できる。これらの電極は、たとえば、スパッタリングで金属膜を成膜した後、フォトリソ・エッチング工程でパターニングすることによって形成できる。
FET100dと同様のFETを製造する方法の一例を、図4A〜図4Hを用いて説明する。図4A、4C、4Eおよび4Gは上面図であり、それらの断面図を図4B、4D、4Fおよび4Hに示す。
以下に、図1DのFET100dの製造方法について他の一例を説明する。まず、図5Aに示すように、基板11の表面にソース電極15およびドレイン電極16を形成する。これらの電極は、第2の製造方法と同様の方法で形成する。
実施形態2では、実施形態1で説明した本発明のFETを備える電子機器の例として、アクティブマトリクス型ディスプレイ、無線IDタグ、および携行用機器について説明する。
Claims (1)
- 基板と、前記基板上に形成された半導体層と、前記半導体層に電気的に接続されたソース電極およびドレイン電極とを備える電界効果トランジスタの製造方法であって、
(i)無機半導体からなる複数の細線を前記基板上に成長させる工程と、
(ii)前記ソース電極と前記ドレイン電極とを結ぶ方向に前記細線を倒す工程と、
(iii)倒された前記細線からなる膜に有機半導体材料を浸透させる工程とを含む電界効果トランジスタの製造方法。
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JP2006532695A JP4767856B2 (ja) | 2004-08-31 | 2005-08-30 | 電界効果トランジスタの製造方法 |
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JP2004251453 | 2004-08-31 | ||
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PCT/JP2005/015705 WO2006025353A1 (ja) | 2004-08-31 | 2005-08-30 | 電界効果トランジスタおよびその製造方法、ならびにそれを用いた電子機器 |
JP2006532695A JP4767856B2 (ja) | 2004-08-31 | 2005-08-30 | 電界効果トランジスタの製造方法 |
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JPWO2006025353A1 JPWO2006025353A1 (ja) | 2008-05-08 |
JP4767856B2 true JP4767856B2 (ja) | 2011-09-07 |
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JP2006532695A Expired - Fee Related JP4767856B2 (ja) | 2004-08-31 | 2005-08-30 | 電界効果トランジスタの製造方法 |
Country Status (5)
Country | Link |
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US (1) | US20080035912A1 (ja) |
JP (1) | JP4767856B2 (ja) |
KR (1) | KR20070053157A (ja) |
CN (1) | CN1950950A (ja) |
WO (1) | WO2006025353A1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2007329351A (ja) * | 2006-06-08 | 2007-12-20 | Sharp Corp | 細線状構造物集合体およびそれを備えた電子デバイス、それらの製造方法、および細線状構造物の配向方法 |
JP2008010566A (ja) * | 2006-06-28 | 2008-01-17 | Ricoh Co Ltd | 半導体デバイス |
JP5273050B2 (ja) * | 2007-09-07 | 2013-08-28 | 日本電気株式会社 | スイッチング素子及びその製造方法 |
JP5333221B2 (ja) * | 2007-09-07 | 2013-11-06 | 日本電気株式会社 | カーボンナノチューブ構造物及び薄膜トランジスタ |
CN103236442B (zh) * | 2013-04-23 | 2016-12-28 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制造方法、阵列基板、电子装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2004067413A (ja) * | 2002-08-02 | 2004-03-04 | Nec Corp | 触媒担持基板およびそれを用いたカーボンナノチューブの成長方法ならびにカーボンナノチューブを用いたトランジスタ |
JP2004088090A (ja) * | 2002-07-02 | 2004-03-18 | Sony Corp | 半導体装置及びその製造方法 |
JP2004111870A (ja) * | 2002-09-20 | 2004-04-08 | Kenji Ishida | 半導体装置およびその製造方法 |
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US6108956A (en) * | 1998-04-03 | 2000-08-29 | Cormark, Inc. | Tri-mount sign system |
US6180956B1 (en) * | 1999-03-03 | 2001-01-30 | International Business Machine Corp. | Thin film transistors with organic-inorganic hybrid materials as semiconducting channels |
US7067867B2 (en) * | 2002-09-30 | 2006-06-27 | Nanosys, Inc. | Large-area nonenabled macroelectronic substrates and uses therefor |
-
2005
- 2005-08-30 JP JP2006532695A patent/JP4767856B2/ja not_active Expired - Fee Related
- 2005-08-30 US US10/599,658 patent/US20080035912A1/en not_active Abandoned
- 2005-08-30 KR KR1020067020125A patent/KR20070053157A/ko not_active Application Discontinuation
- 2005-08-30 WO PCT/JP2005/015705 patent/WO2006025353A1/ja active Application Filing
- 2005-08-30 CN CNA2005800140580A patent/CN1950950A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004088090A (ja) * | 2002-07-02 | 2004-03-18 | Sony Corp | 半導体装置及びその製造方法 |
JP2004067413A (ja) * | 2002-08-02 | 2004-03-04 | Nec Corp | 触媒担持基板およびそれを用いたカーボンナノチューブの成長方法ならびにカーボンナノチューブを用いたトランジスタ |
JP2004111870A (ja) * | 2002-09-20 | 2004-04-08 | Kenji Ishida | 半導体装置およびその製造方法 |
Also Published As
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US20080035912A1 (en) | 2008-02-14 |
CN1950950A (zh) | 2007-04-18 |
JPWO2006025353A1 (ja) | 2008-05-08 |
KR20070053157A (ko) | 2007-05-23 |
WO2006025353A1 (ja) | 2006-03-09 |
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