JP4764517B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine that includes a computer circuit, and more particularly to a gaming machine that can effectively eliminate fraudulent games.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a profit state advantageous to the player. However, in actuality, whether or not the big hit state is determined in advance by the big hit lottery process executed at the time of winning the game ball, and the symbol display unit performs a symbol variation operation exclusively to enliven the player Yes.

  In the big win lottery process, the counter variable CT updated every predetermined time is used, and the value of the counter variable CT (random value RND) acquired at the time of winning the game ball is compared with the winning value Hit to determine whether or not the big win state. Is decided. The counter variable CT is initialized to zero when the entire area of the RAM is zero-cleared (RAM clear processing) after the power is turned on. -1) is cycled.

JP 2003-033532 A Japanese Patent Laid-Open No. 2003-205161

  By the way, the above update rules for the winning value Hit and the counter variable CT can be found by obtaining a ball game machine and analyzing the control program. Therefore, it is relatively easy to intentionally generate a winning state by using an improper instrument if it is immediately after turning on the power and is the first cycle of a circulating operation within a predetermined numerical range. Therefore, for example, there is a concern about illegal acts that repeatedly generate a big hit state by using a powerful electromagnetic wave to run the program and misusing the forced reset of the CPU by the watchdog timer.

  In addition, Patent Document 1 and Patent Document 2 propose that a liquid crystal display informs that the RAM has been cleared to zero, but in the first place, due to such countermeasures, even if the RAM is cleared to zero, the illegal game succeeds. Measures that do not allow it are more effective.

  The present invention has been made based on the above idea, and an object of the present invention is to provide a gaming machine that does not succeed in illegal gaming when the RAM is cleared to zero.

In order to achieve the above object, the present invention provides a second counter that circulates a predetermined numerical range to generate a random number lottery value, and a first counter that defines an initial value of a cyclic operation of the second counter, In a lottery process resulting from a player's operation or a game medium operation, a gaming machine that determines whether or not to generate a profitable state advantageous to the player based on a random number lottery value,
CPU is activated when Ru is reset, the main process including a first updating process that updates a value of the first counter in an infinite loop, is activated and receives an interrupt signal, the value of the second counter at predetermined time intervals An interrupt process including a second update process for repeatedly updating, and a gaming operation is controlled,
There are first and second switches that define whether or not to allow lottery processing,
When the storage area of the memory is initially set in the main process, the second counter makes a round of the predetermined numerical range without executing the lottery process, and the initial value of the subsequent cyclic operation is On the condition that it is changed based on the value, the ON state of the first and second switches is determined,
If the first switch is in the ON state, the subsequent lottery process is permitted regardless of the OFF state of the second switch .

  According to the present invention described above, for example, even if the RAM can be intentionally cleared to zero, the subsequent illegal game cannot be succeeded.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated in detail the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. The circuit configuration of the main control unit is illustrated. It is a flowchart explaining the system reset process of a main control part. It is a flowchart explaining the monitoring interruption process of a main control part. It is a flowchart explaining the original timer interruption process of a main control part. It is a flowchart explaining the backup process of a main control part.

  Hereinafter, the present invention will be described in detail based on a ball game machine according to an embodiment. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be freely opened and closed.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 3. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

As shown in FIG. 2, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display DISP is provided at the approximate center of the game area 5a inside. Has been placed. In addition, at a suitable place in the game area 5a, a symbol starting port 15, a big winning port 16, a plurality of normal winning ports 17 (four on the right and left sides of the big winning port 16), and a gate 18 serving as two passing ports are arranged. Has been. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The liquid crystal display DISP is a device that variably displays a specific symbol related to a big hit state and displays a background image and various characters in an animated manner. This liquid crystal display DISP has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. The special symbol display portions Da to Dc execute a reach effect that expects a big hit state to be invited, and the special symbol display portions Da to Dc and the surroundings perform a notice effect that informs the result of the determination indefinitely. The

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

  For example, the symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a. When the stop symbol after the fluctuation of the normal symbol display unit 19 displays a winning symbol, the symbol start port 15 is opened and closed. The claw 15a is opened for a predetermined time.

  On the other hand, when a game ball wins at the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time, and are determined based on the lottery result corresponding to the winning timing of the game ball at the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 16a is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, a privilege that the game after the end of the special game is in a high probability state is given.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. Broken lines in the figure mainly indicate DC voltage lines.

  As shown in the figure, this pachinko machine GM includes a power supply board 20 that receives 24V AC and outputs various DC voltages and a system reset signal, a main control board 21 that plays a central role in game control operations, and a main control board 21. An effect control board 22 that executes a lamp effect and an audio effect based on the received control command CMD, an effect interface board 23 that transmits a signal received from the effect control board 22 to each part, and an effect interface board 23 A liquid crystal control board 24 for driving the liquid crystal display DISP based on the control command CMD ′, and a payout control board 25 for controlling the payout motor M based on the control command CMD ″ received from the main control board 21 to pay out the game ball; A launch control board 26 that launches a game ball in response to a player's operation is mainly configured.

Here, the main control board 21, the effect control board 22, the liquid crystal control board 24, and the payout control board 25 are each mounted with a computer circuit including a one-chip microcomputer. Therefore, in this specification, the main control board 21, the production control board 22, the liquid crystal control board 24, the circuits mounted on the payout control board 25, and the operations realized by the circuits are collectively referred to as functions. The control unit 21, the production control unit 22, the liquid crystal control unit 24, and the payout control unit 25 may be referred to. All or part of the effect control unit 22, the liquid crystal control unit 24, and the payout control unit 25 are sub-control units.

  As shown in the figure, the main control unit 21 is connected to the command relay board 29 and is connected to each game component of the game board 5 via the game board relay board 27. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. Note that the switch signal from the symbol start port 15 is received directly by the main control unit 21 without going through the game board relay board 27. In this embodiment, clerk switches SW1 and SW2 for preventing unauthorized gaming are provided, and each switch signal is also supplied to the main controller 21.

  The main control unit 21 transmits a control command CMD ″ to the payout control unit 25 in one direction, while the payout control unit 25 receives a prize ball count signal indicating a game ball payout operation and a payout operation. The status signal CON related to the abnormality is received, and the status signal CON includes, for example, a replenishment out signal, a payout shortage error signal, and a lower plate full signal.

  Further, the payout control unit 25 outputs an AC voltage AC24V and a launch control signal CTL to the launch control board 26. The launch control signal CTL is a condition for operating the launch motor M2. When the launch control signal CTL is at L level, the launch operation of the game ball is prohibited.

FIG. 4 illustrates a schematic configuration of the one-chip microcomputer of the main control unit 21. As shown in the figure, the one-chip microcomputer of the main control unit 21 includes a CPU core 21A equivalent to a Z80 CPU (Zilog), a CTC unit (Zilog Counter Timer Circuit equivalent) 21B,
The input port 21C receives switch signals from the staff switches SW1 and SW2, a memory 21D composed of RAM and ROM, and a watchdog timer 21E.

  The timer interrupt signal INT is set every 2 mS from the Z80CTC unit 21B to the Z80 CPU core 21A (ST2 in FIG. 5). In response to the timer interrupt signal INT, an 8-bit interrupt vector (lower) VL is set to be output (ST2).

  On the other hand, the Z80 CPU core 21A is set to operate in the interrupt mode of mode 2 corresponding to the setting of the CTC unit 21B (ST2). Then, the start address of the interrupt processing program to be executed at the time of interrupt processing is specified by the interrupt vector VL received from the CTC unit 21B and the interrupt vector (upper) VH specified by the I register inside the CPU core. It has become.

  FIG. 4B illustrates the relationship between the area of the address table TBL referenced by combining the lower interrupt vector VL and the upper interrupt vector VH, and the storage area of the interrupt processing program. In this embodiment, the reference position in the address table TBL is switched by appropriately rewriting the value of the I register. Even if the same interrupt signal INT is received, the monitoring interrupt processing is performed according to the value of the I register at that time. Either the program ER_INT or the original interrupt processing program TIMER_INT is executed. As will be described later, after the RAM clear processing (ST4 in FIG. 5), the monitoring interrupt processing program ER_INT is executed, and after confirming the switch signal (ST26 in FIG. 6), the original interrupt processing program TIMER_INT is Executed.

  5 to 8 are flowcharts showing a control program of the main control unit 21. The control program of the main control unit 21 includes a system reset process (FIG. 5) that is activated based on restoration or input of the power supply voltage, a timer interrupt process (FIGS. 6 and 7) that is activated every predetermined time, And a non-maskable highest priority interrupt process (FIG. 8) activated by a voltage drop signal from the substrate 20. As described above, in this embodiment, the timer interrupt process is composed of the monitoring interrupt ER_INT (FIG. 6) and the original timer interrupt (FIG. 7).

  Hereinafter, the system reset processing program (main processing) will be described with reference to FIG. The main process starts when the initialization switch (not shown) is turned off and the power is turned on, such as when recovering from a power outage, and when the game hall is opened. May be turned on to turn on the power. Note that, due to the runaway control program, the watchdog timer WDT may be activated and the CPU may be forcibly reset.

In any case, the Z80 CPU first sets itself to the interrupt disabled state (ST1), and initializes each part of the one-chip microcomputer including the Z80 CPU core (ST2). This initial setting includes (a) setting of interrupt mode 2 to the CPU, (b) setting of the original interrupt vector to the I register in the CPU, and (c) timer signal from the CTC unit 21B every 2 mS. Contains settings to output interrupt vectors.

  In Z80 CPU, 0, 1, and 2 can be used as interrupt modes. In interrupt mode 0, an interrupt processing program to be started is designated by software by an RST instruction. In interrupt mode 1, an interrupt signal INT is set. When received, the interrupt processing program after address 0038H is uniformly executed. On the other hand, in the interrupt mode 2, an arbitrary interrupt processing program can be executed depending on the value of the interrupt vector. Therefore, in the process of step ST2, an initial value (XXH) is set in the I register.

  When the initial setting (ST2) including the above processing is completed, the value of the RAM clear signal is determined (ST3). The RAM clear signal is a signal for determining whether or not to initialize all areas of the built-in RAM, and has a value corresponding to the ON / OFF state of the initialization switch operated by the staff.

  Here, it is assumed that the RAM clear signal by the attendant is in the OFF state. Note that the RAM clear signal is also OFF when the CPU is forcibly reset by the watchdog timer WDT or when recovering from a power failure state. In such a case, the content of the backup flag BFL is subsequently determined (ST4). The backup flag BFL is data indicating whether or not the backup data saved by the NMI interrupt processing of FIG. 8 has been restored to the original state. In this embodiment, the backup flag BFL is 5AH in the NMI interrupt processing. (ST56), and is cleared to zero in the process of step ST13 of FIG.

  When the power is turned on or when the power is restored from the power failure state, the content of the backup flag BFL is 5AH. However, if the program goes into a runaway state for some reason and a CPU reset operation is caused by the watchdog timer, the backup flag BFL = 00H. Therefore, when BFL ≠ 5AH (normally BFL = 00H), the process proceeds from step ST4 to step ST7 to return the operation of the gaming machine to the initial state. This is also an operation intended by an unauthorized player.

On the other hand, if the backup flag BFL = 5AH, a checksum operation for calculating a checksum value is executed (ST5). Here, the checksum operation is an 8-bit addition operation on the work area of the internal RAM (see FIG. 8C). When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the RAM (ST6).

  In the SUM address, the checksum value by the same checksum calculation is stored in the NMI interrupt process (FIG. 8) executed when the voltage drops. The stored calculation results are maintained by a backup power source together with other data in the built-in RAM. Therefore, the two should be matched by the determination in step ST6. However, if the checksum values do not match for some reason, the process proceeds to step ST7.

  In this way, not only when the RAM clear signal is in the ON state, but also when the backup flag BFL is 00H or when the checksum values do not match, the process proceeds to step ST7, and all of the RAM is The area data is cleared to zero (ST7). Therefore, the value of the jackpot lottery counter CT for jackpot lottery becomes zero as intended by the unauthorized player together with other data.

  However, in this embodiment, when the RAM area is cleared to zero, the value of the I register of the CPU is changed and rewritten to YYH (ST8), so that the illegal game does not succeed at all (this point will be described in detail later). Further, in accordance with the change of the I register value, the value of the monitoring timer variable TM is initialized, and the launching operation of the game ball on the launch control board 26 is prohibited (ST8). The monitoring timer variable TM is initially set to a time for which the big hit counter CT makes a complete round of its numerical range (0 to MAX-1).

  Specifically, the firing operation prohibiting process is executed by setting the firing control signal CTL from the dispensing control board 25 to the firing control board 26 to the L level by the control command COM "to the dispensing control board 25. As described above, in this embodiment, since the game ball launching operation is prohibited for a while after the RAM is cleared, there is no trouble that the game ball wins during execution of the monitoring interrupt processing program ER_INT. If the game ball launch operation is not prohibited, if the game ball wins during execution of the monitoring interrupt processing program ER_INT, the game machine does not respond at all, so it is suspicious to general legitimate players. It gives a feeling.

  In step ST8, a control command for displaying the fact of RAM clear is transmitted to the liquid crystal display DISP. Therefore, the fact that the gaming machine has returned to the initial state becomes known not only to the player of the gaming machine but also to the players around it.

  When the process of step ST8 is completed, the CPU is set to an interrupt enabled state by executing the EI instruction (ST9). Thereafter, the counter update process is executed in an infinite loop (ST10). The counter to be updated includes an initial value change counter BGN. The initial value change counter BGN is a counter that determines an initial value of a subsequent round operation when the jackpot counter CT updated in the random number generation process (ST31) makes a round of a predetermined numerical range. Therefore, the initial value change counter BGN circulates in the same numerical range (0 to MAX-1) as the big hit counter CT in an infinite loop.

By the way, in the determination of step ST6, if the checksum value obtained by the checksum calculation (ST5) matches the stored value at the SUM address, the RAM is not cleared and the 16 read from the SP storage area of the RAM is read. Bit data is written to the stack pointer SP of the CPU (ST11). Next, the POP instruction is executed to restore the values of the registers (BC, DE, HL) excluding the AF register from the RAM stack area (ST12). As a result of this processing, the return processing from the time of power-off is completed for the time being, so the backup flag BFL is cleared to zero to indicate that (ST13).

Next, the value of the interrupt permission flip-flop is returned to the P / V flag of the Z80 CPU by the POP AF instruction (ST14). As will be described later, in NMI processing, LDA, I
And the value of the interrupt permission flip-flop is set in the P / V flag, and then the PUSH AF instruction is executed. Therefore, it is possible to determine whether or not the interrupt voltage is permitted before the power supply voltage is lowered, based on the value of the P / V flag after execution of the POP AF instruction in step ST14.

  Therefore, based on the value of the P / V flag, it is checked whether or not the interruption of the power supply voltage was in the interrupt disabled state (ST15), and after returning the AF register from the stack area, the interrupt disabled state is maintained. Either the process is finished (ST17), or the process is returned to the interrupt enabled state and the return process is finished (ST16). Then, by executing the RET instruction in step ST18, the value of the PC (program counter) at the time of the interruption that has been PUSH processed in the stack area is restored, and the processing before power-off is resumed.

  In the flowchart shown in FIG. 5, since the value of the I register is initially set in the process of step ST2, the save value of the stack area is restored to the I register in the restoration process (ST11 to ST18). Absent. Therefore, if the interrupt signal INT is received after the return process (ST11 to ST18), the original timer interrupt process (FIG. 7) is always executed. Therefore, in the sense that thorough prevention of fraudulent games is taken into account such points, the instruction of LDI, A is executed following POP AF in the process of step ST14 (see parentheses), and the value of the I register is changed. It is effective to return to the value before power off. If such a configuration is adopted, even if the power is cut off during the execution of the monitoring interrupt processing program ER_INT, the processing of the monitoring interrupt processing program ER_INT can be resumed after the processing of step ST18.

  Next, a timer interrupt processing program that is started every 2 mS while interrupting the main processing of FIG. 5 will be described. First, the monitoring interrupt program ER_INT will be described with reference to FIG. Note that this monitoring interrupt program ER_INT is executed when the value of the I register is changed from XXH to YYH by the process of step ST8.

  In the monitoring interrupt program ER_INT, first, after the value of each register is saved in the stack area (ST21), the big hit counter CT is incremented and updated (ST22). The specific processing content is as shown in FIG. 6C, and the big hit counter CT is incremented within a numerical range of 0 to MAX-1 (ST61 to ST63). If the updated value of the big hit counter CT coincides with the initial value ST in a round operation within the numerical range, it is reset to the initial value change counter BGN, and thereafter, the reset initial value ST is reset. The one-round operation from is resumed (ST64 to ST65).

  When the big hit counter CT updating process (ST22) is finished, the value of the monitoring timer variable TM is checked next. If TM ≠ 0, the monitoring timer variable TM is decremented and the process is finished (ST24, ST28). ).

When such timer interrupt processing ER_INT is repeated, the monitoring timer variable TM eventually becomes zero. As described above, the monitoring timer variable TM is initially set to a time that the big hit counter CT makes a round of its numerical range (0 to MAX-1) with certainty. Therefore, at the stage where the monitoring timer variable TM becomes zero, the big hit counter CT has undergone the processing of step ST65 and is executing a cyclic operation starting from a sufficiently random initial value BGN.

  Therefore, after the monitoring timer variable TM becomes zero, the process proceeds to a process of monitoring the ON / OFF state of the staff switches SW1 and SE2 (ST25). If the determination result in step ST25 is OK, the value of the I register is set to the original value XXH (ST26), and the game ball launching operation is permitted (ST27).

  As a result, in the subsequent timer interrupt INT, the original timer interrupt processing TIMER_INT is started and normal game operation is started. As described above, in this embodiment, when the RAM is cleared, the gaming operation is not started at least until the value of the big hit counter CT goes through the numerical value range. However, the RAM is usually cleared only before the opening of the game hall, and the time during which the game operation is prohibited is 2 mS × MAX (usually about 2 × 300 mS), so there is no problem. Does not occur. Similarly, even if the CPU is reset due to a device trouble regardless of illegal activities during the game hall business hours, if the pre-permission switch SW1 described later is set to the ON state, Since the prohibition time (2 mS × MAX) is very small, it does not bother ordinary players.

  The configuration of the clerk switch determined in the process of step ST25 is appropriately determined. In this embodiment, a prior permission switch SW1 and an individual permission switch SW2 are provided. The prior permission switch SW1 is a switch for omitting individual operations by the staff, and is set to the ON state in the gaming machine in the initial state at the factory shipment stage.

As shown in FIG. 6B, if the prior permission switch SW1 is in the ON state, the determination in step ST25 is evaluated as OK regardless of the ON / OFF state of the individual permission switch SW2. This is because, even if the RAM is illegally cleared, (a) the timing at which the process of step ST25 is executed is after the round-robin counter CT has completed a cycle, and (b) the subsequent illegal game Because it is impossible, it is not always necessary to dispatch the staff to the scene.

  However, even in such a case, threats to an unauthorized player by sending an attendant to the scene are effective. Therefore, in a gaming hall where importance is placed on the threatening effect, it is only necessary to set the prior permission switch SW1 to the OFF state. In this case, the determination in step ST25 is performed unless the individual permission switch SW2 is turned on. Not evaluated as OK. Therefore, in the case of adopting such an embodiment, a process for notifying the hall computer that “RAM clear process has been executed” may be provided after the RAM clear process. Alternatively, or in addition to this, a control command is sent to the liquid crystal control board (ST8). For example, “The gaming machine has been reset to the initial state. Please display ".

  In game halls where the operation of such a gaming machine is selected, even if the CPU is reset due to a mere equipment trouble, it will cause a general player to wait for the game to start. Since it is extremely rare for the timer to start, virtually no problem arises.

  When the above operation is confirmed, in the monitoring interrupt process ER_INT, only the big hit counter CT is updated, and the big hit lottery process is not executed. Therefore, the prospect of the illegal player will not succeed. The initial value change counter BGN is repeatedly updated in the infinite loop process in the system reset process (ST10), and thus becomes a sufficiently random value. I can't know.

  Next, the original timer interrupt TIMER_INT shown in FIG. 7 will be described. If a timer interrupt occurs after the I register is rewritten by the process of step ST26, the contents of each register are saved in the stack area (ST30), and then a random number generation process is performed first (ST31). The random number generation processing includes update processing of the winning counter RG and the big hit counter CT used in the lottery operation in the normal symbol processing ST39 and the special symbol processing ST44. The update process of the big hit counter CT is as shown in FIG. 6C. Every time the numerical value range is made, the initial value ST of the subsequent cyclic operation is based on the value of the initial value change counter BGN. Randomly set.

  When such random number generation processing (ST31) ends, timer subtraction processing is performed for the timer that manages the time of each gaming operation (ST32). The timer to be subtracted here is mainly used for managing the opening time of the electric tulip and the special winning opening and other game effect times. At this time, a clear pulse is supplied to the watchdog timer WDT to prevent the CPU from being forcibly reset.

  Subsequently, ON / OFF signals of various switches including the winning detection switch of the symbol start opening 15 and the big winning opening 16 are inputted, and the ON / OFF signals are stored in the work area (ST33). If an unreasonable ON signal is detected, an illegal winning command is transmitted (ST34). The illegal winning command is transmitted, for example, when an ON signal is obtained from the detection switch of the special winning opening 16 even though the special game is not being performed.

  Next, error management processing is performed (ST35). The error management process is a determination as to whether or not an abnormality has occurred inside the device, such as whether or not the supply of game balls has stopped or the game balls are clogged. Next, after creating a control command for the payout control board (ST36), the control command generated in each of the above processes is transmitted to the corresponding sub-control board (ST37).

  Next, normal symbol processing is performed on the condition that the current operation mode is not the hit mode (ST39). The normal symbol processing means determination as to whether or not to operate an ordinary electric accessory such as an electric tulip. Specifically, when it is determined that the game ball is passing the gate based on the switch input result in step ST33, the winning counter RG updated in the random number generation process (ST31) is compared with the winning winning value. Done. If the comparison result is a winning state, the operation mode is changed to the winning operation mode. Also, if it is hit, processing for the operation of the ordinary electric accessory such as an electric tulip is performed (ST41).

  Subsequently, necessary control commands are transmitted to the corresponding sub-control board (ST42), and special symbol processing is performed on the condition that the current operation mode is not a big hit (ST44). The special symbol process is a determination as to whether or not to operate a special electric accessory such as the special prize opening 16. Specifically, when it is determined from the switch input result of step ST33 that the game ball has passed the symbol start port, the big hit counter CT updated in the random number generation process (ST31) is used as the big win winning value Hit. In contrast to. Then, if the comparison result is a winning state, the operation mode is changed to the big hit mode. If it is a big hit, processing for the operation of the first type special electric accessory such as a big prize opening is performed (ST46).

Thereafter, the control command generated in each of the above processes is transmitted to the corresponding sub control board. For example, when the special symbol process (ST44) is executed, regardless of the lottery result, the symbol variation operation is started in the liquid crystal display DISP when the control command is transmitted. In any case, when the process of step ST47 is finished, the register saved in the process of step ST30 is restored (ST48), and the interrupt process is finished. As a result, the routine usually returns from the interrupt processing routine to the infinite loop processing (ST7 in FIG. 4) of the main processing.

  FIG. 8A is a flowchart showing the contents of an NMI interrupt processing program that occurs when the power supply voltage drops. Note that this NMI interrupt processing is started not only in the case of a power failure or the like, but also at the end of business operation of the game hall and when the AC power supply is shut off.

In the NMI interrupt processing, first, the contents of each register (AF, I, BC, DE, HL) are saved in the stack area of the built-in RAM (ST50). Specifically, the PUSH instructions in FIG. 8C are executed in order, but the interrupt vector register I is changed to A by executing the instructions of the LD A and I.
When loaded into the register (accumulator), the value of the interrupt enable flip-flop of the Z80 CPU is set in P / V (parity / overflow flag) correspondingly. Therefore, by executing the PUSH AF instruction for the second time, the I register and the F register (P / V flag) in which the value of the permission flip-flop is copied are stored in the stack area.

  When the execution of a group of PUSH instructions is completed in this way, the value of the stack pointer SP at that time is then stored in the SP storage area of the RAM (ST51).

  Subsequently, since there is a case where a prize ball is currently being paid out, the state of the prize ball counting switch is detected and stored (ST52). Note that waiting for a predetermined time (ST53) takes into account the time during which the prize ball being paid out moves.

  If the passage of the predetermined time is confirmed, the value of the backup flag BFL is next determined (ST54). As described above, the backup flag BFL is cleared to zero in the RAM clear process (ST7) of the main process or the flag clear process (ST13). Therefore, the backup flag BFL should be zero after the gaming machine is normally started through any of the above processes.

  On the other hand, when the backup flag BFL is not zero, it means that the flag value 5AH set in step ST56 is maintained as it is. Such a situation occurs when the power is turned off after starting the main process and before executing the RAM clear process (ST7) or the flag clear process (ST13). Therefore, in this embodiment, when the backup flag BFL is not zero, the checksum calculation in step ST55 is skipped.

  However, in the normal case, since the backup flag BFL = 0, the same checksum calculation as in step ST5 of the main process is executed (ST55). Specifically, 8-bit addition is continuously performed on the work area of the internal RAM (see FIG. 8C), and the addition result is stored as a checksum value at the SUM address. Since it is preferable that the area to be subjected to 8-bit operation is wide, the entire area of the RAM excluding the SUM address and the BFL address (backup flag BFL) is used here.

  Thereafter, after storing the flag value 5AH at the address BFL (ST56), the RAM access is prohibited, and the CPU waits for the power supply voltage to drop and the CPU to become inoperative (ST57). After that, the CPU is in an inoperative state, but since the backup power BU is supplied to the RAM, the backed up data continues to be stored as it is. That is, the contents of the RAM are maintained as they are even after the power supply voltage is completely cut off.

Although the embodiments of the present invention have been specifically described above, the specific description content is not intended to limit the present invention, and various modifications can be made. For example, in the embodiment, the interrupt vector is changed by changing the value of the I register of the CPU, but the interrupt vector output from the CTC unit may be changed instead. Further, although the interrupt mode 2 is used in the embodiment, the interrupt mode 1 may be used. In this case, the start address of the interrupt processing routine is fixed. For example, by checking the value of the monitoring timer variable TM at the beginning of the interrupt routine, either of FIG. 6A or FIG. It may be determined whether the processing should be started.

  In the embodiment, the clerk switch is provided. However, instead of this, the clerk may perform a predetermined operation as a start condition of the game operation. The operation by the clerk may be input of a cryptographic value using a numeric keypad. In addition, a plurality of switches such as the chance button 11 and the RAM clear switch may be operated in a predetermined order as a condition for starting the game operation.

  Further, in the embodiment, after the RAM clear process, the launch of the game ball is prohibited, but it is not always necessary to prohibit the launch of the game ball. In the case of not prohibiting the launch of the game ball, when the game ball wins at any of the winning openings, the OK evaluation of step ST26 can be made. This is because there is virtually no possibility that a game ball will win before the big hit counter CT is completed. And if such an embodiment is taken, there exists an advantage which a player does not wait for the start of game operation | movement at all. The fact that the game ball has won the winning opening is stored in a dedicated detection flag FG, and in the original timer interrupt TIMER_INT after steps ST25 to 28, the winning ball is paid out based on the dedicated detection flag FG. Is executed without any problem.

BGN 1st counter CT 2nd counter

Claims (3)

A second counter that circulates a predetermined numerical range to generate a random number lottery value and a first counter that defines an initial value of the cyclic operation of the second counter are provided, resulting from the player's operation or the operation of the game medium In a lottery process, a gaming machine that determines whether or not to generate a profit state advantageous to a player based on a random number lottery value,
CPU is activated when Ru is reset, a main processing that includes a first updating process that updates a value of the first counter in an infinite loop, is activated and receives an interrupt signal, the value of the second counter at predetermined time intervals An interrupt process including a second update process for repeatedly updating, and a gaming operation is controlled,
There are first and second switches that define whether or not to allow lottery processing,
When the storage area of the memory is initially set in the main process, the second counter makes a round of the predetermined numerical range without executing the lottery process, and the initial value of the subsequent cyclic operation is On the condition that it is changed based on the value, the ON state of the first and second switches is determined,
A gaming machine configured such that if the first switch is in the ON state, the subsequent lottery process is permitted regardless of the OFF state of the second switch . The gaming machine according to claim 1, wherein when the first switch is in an OFF state, a subsequent lottery process is permitted on condition that the second switch is in an ON state . The gaming machine according to claim 1 or 2, wherein a game medium launching operation is prohibited at a timing until the ON state of the first and second switches is determined.

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