JP4746699B1 - 半導体記憶装置及びその制御方法 - Google Patents
半導体記憶装置及びその制御方法 Download PDFInfo
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- JP4746699B1 JP4746699B1 JP2010019546A JP2010019546A JP4746699B1 JP 4746699 B1 JP4746699 B1 JP 4746699B1 JP 2010019546 A JP2010019546 A JP 2010019546A JP 2010019546 A JP2010019546 A JP 2010019546A JP 4746699 B1 JP4746699 B1 JP 4746699B1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices
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Abstract
【解決手段】複数のCPUと複数チャネルの不揮発性メモリとを有する半導体記憶装置であって、複数チャネルの不揮発性メモリ毎の消去動作用のアドレスからなるアドレスリストをアドレスキュー(14)に設定する手段()と、いずれかのCPUから発生された単一の消去動作要求に応じて前記アドレスリストに記載の各アドレスについての一連の消去動作コマンドを連続して発生するコマンド制御部(18)と、前記一連の消去動作コマンドを各アドレスに対応したチャネルの不揮発性メモリに与える分配器(24)とを具備する。
【選択図】図1
Description
Claims (4)
- 複数のCPUと複数チャネルの不揮発性メモリとを有する半導体記憶装置であって、
複数チャネルの不揮発性メモリ毎の消去動作用のアドレスからなる消去用アドレスリストを生成する手段と、
いずれかのCPUから発生された単一の消去動作要求に応じて前記消去用アドレスリストに記載の各アドレスについての一連の消去動作コマンドを連続して発生する手段と、
前記一連の消去動作コマンドを各アドレスに対応したチャネルの不揮発性メモリに与える手段と、
を具備する半導体記憶装置。 - 前記不揮発性メモリは書き込み動作の実行前に消去動作の実行が必要なメモリからなる請求項1記載の半導体記憶装置。
- 前記消去用アドレスリストは複数チャネルの不揮発性メモリ毎の書き込み動作用のアドレスからなる書き込み用アドレスリストと同じである請求項1記載の半導体記憶装置。
- 複数のCPUと複数チャネルの不揮発性メモリとを有する半導体記憶装置の制御方法であって、
複数チャネルの不揮発性メモリ毎の消去動作用のアドレスからなる消去用アドレスリストを生成することと、
いずれかのCPUから発生された単一の消去動作要求に応じて前記消去用アドレスリストに記載の各アドレスについての一連の消去動作コマンドを連続して発生することと、
前記一連の消去動作コマンドを各アドレスに対応したチャネルの不揮発性メモリに与えることと、
を具備する制御方法。
Priority Applications (2)
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JP2010019546A JP4746699B1 (ja) | 2010-01-29 | 2010-01-29 | 半導体記憶装置及びその制御方法 |
US13/013,667 US20110191527A1 (en) | 2010-01-29 | 2011-01-25 | Semiconductor storage device and control method thereof |
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JP2010019546A JP4746699B1 (ja) | 2010-01-29 | 2010-01-29 | 半導体記憶装置及びその制御方法 |
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JP2011108189A Division JP4776742B1 (ja) | 2011-05-13 | 2011-05-13 | 半導体記憶装置及びその制御方法 |
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JP4746699B1 true JP4746699B1 (ja) | 2011-08-10 |
JP2011159070A JP2011159070A (ja) | 2011-08-18 |
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JP2010019546A Expired - Fee Related JP4746699B1 (ja) | 2010-01-29 | 2010-01-29 | 半導体記憶装置及びその制御方法 |
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US (1) | US20110191527A1 (ja) |
JP (1) | JP4746699B1 (ja) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
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US9021180B2 (en) | 2011-06-10 | 2015-04-28 | International Business Machines Corporation | Clearing blocks of storage class memory |
US9021226B2 (en) | 2011-06-10 | 2015-04-28 | International Business Machines Corporation | Moving blocks of data between main memory and storage class memory |
US9021179B2 (en) | 2011-06-10 | 2015-04-28 | International Business Machines Corporation | Store storage class memory information command |
US9037907B2 (en) | 2011-06-10 | 2015-05-19 | International Business Machines Corporation | Operator message commands for testing a coupling facility |
US9058245B2 (en) | 2011-06-10 | 2015-06-16 | International Business Machines Corporation | Releasing blocks of storage class memory |
US9058275B2 (en) | 2011-06-10 | 2015-06-16 | International Business Machines Corporation | Data returned responsive to executing a start subchannel instruction |
US9116788B2 (en) | 2011-06-10 | 2015-08-25 | International Business Machines Corporation | Using extended asynchronous data mover indirect data address words |
US9116789B2 (en) | 2011-06-10 | 2015-08-25 | International Business Machines Corporation | Chaining move specification blocks |
US9116634B2 (en) | 2011-06-10 | 2015-08-25 | International Business Machines Corporation | Configure storage class memory command |
US9323668B2 (en) | 2011-06-10 | 2016-04-26 | International Business Machines Corporation | Deconfigure storage class memory command |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US8583845B2 (en) * | 2008-08-07 | 2013-11-12 | Nec Corporation | Multi-processor system and controlling method thereof |
KR20130114486A (ko) | 2012-04-09 | 2013-10-17 | 삼성전자주식회사 | 씨에이유 별 병렬 큐를 가진 비휘발성 메모리 장치, 이를 포함하는 시스템, 및 비휘발성 메모리 장치의 동작 방법 |
US9792989B2 (en) | 2013-02-07 | 2017-10-17 | Toshiba Memory Corporation | Memory system including nonvolatile memory |
JP5824472B2 (ja) | 2013-04-25 | 2015-11-25 | 京セラドキュメントソリューションズ株式会社 | メモリーアクセス制御システム及び画像形成装置 |
US10019161B2 (en) * | 2015-08-31 | 2018-07-10 | Sandisk Technologies Llc | Out of order memory command fetching |
TWI614764B (zh) * | 2016-06-30 | 2018-02-11 | 華邦電子股份有限公司 | 記憶體裝置及其操作方法 |
CN107564563B (zh) | 2016-06-30 | 2020-06-09 | 华邦电子股份有限公司 | 存储器装置及其操作方法 |
US20180285562A1 (en) * | 2017-03-31 | 2018-10-04 | Intel Corporation | Computing system with protection against memory wear out attacks |
CN109683823B (zh) * | 2018-12-20 | 2022-02-11 | 湖南国科微电子股份有限公司 | 一种管理存储器多并发请求的方法及装置 |
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JPH07160569A (ja) * | 1993-12-09 | 1995-06-23 | Matsushita Electric Ind Co Ltd | メモリ制御装置 |
KR970005644B1 (ko) * | 1994-09-03 | 1997-04-18 | 삼성전자 주식회사 | 불휘발성 반도체 메모리장치의 멀티블럭 소거 및 검증장치 및 그 방법 |
JP3440032B2 (ja) * | 1999-07-15 | 2003-08-25 | パナソニック コミュニケーションズ株式会社 | メモリ制御装置,ファクシミリ装置および画像形成装置 |
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JP2003036681A (ja) * | 2001-07-23 | 2003-02-07 | Hitachi Ltd | 不揮発性記憶装置 |
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2010
- 2010-01-29 JP JP2010019546A patent/JP4746699B1/ja not_active Expired - Fee Related
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2011
- 2011-01-25 US US13/013,667 patent/US20110191527A1/en not_active Abandoned
Cited By (27)
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US9021180B2 (en) | 2011-06-10 | 2015-04-28 | International Business Machines Corporation | Clearing blocks of storage class memory |
US9021226B2 (en) | 2011-06-10 | 2015-04-28 | International Business Machines Corporation | Moving blocks of data between main memory and storage class memory |
US9021179B2 (en) | 2011-06-10 | 2015-04-28 | International Business Machines Corporation | Store storage class memory information command |
US9037907B2 (en) | 2011-06-10 | 2015-05-19 | International Business Machines Corporation | Operator message commands for testing a coupling facility |
US9037784B2 (en) | 2011-06-10 | 2015-05-19 | International Business Machines Corporation | Clearing blocks of storage class memory |
US9037785B2 (en) | 2011-06-10 | 2015-05-19 | International Business Machines Corporation | Store storage class memory information command |
US9043568B2 (en) | 2011-06-10 | 2015-05-26 | International Business Machines Corporation | Moving blocks of data between main memory and storage class memory |
US9043643B2 (en) | 2011-06-10 | 2015-05-26 | International Business Machines Corporation | Operator message commands for testing a coupling facility |
US9058245B2 (en) | 2011-06-10 | 2015-06-16 | International Business Machines Corporation | Releasing blocks of storage class memory |
US9058275B2 (en) | 2011-06-10 | 2015-06-16 | International Business Machines Corporation | Data returned responsive to executing a start subchannel instruction |
US9058243B2 (en) | 2011-06-10 | 2015-06-16 | International Business Machines Corporation | Releasing blocks of storage class memory |
US9116788B2 (en) | 2011-06-10 | 2015-08-25 | International Business Machines Corporation | Using extended asynchronous data mover indirect data address words |
US9116813B2 (en) | 2011-06-10 | 2015-08-25 | International Business Machines Corporation | Data returned responsive to executing a Start Subchannel instruction |
US9116789B2 (en) | 2011-06-10 | 2015-08-25 | International Business Machines Corporation | Chaining move specification blocks |
US9116634B2 (en) | 2011-06-10 | 2015-08-25 | International Business Machines Corporation | Configure storage class memory command |
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US9122573B2 (en) | 2011-06-10 | 2015-09-01 | International Business Machines Corporation | Using extended asynchronous data mover indirect data address words |
US9164882B2 (en) | 2011-06-10 | 2015-10-20 | International Business Machines Corporation | Chaining move specification blocks |
US9323668B2 (en) | 2011-06-10 | 2016-04-26 | International Business Machines Corporation | Deconfigure storage class memory command |
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US9411737B2 (en) | 2011-06-10 | 2016-08-09 | International Business Machines Corporation | Clearing blocks of storage class memory |
US9418006B2 (en) | 2011-06-10 | 2016-08-16 | International Business Machines Corporation | Moving blocks of data between main memory and storage class memory |
US9477417B2 (en) | 2011-06-10 | 2016-10-25 | International Business Machines Corporation | Data returned responsive to executing a start subchannel instruction |
US9747033B2 (en) | 2011-06-10 | 2017-08-29 | International Business Machines Corporation | Configure storage class memory command |
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US10387040B2 (en) | 2011-06-10 | 2019-08-20 | International Business Machines Corporation | Configure storage class memory command |
US11163444B2 (en) | 2011-06-10 | 2021-11-02 | International Business Machines Corporation | Configure storage class memory command |
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US20110191527A1 (en) | 2011-08-04 |
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