JP4745273B2 - 半導体装置の製造方法及び半導体製造装置 - Google Patents

半導体装置の製造方法及び半導体製造装置 Download PDF

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Publication number
JP4745273B2
JP4745273B2 JP2007070033A JP2007070033A JP4745273B2 JP 4745273 B2 JP4745273 B2 JP 4745273B2 JP 2007070033 A JP2007070033 A JP 2007070033A JP 2007070033 A JP2007070033 A JP 2007070033A JP 4745273 B2 JP4745273 B2 JP 4745273B2
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Japan
Prior art keywords
wafer
etching
chamber
thin film
reaction product
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Expired - Fee Related
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JP2007070033A
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English (en)
Japanese (ja)
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JP2008109071A (ja
JP2008109071A5 (enExample
Inventor
裕 勝俣
克明 青木
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Toshiba Corp
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Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2007070033A priority Critical patent/JP4745273B2/ja
Priority to US11/690,450 priority patent/US7833911B2/en
Priority to KR1020070050357A priority patent/KR100937911B1/ko
Publication of JP2008109071A publication Critical patent/JP2008109071A/ja
Publication of JP2008109071A5 publication Critical patent/JP2008109071A5/ja
Application granted granted Critical
Publication of JP4745273B2 publication Critical patent/JP4745273B2/ja
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
JP2007070033A 2006-09-25 2007-03-19 半導体装置の製造方法及び半導体製造装置 Expired - Fee Related JP4745273B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007070033A JP4745273B2 (ja) 2006-09-25 2007-03-19 半導体装置の製造方法及び半導体製造装置
US11/690,450 US7833911B2 (en) 2006-09-25 2007-03-23 Method of manufacturing semiconductor device, apparatus of manufacturing semiconductor device and semiconductor device
KR1020070050357A KR100937911B1 (ko) 2006-09-25 2007-05-23 반도체 장치의 제조 방법, 반도체 제조 장치 및 반도체장치

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2006258536 2006-09-25
JP2006258536 2006-09-25
JP2007070033A JP4745273B2 (ja) 2006-09-25 2007-03-19 半導体装置の製造方法及び半導体製造装置

Publications (3)

Publication Number Publication Date
JP2008109071A JP2008109071A (ja) 2008-05-08
JP2008109071A5 JP2008109071A5 (enExample) 2009-11-12
JP4745273B2 true JP4745273B2 (ja) 2011-08-10

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Family Applications (1)

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JP2007070033A Expired - Fee Related JP4745273B2 (ja) 2006-09-25 2007-03-19 半導体装置の製造方法及び半導体製造装置

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Country Link
US (1) US7833911B2 (enExample)
JP (1) JP4745273B2 (enExample)
KR (1) KR100937911B1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5052313B2 (ja) * 2007-10-29 2012-10-17 株式会社東芝 半導体装置の製造方法
US20140262028A1 (en) * 2013-03-13 2014-09-18 Intermolecular, Inc. Non-Contact Wet-Process Cell Confining Liquid to a Region of a Solid Surface by Differential Pressure
KR102620219B1 (ko) 2018-11-02 2024-01-02 삼성전자주식회사 기판 처리 방법 및 기판 처리 장치
KR102813409B1 (ko) * 2021-11-12 2025-05-30 주식회사 테스 기판 처리 방법
TWI836713B (zh) 2021-11-12 2024-03-21 南韓商Ｔｅｓ股份有限公司 基板處理方法
US20250318418A1 (en) * 2024-04-05 2025-10-09 Emagin Corporation High resolution dpd mask cleaning methods

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0666294B2 (ja) * 1986-09-19 1994-08-24 株式会社日立製作所 ドライエツチング方法
JPH05129246A (ja) 1991-11-07 1993-05-25 Fujitsu Ltd 半導体製造装置のクリーニング方法
JP3299783B2 (ja) * 1992-02-10 2002-07-08 シャープ株式会社 半導体装置の製造方法
JPH08148474A (ja) * 1994-11-16 1996-06-07 Sony Corp ドライエッチングの終点検出方法および装置
JP3393248B2 (ja) * 1995-11-29 2003-04-07 ソニー株式会社 パターンエッチング方法
US5756400A (en) * 1995-12-08 1998-05-26 Applied Materials, Inc. Method and apparatus for cleaning by-products from plasma chamber surfaces
WO2000024048A1 (en) * 1998-10-19 2000-04-27 Applied Materials, Inc. Method of etching patterned layers useful as masking during subsequent etching or for damascene structures
JP3712898B2 (ja) 1998-05-28 2005-11-02 株式会社日立製作所 プラズマエッチング装置
US6527968B1 (en) * 2000-03-27 2003-03-04 Applied Materials Inc. Two-stage self-cleaning silicon etch process
US6677242B1 (en) * 2000-08-12 2004-01-13 Applied Materials Inc. Integrated shallow trench isolation approach
JP2002110643A (ja) * 2000-09-27 2002-04-12 Toshiba Corp エッチング方法および半導体装置の製造方法
KR20040074681A (ko) 2003-02-18 2004-08-26 삼성전자주식회사 인시츄 챔버 클리닝 방법 및 이를 이용한 반도체 웨이퍼처리 장치
KR100602080B1 (ko) * 2003-12-31 2006-07-14 동부일렉트로닉스 주식회사 식각 챔버의 세정 방법
KR20050099666A (ko) * 2004-04-12 2005-10-17 삼성전자주식회사 반도체 기판 가공 장치
JP4522888B2 (ja) * 2005-03-01 2010-08-11 東京エレクトロン株式会社 プラズマ処理装置におけるｆ密度測定方法とプラズマ処理方法およびプラズマ処理装置

Also Published As

Publication number Publication date
KR100937911B1 (ko) 2010-01-21
US20080076261A1 (en) 2008-03-27
KR20080027714A (ko) 2008-03-28
JP2008109071A (ja) 2008-05-08
US7833911B2 (en) 2010-11-16

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