JP4734580B2 - エンハンスド・バス・ターンアラウンド集積回路ダイナミック・ランダム・アクセス・メモリ装置 - Google Patents

エンハンスド・バス・ターンアラウンド集積回路ダイナミック・ランダム・アクセス・メモリ装置 Download PDF

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Publication number
JP4734580B2
JP4734580B2 JP2001052888A JP2001052888A JP4734580B2 JP 4734580 B2 JP4734580 B2 JP 4734580B2 JP 2001052888 A JP2001052888 A JP 2001052888A JP 2001052888 A JP2001052888 A JP 2001052888A JP 4734580 B2 JP4734580 B2 JP 4734580B2
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Prior art keywords
memory
memory device
integrated circuit
refresh
signal
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JP2001052888A
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Japanese (ja)
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JP2001283587A5 (enExample
JP2001283587A (ja
Inventor
デビッド・ボンデュラント
デビッド・フィッシュ
ブルース・グリーシャバー
ケネス・モブレイ
マイケル・ピータース
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インテレクチュアル ベンチャーズ ワン エルエルシー
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System (AREA)
JP2001052888A 2000-02-29 2001-02-27 エンハンスド・バス・ターンアラウンド集積回路ダイナミック・ランダム・アクセス・メモリ装置 Expired - Fee Related JP4734580B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/515,007 US6151236A (en) 2000-02-29 2000-02-29 Enhanced bus turnaround integrated circuit dynamic random access memory device
US09/515007 2000-02-29

Publications (3)

Publication Number Publication Date
JP2001283587A JP2001283587A (ja) 2001-10-12
JP2001283587A5 JP2001283587A5 (enExample) 2008-03-13
JP4734580B2 true JP4734580B2 (ja) 2011-07-27

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JP2001052888A Expired - Fee Related JP4734580B2 (ja) 2000-02-29 2001-02-27 エンハンスド・バス・ターンアラウンド集積回路ダイナミック・ランダム・アクセス・メモリ装置

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US (2) US6151236A (enExample)
EP (1) EP1130603A3 (enExample)
JP (1) JP4734580B2 (enExample)

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US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
JP2000137983A (ja) * 1998-08-26 2000-05-16 Toshiba Corp 半導体記憶装置
US7069406B2 (en) 1999-07-02 2006-06-27 Integrated Device Technology, Inc. Double data rate synchronous SRAM with 100% bus utilization
JP4083944B2 (ja) 1999-12-13 2008-04-30 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
US6373751B1 (en) 2000-05-15 2002-04-16 Enhanced Memory Systems, Inc. Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies
EP2056301B1 (en) * 2000-07-07 2011-11-30 Mosaid Technologies Incorporated A high speed dram architecture with uniform access latency
CA2340804A1 (en) * 2001-03-14 2002-09-14 Atmos Corporation Sram emulator
US7085186B2 (en) * 2001-04-05 2006-08-01 Purple Mountain Server Llc Method for hiding a refresh in a pseudo-static memory
JP4459495B2 (ja) * 2001-12-13 2010-04-28 富士通マイクロエレクトロニクス株式会社 半導体記憶装置のリフレッシュ制御方法、及び該制御方法を有する半導体記憶装置
US6829184B2 (en) * 2002-01-28 2004-12-07 Intel Corporation Apparatus and method for encoding auto-precharge
US6795899B2 (en) * 2002-03-22 2004-09-21 Intel Corporation Memory system with burst length shorter than prefetch length
US7043599B1 (en) * 2002-06-20 2006-05-09 Rambus Inc. Dynamic memory supporting simultaneous refresh and data-access transactions
JP4236901B2 (ja) 2002-10-23 2009-03-11 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及びその制御方法
JP4236903B2 (ja) 2002-10-29 2009-03-11 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及びその制御方法
JP4439838B2 (ja) 2003-05-26 2010-03-24 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及びその制御方法
US7433258B2 (en) * 2003-10-10 2008-10-07 Datasecure Llc. Posted precharge and multiple open-page RAM architecture
US20050159925A1 (en) * 2004-01-15 2005-07-21 Elias Gedamu Cache testing for a processor design
US20050172091A1 (en) * 2004-01-29 2005-08-04 Rotithor Hemant G. Method and an apparatus for interleaving read data return in a packetized interconnect to memory
US7042776B2 (en) * 2004-02-18 2006-05-09 International Business Machines Corporation Method and circuit for dynamic read margin control of a memory array
US8151030B2 (en) * 2004-05-26 2012-04-03 Ocz Technology Group, Inc. Method of increasing DDR memory bandwidth in DDR SDRAM modules
US8688892B2 (en) 2004-05-26 2014-04-01 OCZ Storage Solutions Inc. System and method for increasing DDR memory bandwidth in DDR SDRAM modules
JPWO2006080065A1 (ja) * 2005-01-27 2008-06-19 スパンション エルエルシー 記憶装置、およびその制御方法
US7584335B2 (en) 2006-11-02 2009-09-01 International Business Machines Corporation Methods and arrangements for hybrid data storage
IT201800000581A1 (it) * 2018-01-05 2019-07-05 St Microelectronics Srl Metodo di gestione dell'accesso in tempo reale a una memoria differenziale, memoria differenziale e sistema elettronico includente la memoria differenziale
US11256442B2 (en) 2018-01-05 2022-02-22 Stmicroelectronics S.R.L. Real-time update method for a differential memory, differential memory and electronic system
IT201800000580A1 (it) 2018-01-05 2019-07-05 St Microelectronics Srl Metodo di aggiornamento in tempo reale di una memoria differenziale con accessibilita' continua in lettura, memoria differenziale e sistema elettronico

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EP0440243A3 (en) * 1990-01-31 1993-12-15 Nec Corp Memory controller for sub-memory unit such as disk drives
US5652723A (en) * 1991-04-18 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
JPH0581852A (ja) * 1991-09-24 1993-04-02 Mitsubishi Denki Eng Kk 半導体記憶装置
EP0895162A3 (en) * 1992-01-22 1999-11-10 Enhanced Memory Systems, Inc. Enhanced dram with embedded registers
US5537564A (en) * 1993-03-08 1996-07-16 Zilog, Inc. Technique for accessing and refreshing memory locations within electronic storage devices which need to be refreshed with minimum power consumption
JPH07254271A (ja) * 1994-03-16 1995-10-03 Toshiba Corp ダイナミックランダムアクセスメモリおよびこれを用いたメモリシステム
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US5983313A (en) * 1996-04-10 1999-11-09 Ramtron International Corporation EDRAM having a dynamically-sized cache memory and associated method
US5940851A (en) * 1996-11-27 1999-08-17 Monolithic Systems, Inc. Method and apparatus for DRAM refresh using master, slave and self-refresh modes
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US5991851A (en) * 1997-05-02 1999-11-23 Enhanced Memory Systems, Inc. Enhanced signal processing random access memory device utilizing a DRAM memory array integrated with an associated SRAM cache and internal refresh control
US5999481A (en) * 1997-08-22 1999-12-07 Micron Technology, Inc. Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals
JP3092558B2 (ja) * 1997-09-16 2000-09-25 日本電気株式会社 半導体集積回路装置
US5999474A (en) * 1998-10-01 1999-12-07 Monolithic System Tech Inc Method and apparatus for complete hiding of the refresh of a semiconductor memory

Also Published As

Publication number Publication date
US6301183B1 (en) 2001-10-09
EP1130603A3 (en) 2002-04-03
US6151236A (en) 2000-11-21
JP2001283587A (ja) 2001-10-12
EP1130603A2 (en) 2001-09-05

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