JP4723757B2 - Game machine - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pachinko machine that can be reset for each symbol control function and other functions.
[0002]
[Prior art]
Conventionally, in a pachinko machine, a function that controls the entire pachinko machine is assigned to the main board, and a specific function that is performed according to a command from the main board, for example, a symbol control function, a voice control function, a lamp control function, A prize ball payout control function, a launch control function, and the like are allocated to the sub-board. Power is supplied to such a main board and sub board by one power supply unit, and a power-on reset signal is sent from the power supply unit to a CPU (central processing unit) on the main board. And is directly supplied to each CPU of the sub-board. This power-on reset signal changes from active to inactive, for example, 100 ms after the power is turned on.
[0003]
As the delay circuit, for example, a delay circuit as shown in FIG. 6 having a resistor 61, a capacitor 62, and a Schmitt trigger buffer 63 is used. The power-on reset signal is delayed by this delay circuit, and the initialization process of the main board is performed. Since the time becomes longer than the maximum initialization processing time of the sub-board, the command from the main board is surely received by each sub-board.
[0004]
Here, the initialization processing time is the CPU initialization processing by the main board CPU in response to the power-on reset signal input to the main board CPU being changed from active to inactive. For example, this is the time it takes for the main board CPU to issue a command to the sub board, such as setting the I / O port, clearing the RAM, and setting the initial value data. In response to the power-on reset signal input to the sub-board CPU being changed from active to inactive, the CPU of the sub-board performs CPU initialization processing, for example, input / output port setting, RAM clearing and initial Time until processing of setting value data or the like is performed and a command from the main board can be received by the CPU of the sub board.
[0005]
[Problems to be solved by the invention]
However, when an instantaneous power failure occurs (FIG. 7 (a)), the Schmitt trigger buffer 63 from when the power-on reset signal once falls until it rises after holding the low level for 5 ms, for example (FIG. 7 (b)). 7C is, for example, as shown in FIG. 7C. Since the power-on reset signal is not supplied from the delay circuit of FIG. 6 (FIG. 7D), the main board is not reset. Therefore, no command is issued by the CPU of the main board.
[0006]
On the other hand, each sub-board is reset, and when the power-on reset signal changes from active to inactive, CPU initialization processing, for example, input / output port setting, RAM clearing, initial value data setting, and the like are performed. Although it is possible to receive a command after the CPU initialization process by the CPU on the sub board, the command is not issued after the CPU initialization process by the CPU on the main board, so that the pachinko machine malfunctions. was there.
[0007]
An object of the present invention is to solve the above-described problems and provide a gaming machine that can prevent a command from being missed by each sub-control means not only after turning on the power but also after a momentary power failure. It is in.
[0008]
[Means for Solving the Problems]
According to the first aspect of the present invention, the main control means, the plurality of sub-control means for performing a predetermined control in accordance with a control command from the main control means, and the active state after a predetermined time has elapsed since the power was turned on. A power-on reset signal which becomes inactive and remains inactive after a predetermined holding time shorter than the time after an instantaneous power failure is supplied to the main control means and the plurality of sub control means In a gaming machine having a supply means,
The main control means includes a first resistance, a second resistance having a resistance value smaller than the first resistance, a capacitor, a diode, and a Schmitt trigger buffer, and a power-on reset signal supplied by the supply means The first resistor and the capacitor have a time required for the voltage across the capacitor charged through the first resistor to rise to the threshold voltage of the Schmitt trigger buffer. The second resistor has a resistance value and a capacitance such that a total time with the initialization processing time of the main control means is equal to a predetermined time exceeding the maximum initialization processing time of the plurality of sub-control means. The voltage across the capacitor discharged through the circuit formed by connecting the diode and the second resistor in series is Time taken to drops to the threshold voltage of the mitt trigger buffer, characterized by comprising a delay means having an equal such resistance in a predetermined time less than the retention time.
[0009]
According to the second aspect of the present invention, the main control means, the plurality of sub-control means for performing predetermined control according to the control command from the main control means, and the active state after the predetermined time has elapsed since the power was turned on. A power-on reset signal which becomes inactive and remains inactive after a predetermined holding time shorter than the time after an instantaneous power failure is supplied to the main control means and the plurality of sub control means In the gaming machine having a supply means, the main control means is a clock generation means for generating a clock, and a delay means for delaying a power-on reset signal supplied by the supply means, the active power-on reset The signal is reset to activate the output, while the inactive power-on reset signal A counter for releasing the set and making the output inactive, and at the time of reset release, the clock generated by the clock generating means is converted to a maximum initialization process of the pulse width of the clock and the plurality of sub-control means. A delay unit having a counter that inactivates the output when a predetermined number is counted from time, an inverter connected to an output side of the counter of the delay unit and inverting the output from the counter, and An AND gate for performing an AND operation on the output and the clock output from the clock means and inputting the operation result to the counter is provided.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0011]
<First Embodiment>
FIG. 1 shows a first embodiment of the present invention. This is an example of a pachinko machine. In FIG. 1, reference numeral 1 denotes a power supply unit, which includes a regulator 101 and a power-on reset circuit 102. The regulator 101 outputs 12V and 5V voltages. The power-on reset circuit 102 outputs a power-on reset signal after a predetermined time has elapsed after the voltage of 5 V is output from the regulator 101. Reference numeral 2 denotes a main control unit having a delay circuit 201 and a CPU 202. The delay circuit 201 delays the power-on reset signal from the power-on reset circuit 102 by a predetermined time. The CPU 202 includes a ROM and a RAM, and a power-on reset signal from the delay circuit 201 is input to the CPU 202.
[0012]
Reference numeral 3 denotes a symbol control unit which has a CPU 301 with a built-in ROM and RAM and controls the display 4. Voltages of 12V and 5V from the regulator 101 are applied to the symbol control unit 3. A power-on reset signal is directly input from the power-on reset circuit 102 to the CPU 301. An audio control unit 5 includes a CPU 501 with a built-in ROM and RAM, and controls driving of the speaker 4. Voltages of 12V and 5V from the regulator 101 are applied to the voice control unit 5. A power-on reset signal is directly input from the power-on reset circuit 102 to the CPU 501.
[0013]
A lamp control unit 7 has a CPU 701 with a built-in ROM and RAM, and controls driving of the indicator lamp 8. The lamp controller 7 is applied with voltages of 12 V and 5 V of the regulator 101. A power-on reset signal is directly input from the power-on reset circuit 102 to the CPU 701. A payout control unit 9 has a CPU 901 with a built-in ROM and RAM, and controls the payout device 10. The dispensing control unit 9 is applied with voltages of 12 V and 5 V of the regulator 101. A power-on reset signal is directly input from the power-on reset circuit 102 to the CPU 901. A launch control unit 11 includes a CPU 1101 incorporating a ROM and a RAM, and controls the launch device 12. Voltages 12V and 5V of the regulator 101 are applied to the launch control unit 11. A power-on reset signal is directly input from the power-on reset circuit 102 to the CPU 1101.
[0014]
The symbol control unit 3, the voice control unit 5, the lamp control unit 7, the payout control unit 9, and the launch control unit 11 are sub-control units for the main control unit 2.
[0015]
FIG. 2 shows a configuration of the delay circuit 201 of FIG. The power-on reset signal input terminal is connected to the input terminal of the Schmitt trigger buffer 23 via the resistor 21, and the node between the resistor 21 and the input terminal of the Schmitt trigger buffer 23 is connected to the ground via the capacitor 22. A circuit formed by connecting the resistor 24 and the cathode of the diode 25 is connected to the resistor 21 in parallel.
[0016]
According to the delay circuit 201 configured as described above, the rising edge (FIG. 3A) of the power-on reset signal is expressed by the following equation:
[0017]
[Expression 1]
Trd = −C · R1 · ln (1− (Vth / Vh)) (1)
[0018]
Where C is the capacitance of the capacitor 22,
R1: resistance value of the resistor 21,
Vth: Schmitt trigger buffer threshold,
Vh: Delayed by a delay time Trd obtained from the high level voltage of the power-on reset signal (see FIGS. 3B and 3C).
[0019]
On the other hand, according to the delay circuit 201 configured as described above, the falling edge (FIG. 3A) of the power-on reset signal is expressed by the following equation:
[0020]
[Expression 2]
Tfd = −C · R2 · ln (Vth / Vh) (2)
[0021]
Where C is the capacitance of the capacitor 22,
R2: resistance value of the resistor 24,
Vth: Schmitt trigger buffer threshold,
Vh: Delayed by a delay time Tfd obtained from the high level voltage of the power-on reset signal (see FIGS. 3B and 3C).
[0022]
Here, it is assumed that the threshold (Vth) of the Schmitt trigger buffer and the high level voltage (Vh) of the power-on reset signal are known in advance.
[0023]
Therefore, the total time of the delay time Trd and the initialization process time of the main board is determined as the maximum initialization process among the graphic control unit 3, the voice control unit 5, the lamp control unit 7, the payout control unit 9, and the launch control unit 11. The delay time Tfd is set equal to a predetermined time exceeding the time, and the delay time Tfd is a predetermined time shorter than a known holding time Tinst until the power-on reset signal level once becomes low level after instantaneous power failure. To satisfy Eqs. (1) and (2), and
[0024]
[Equation 3]
Resistance value of resistor 21 >> Resistance value of resistor 24
The capacitor 22 and the resistors 21 and 24 having a capacitance and a resistance value satisfying the above are employed.
[0026]
According to the delay circuit 201 employing the capacitor 22 and the resistors 21 and 24 having such capacitance and resistance value, the rising edge delay time of the rising edge of the power-on reset signal after power-on and the initialization processing time of the main board And the total initialization time exceeds the maximum initialization processing time of the sub-board. On the other hand, the falling edge of the power-on reset signal can be delayed by a predetermined time less than the time Tinst after the instantaneous power failure. The total time of the edge delay time and the initialization processing time of the main board exceeds the maximum initialization processing time of the sub-board.
[0027]
Therefore, it is possible to prevent the command control unit 3, the voice control unit 5, the lamp control unit 7, the payout control unit 9, and the launch control unit 11 from losing commands not only after the power is turned on but also after the power supply is momentarily stopped. .
[0028]
<Second Embodiment>
The present embodiment is different from the first embodiment in the configuration of the delay circuit.
[0029]
FIG. 4 shows a delay circuit according to this embodiment. This delay circuit has a counter 41, an inverter 42, and an AND gate 43. The counter 41 is reset by a low-level power-on reset signal, the inverter 42 inverts the output level of the counter, and the AND gate 43 performs an AND operation on the output of the inverter 42 and the clock ck. Is.
[0030]
The counter 41 is set so that the level of the output terminal becomes high when n clocks ck are counted. At this time, one of the two input terminals of the AND gate 43 becomes low level due to the output of the inverter 42, and AND The clock ck is not output to the output of the gate 43, and therefore the clock ck is not input to the counter 41.
[0031]
The delay time Td is set equal to a predetermined time exceeding the maximum initialization processing time among the graphic control unit 3, the voice control unit 5, the lamp control unit 7, the payout control unit 9, and the launch control unit 11.
[0032]
Furthermore, a relational expression between the pulse width t of the clock ck, the delay time Td, and the count number n of the counter 41, that is,
[0033]
[Expression 4]
Td ≤ t · n
[0034]
It is assumed that n obtained from the above is adopted.
[0035]
According to the delay circuit configured as described above, the counter 41 is reset until the power-on reset signal from the power-on reset circuit 102 rises after the power is turned on, and the level of the output terminal becomes the low level. The output level of the inverter 42 is high. As a result, the clock ck is input to the counter 41 via the AND gate 43. However, since the counter 41 is in a reset state, the clock ck cannot be counted (FIGS. 5C and 5D).
[0036]
Thereafter, when the power-on reset signal rises (FIG. 5B), the counter 41 is released from the reset and starts counting the clock ck. When n clocks ck are counted (FIG. 5 (d)), the level of the output terminal of the counter 41 is changed from the low level to the high level (FIG. 5 (e)), so that the output level of the inverter 42 is low level. become. As a result, the clock ck is not input to the counter 41 via the AND gate.
[0037]
On the other hand, once an instantaneous power failure occurs (FIG. 5A), the level of the power-on reset signal is low until the power-on reset signal rises, that is, until the time Tinst elapses after the power is supplied. Since it is level, the counter 41 is in a reset state, the level of the output terminal is low level, and the output level of the inverter 42 is high level. The clock ck is input to the counter 41 via the AND gate. However, since the counter 41 is in a reset state, the clock ck cannot be counted (FIGS. 5C and 5D).
[0038]
When the power-on reset signal rises (FIG. 5 (b)), the counter 41 is released from the reset and starts counting the clock ck. When n clocks ck are counted (FIG. 5 (d)), that is, when delayed by the rising edge delay time corresponding to the multiplication result of the pulse width of the clock ck and n, the level of the output terminal becomes low level. To the high level (FIG. 5 (e)), so that the output level of the inverter 42 becomes the low level. As a result, the clock ck is not input to the counter 41 via the AND gate.
[0039]
According to such a delay circuit 201, the total time of the rising edge delay time of the rising edge of the power-on reset signal after power-on and the initialization processing time of the main board exceeds the maximum initialization processing time of the sub board. On the other hand, the falling edge of the power-on reset signal can be delayed by a predetermined time less than the time Tinst after a power failure, and the total time of the rising edge delay time and the main board initialization processing time The maximum initialization processing time of the sub-board will be exceeded.
[0040]
Therefore, it is possible to prevent the command control unit 3, the voice control unit 5, the lamp control unit 7, the payout control unit 9, and the launch control unit 11 from losing commands not only after the power is turned on but also after the power supply is momentarily stopped. .
[0041]
【The invention's effect】
As described above, according to the present invention, since it is configured as described above, it is possible to prevent a command from being missed by each sub-control unit not only after the power is turned on but also after a momentary power failure.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of the present invention.
2 is a circuit diagram showing a configuration of a delay circuit 201 in FIG. 1. FIG.
FIG. 3 is a timing chart showing an example of the timing of each part of the delay circuit 201 in FIG. 2;
FIG. 4 is a block diagram showing a second embodiment of the present invention.
FIG. 5 is a timing chart showing an example of the timing of each part of the delay circuit in FIG. 4;
FIG. 6 is a circuit diagram showing a conventional example of a delay circuit.
7 is a timing chart showing an example of the timing of each part of the delay circuit in FIG. 6. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Power supply unit 2 Main control part 3 Graphic control part 4 Audio | voice control part 7 Lamp control part 9 Discharge control part 11 Launch control part 21, 24 Resistance 22 Capacitor 23 Schmitt trigger buffer 25 Diode 41 Counter 42 Inverter 43 AND gate 101 Regulator 102 Power On-reset circuit 201 Delay circuit 202, 301, 501, 701, 901, 1101 CPU

Claims (2)

A main control means, a plurality of sub-control means for performing a predetermined control in accordance with a control command from the main control means, a transition from an active state to an inactive state after an elapse of a predetermined time after the power is turned on, A gaming machine having supply means for supplying a power-on reset signal that becomes inactive after holding an active state for a predetermined holding time shorter than the time later to the main control means and the plurality of sub-control means In
The main control means includes
A delay unit that includes a first resistor, a second resistor having a resistance value smaller than that of the first resistor, a capacitor, a diode, and a Schmitt trigger buffer, and delays a power-on reset signal supplied by the supply unit; The first resistor and the capacitor are connected to the capacitor to be charged via the first resistor. The time required for the voltage between the terminals of the capacitor to rise to the threshold voltage of the Schmitt trigger buffer is increased. And a resistance value and a capacitance such that a total time of the second resistance is equal to a predetermined time exceeding a maximum initialization time among the plurality of sub-control means, and the second resistance includes the diode and the second resistance A voltage across the capacitor discharged through a circuit formed by connecting a second resistor in series is the Schmitt trigger buffer. Gaming machine takes to descend until the threshold voltage of §, characterized in that a delay means having an equal such resistance in a predetermined time less than the retention time. A main control means, a plurality of sub-control means for performing a predetermined control in accordance with a control command from the main control means, a transition from an active state to an inactive state after an elapse of a predetermined time after the power is turned on, A gaming machine having supply means for supplying a power-on reset signal that becomes inactive after holding an active state for a predetermined holding time shorter than the time later to the main control means and the plurality of sub-control means In
The main control means includes
Clock generation means for generating a clock;
Delay means for delaying the power-on reset signal supplied by the supply means, resetting the active power-on reset signal to activate the output, and releasing the reset by the inactive power-on reset signal A counter that inactivates the output, and at the time of reset release, the clock generated by the clock generating means is calculated from the pulse width of the clock and the maximum initialization processing time of the plurality of sub-control means. Delay means having a counter for inactivating the output when counting a predetermined number ;
An inverter connected to the output side of the counter of the delay means and inverting the output from the counter;
An gaming machine comprising: an AND gate that performs an AND operation on an output of the inverter and a clock output from the clock means, and inputs the operation result to the counter .

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