JP3817639B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine, and more particularly to a gaming machine including a main control board that controls the progress of a game and a sub-control board other than the main control board.

In gaming machines, such as pachinko machines, hardware interrupts are applied to the reset terminal when the power is turned on, and hardware interrupts are applied to the user reset terminal of the main control board every predetermined time (about 2 ms to 4 ms) For each interrupt, the main routine process is repeatedly executed in the program that controls the game, and each process of the main routine is executed in a time shorter than the predetermined time. The remaining processing is executed, and when a user reset is caused by a hardware interrupt, the process returns to the top of the main routine and the processing is repeated. As a result, even if the process is runaway due to noise, the process returns to the original place, and the runaway state can be prevented. Then, when the memories are compared and the memory value is a value within a certain area, it is determined as normal data, and the game is continued with reference to the stored data. Also, since the random number update timing and the detection timing of various switches are set to a fixed period and the winning or passing timing is random, the timer value extracted at the winning or passing timing is randomly extracted and the appearance rate is uniform. Therefore, it functions as a random number.
On the other hand, when memory backup is used for battery backup and measures are taken for power failure, a hardware interrupt is forcibly applied to a non-maskable interrupt (hereinafter abbreviated as NMI) terminal of the CPU provided on the main control board during a power failure such as a momentary power failure. Data to be retained is saved.

  However, the conventional pachinko gaming machine has the following problems. That is, as described above, when an attempt is made to detect a power failure by the rise or fall of a signal at the NMI terminal, there may be a case where the power failure cannot be detected depending on the timing of the hardware interrupt to the user reset terminal. For example, when the timing at which the user reset signal becomes valid and the timing at which the NMI signal becomes valid occur almost at the same time, the rise and fall of the NMI signal may not be detected. In order to avoid this, it is also conceivable to execute the power failure detection by making the NMI signal valid for a predetermined time or more and determining whether or not the signal is continuously output for a predetermined time or more. However, since the data saving time such as data backup for power failure becomes short, the power failure processing is greatly delayed, and it is impossible to detect a game ball in which a winning ball or a ball lending ball is falling. Therefore, the power failure is detected only at the rise and fall of the NMI signal, and it is very difficult to avoid the inconvenience.

  Therefore, the gaming machine of the present invention is made for the purpose of preventing the NMI interrupt and the user reset interrupt from competing in hardware when the memory is retained by battery backup.

That is, in order to solve the above-mentioned problem, the present invention has been found by executing the resetting by software, instead of performing the resetting by applying the user reset to the main routine every predetermined time in terms of hardware. That is, the invention described in claim 1 is a power failure process for saving data for resuming a game from a gaming state at the time of a power failure, an initialization process for initializing a RAM when power is turned on, and the saving process. Including a power-on process for executing any one of the backup start setting processes for performing the setting process according to the data, and an input process for monitoring the input states of a plurality of switches after executing the power-on process and a random number update process. A gaming machine comprising a main control board having means for executing a main process for performing a process relating to the progress of a game and a residual process for performing an update process of the random number after the main process ends, wherein the main control N substrate, after completion of the power-on process, the normal processing execution section for executing the normal constructed from the present process and the remaining process, which is input to the forced interruption terminal By I control signal is changed, the backup setting processing for setting the NMI flag, and timer means for performing measurement of the time, the elapsed time is the set time from the start of processing at the time of the normal clocked by said timer means a time-up determining means for setting the INT flag indicating that elapsed, if the INT flag by the time-up determining means is set, abort the remaining processing to force, the process after discontinuation during the normal If the NMI flag is set by executing processing regression means for returning to the beginning of processing and processing for determining the presence or absence of the NMI flag before processing for determining the presence or absence of the INT flag Power failure processing transition means for forcibly stopping the normal processing regardless of the presence or absence of the INT flag and shifting to the power failure processing A game machine characterized by comprising a.

  The gaming machine according to claim 1 having the above-mentioned configuration can solve the above-mentioned problem suitably, can equalize random number update timing (timer update timing) and detection timing of various switches, and randomize winning or passing timing Therefore, it is possible to directly use the conventional random number extraction technique.

  The sub-control board includes at least a prize payout control board. In a pachinko gaming machine, the sub-control board may include a symbol control board or the like that displays symbols in a variable manner. The prize payout control board is a board that controls a drive device for paying out prizes, and in a pachinko machine, a motor or solenoid that pays out a prize ball (also referred to as “prize ball” or “prize ball”) as a prize. In a throttle gaming machine, a board that drives and controls a hopper that pays out coins as a prize.

  According to the first aspect of the present invention, the NMI interrupt and the user reset interrupt do not compete with each other in hardware although the program is periodically executed. Therefore, the process at the time of a power failure can be processed appropriately.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The embodiments of the present invention are not limited to the following examples, and it goes without saying that various forms can be adopted as long as they belong to the technical scope of the present invention.
As shown in FIG. 1, the pachinko machine 10 according to the present embodiment includes a rectangular outer frame 11 and a front frame 12. A known card reader (prepaid card unit) 13 is provided on the left side of the outer frame 11. It has been. The front frame 12 is rotatably attached to the outer frame 11 by hinges 14 at the upper and lower left ends.
An upper plate 15 is provided below the front frame 12, and a lending button 16, a settlement button 17 and a balance display unit 18 are provided on the upper plate 15. When a prepaid card is inserted into the card slot 19 of the card reader 13, the stored balance is displayed on the balance display unit 18, and when the lending button 16 is pressed, the game ball is lent out and the game ball is loaded from the payout slot of the upper plate 15. Discharged.

A window-shaped metal frame 20 is removably attached to the front frame 12 with respect to the front frame 12. A plate glass 21 is double fitted in the metal frame 20. A game board 22 is stored behind the plate glass 21.
A lower plate 23 is provided at the lower part of the front frame 12 of the upper plate 15, and a firing handle 24 is attached to the right side of the lower plate 23. A rotation ring (not shown) is held on the outer periphery of the launch handle 24, and the game ball can be launched onto the game board 22 by rotating clockwise.
The upper plate 15 and the lower plate 23 are connected to each other, and are configured to guide the game ball to the lower plate 23 when the upper plate 15 is full of game balls.

FIG. 2 is a back view of the pachinko machine 10 viewed from the back side. As shown in the drawing, a mechanism board 26 to which the above-described game board 22 is detachably attached is housed in the above-described outer frame 11. The mechanism panel 26 is provided with a ball tank 27, a guide rod 28, and a payout device 29 from above. With this configuration, if there is a winning game ball at the winning slot on the game board 22, a predetermined number of gaming balls can be discharged from the ball tank 27 via the guide rod 28 to the above-described upper plate 15 by the payout device 29. .
In addition, the main control board 30 and the payout control board 31 can be attached to and detached from the mechanism board 26. The game board 22 has a special symbol display device 32, the launch control board 33 in the lower left part of the front frame, and the special symbol display device 32. External connection terminal boards 42 are respectively attached to the left side of each.

Next, the game board 22 will be described with reference to FIG.
The game board 22 has an LCD panel unit (hereinafter referred to as “LCD”) 32a constituting a special symbol display device 32 at the center, a normal electric accessory 36 as a first type starting port at the lower part, and an ordinary upper part of the LCD 32a. The symbol display device 37, the normal symbol operation gates 38 and 39 on the left and right of the LCD 32a used to start the variation of the symbol displayed on the normal symbol display device 37, the large winning opening 40 below the normal electric accessory 36, and the bottom bottom out A mouth 41, other various winning holes, a windmill, a game nail (not shown), and the like are provided.
With this configuration, when the above-described launch handle 24 is rotated, the launch motor 33a (see FIG. 4) driven by the launch control board 33 is driven, and the game ball on the upper plate 15 is played through the guide rail 22 via the guide rail. Fired up. If the launched game ball wins each winning hole, the game ball is taken into the back of the board as a safe ball, and if not won, it is taken into the back of the board through the out port 41 as well.

Next, the electrical configuration of the pachinko machine 10 described above will be described with reference to the block diagram of FIG.
As shown in the figure, the electric circuit of the pachinko machine 10 includes the main control board 30, the payout control board 31, the special symbol display device 32, the launch control board 33, the lamp control board 34, the sound control board 35, and the like. Yes. In this circuit diagram, a so-called relay board for transferring signals is not described.

The main control board 30 is configured as a logic operation circuit centered on an 8-bit one-chip microcomputer incorporating a CPU 66, a ROM 81 storing a game control program, a RAM 80 serving as a work area for operations, a timer circuit 82, and the like. External input / output circuits for inputting / outputting from / to each substrate or various switches and various actuators are also provided.
On the input side of the main control board 30 are a first type start port switch 36a, normal symbol operation switches 38a and 39a, an accessory continuous operation switch (hereinafter simply referred to as "V switch") 40a, a count switch 40b, a full tank A switch 43, a replenishment switch 44, a plurality of other prize opening switches 45, a ball removal switch 46, and the like are connected. On the output side, a big prize opening solenoid 40c, a V solenoid 40d, a normal accessory solenoid 36b, an external connection terminal board 42, and the like are connected.

The first type start port switch 36a is in the ordinary electric accessory 36 on the game board 22 described above, the normal symbol operation switches 38a and 39a are in the normal symbol operation gates 38 and 39, respectively, and the V switch 40a is in the big prize opening 40. In a specific area, the count switch 40b is also in the big prize opening 40, the full tank switch 43 is in the lower tray 23, the replenishment switch 44 is in the ball tank 27, and the other prize opening switches 45 are the ordinary electric accessory 36 and the big prize opening 40. Each winning opening on the board surface and the ball removal switch 46 are attached in the vicinity of the payout device 29. Here, the V switch 40a wins the prize winning opening 40 when the game ball that has won the prize winning opening 40 has passed the special device operating area (hereinafter referred to as "special area"). For all game balls, the full tank switch 43 indicates that the game ball is full in the lower plate 23, the replenishment switch 44 indicates that there is a game ball in the ball tank 27, and the other prize opening switch 45. Indicates that a game ball has been won at each prize slot on the board other than the ordinary electric accessory 36 and the big prize slot 40, and a ball removal switch 46 is used to detect that the ball removal operation button has been pressed. It is.
The large winning opening solenoid 40c connected to the output side is used in the large winning opening 40, the V solenoid 40d is used in a special area in the large winning opening 40, and the ordinary accessory solenoid 36b is used for opening and closing the ordinary electric accessory 36. Is.

  The special symbol display device 32 includes the above-described LCD 32a and a symbol display device control board (hereinafter simply referred to as “design control board” (hereinafter also referred to as “image control board”)) 32b for driving and controlling the LCD 32a. The special symbol start memory display device 32c (see FIG. 3) for displaying the start memory number and the attached unit such as a backlight and an inverter board. Similar to the main control board 30 described above, the symbol control board 32b is configured as a logic operation circuit centered on an 8-bit one-chip microcomputer.

As with the main control board 30, the payout control board 31 is configured as a logical operation circuit using a microcomputer. The input circuit is connected to a prize ball payout switch 31a and a ball rental payout switch 31b, and the output circuit is cut into balls. A motor 31c and a ball lending motor 31d are connected. Further, the card reader 13 described above is bidirectionally connected to the payout control board 31, and a CR settlement display board 47 is connected to the card reader 13. The prize ball payout switch 31 a is also connected to the main control board 30.
The ball cutting motor 31c and the ball lending motor 31d are provided in the above-described payout device 29, and flow down a predetermined number of game balls supplied from the guide rod 28. A game ball paid out from the ball cutting motor 31c is detected by a prize ball payout switch 31a, and a game ball paid out from the ball rental motor 31d is detected by a ball rental payout switch 31b.
The CR adjustment display board 47 includes the lending button 16, the adjustment button 17, and the balance display unit 18 of the upper plate 15 described above. The CR adjustment display board 47 may be connected to the payout control board 31.

When prize ball payout command data is transmitted from the main control board 30 with the above configuration, the payout control board 31 that has received this data adds the number of prize balls indicated by the transmitted data to the unpaid prize ball data. Are stored as new prize ball data, and after subtracting a predetermined number of game balls as prize balls, a subtraction process is executed from the prize ball data stored in the game balls detected by the prize ball payout switch 31a to obtain new prize balls. The payout process is executed until the value of the prize ball data becomes zero.
On the other hand, when the lending button 16 on the CR adjustment display board 47 is pressed, a 1-pulse signal is transmitted from the card reader 13 to the payout control board 31 in the case of 100 yen, and a 5-pulse signal is transmitted in the case of 500 yen. The The payout control board 31 executes a process of paying out the lending balls by drivingly controlling the ball lending motor 31d until 25 game balls are detected by the lending payout switch 31b for one pulse signal.

The launch control board 33 drives and controls the launch motor 33a in accordance with the amount of rotation of the launch handle 24 operated by the player. When the player presses the launch stop switch 24b, the launch control board 33 stops firing or launches. When the touch switch 24a built in the handle 24 is in an ON state, the touch lamp 48 is turned on.
The touch switch 24 a is built in the firing handle 24 and detects that the player is touching the firing handle 24.

  The lamp control board 34 is mainly composed of a drive element such as a transistor. Upon receiving a command from the main control board 30, a normal symbol display device 37 having a normal symbol holding lamp and a normal symbol LED, a big hit lamp and an error. This is for lighting and displaying lamps such as lamps and various lamps such as LEDs.

  The sound control board 35 includes a sound source IC, an amplifier, and the like, and is used to drive and control the speaker 49 in response to a command from the main control board 30.

  Transmission to the special symbol display device 32, the payout control board 31, the launch control board 33, the lamp control board 34, and the sound control board 35 described above is a one-way communication circuit so that transmission can be performed only from the main control board 30. It is configured. This one-way communication circuit can be realized using an inverter circuit or a latch circuit.

As shown in FIGS. 5 and 6, the main control board 30, the payout control board 31, the design control board 32b, the launch control board 33, the lamp control board 34, the sound control board 35, etc. Is supplied.
The power supply board 50 is connected to a 24V AC power supply 51, diode bridge circuits 52 and 53 connected to the 24V AC power supply 51, full wave 24V generation circuit 54 and DC32V generation circuit 55 connected to the diode bridge circuit 52, and diode bridge circuit 53. DCP2V generation circuit 56 and DC5V generation circuit 57 connected to the DC5V generation circuit 57, and a VBB power supply generation circuit 58 that is connected to the DC5V generation circuit 57 and generates a DC5V backup power supply by a capacitor, and supplies necessary power to each control board. It is configured as follows.
The VBB power supply generation circuit 58 is connected to the main control board 30 and the payout control board 31 and supplies a backup power supply VBB.

Here, as shown in FIG. 6, the power supply substrate 50 includes a power-on reset circuit 61, an AC voltage monitoring circuit 62, a timer 1 circuit 63, a timer 2 circuit 64, and a power-down reset circuit 65.
The output side of the AC voltage monitoring circuit 62 is connected to the forced interrupt terminal NMI of the CPU 66 of the main control board 30 and the forced interrupt terminal NMI of the CPU 67 of the payout control board 31.
A power-down reset circuit 65 and a timer 2 circuit 64 are connected via an OR circuit 68 to the reset terminal RES of the CPU 66 of the main control board 30.
A power-down reset circuit 65 and a timer 1 circuit 63 are connected to a reset terminal RES of the CPU 67 of the payout control board 31 via an OR circuit 69.
A power-down reset circuit 65 and a power-on reset circuit 61 are connected via an OR circuit 71 to the reset terminal RES of the CPU 70 of the symbol control board 32b.
Similarly, a power-down reset circuit 65 and a power-on reset circuit 61 are also connected to the CPUs 72, 74, and 76 of the launch control board 33, the lamp control board 34, and the sound control board 35 via OR circuits 73, 75, and 77, respectively. It is connected.
The VBB power generation circuit 58 is connected to the backup terminal VBB (RAM) of the CPU 66 of the main control board 30 and the backup terminal VBB (RAM) of the CPU 67 of the payout control board 31.

As shown in FIG. 7, the power-on reset circuit 61 includes a voltage monitoring IC 8, resistors R38, R39 and R40, bypass capacitors C22 and C23, and the like. The VS terminal that is the input terminal of the voltage monitoring IC 8 is supplied with a DC12V power source divided by the resistors R39 and R40, and the RESET terminal that is the output terminal is pulled up to DC5V by the resistor R38.
With the above configuration, the RESET terminal, which is the output terminal of the voltage monitoring IC 8, changes the reset signal 1 to be output from the high level to the low level when the voltage of the DC12V power supply decreases to 7.20-7.75V or less.

The timer 1 circuit 63 sets the CPU reset signal 2 output after a predetermined time (in this embodiment, 100 ms) from when the CPU reset signal 1 output from the power-on reset circuit 61 is changed from high level to low level. The delay circuit is configured to change from a level to a low level.
The timer 2 circuit 64 sets the CPU reset signal 3 output after a predetermined time (300 ms in this embodiment) from when the CPU reset signal 1 output from the power-on reset circuit 61 is changed from high level to low level. The delay circuit is configured to change from a level to a low level.

  The power-down reset circuit 65 sets the CPU reset signal 4 output after a predetermined time (in this embodiment, 100 ms) from when the power failure detection signal output from the AC voltage monitoring circuit 62 is changed from high level to low level. The delay circuit is configured to change from a level to a low level.

With the above configuration, the main control board 30, the payout control board 31, and other sub-control boards other than the payout control board 31 when the power is supplied to the pachinko machine 10, that is, the symbol control board 32b, the launch control board 33, the lamp The operation of each CPU or the rising state of the control operation of each of the control board 34 and the sound control board 35 will be described with reference to the timing chart shown in FIG.
When the pachinko machine 10 is turned on, the power supply board 50 generates DC32V, DC12V, DC5V, and battery backup power supply (VBB). Each generated power supply is supplied to each control board. The sub-control board including the symbol control board 32b, the payout control board 31, and the power-on reset circuit 61, the timer 1 circuit 63, and the timer 2 circuit 64 The main control board 30 performs an operation start-up process as follows.

  As shown in FIG. 8, when the power supply is turned on to the power supply board 50 (point P1), the voltages of the DC32V, DC12V, and DC5V power supplies gradually rise from 0V to 32V, 12V, and 5V in a parabolic manner. The NMI control signal is set after a predetermined time T1 has elapsed since the voltage of the DC5V power supply that gradually rises to the reference value LV2 (point P2) indicating the power-on reset voltage. In the meantime, DC32V reaches the gaming machine parts guaranteed voltage level, and then DC32V reaches the backup start voltage. The power-on reset circuit 61 does not immediately output a reset control signal even when the DC5V power supply reaches the reference value LV2. In this embodiment, the power-on reset time T2 rises after the backup start timing by the backup power supply VBB. = After about 100 ms, the reset control signal, which is the output signal of the power-on reset circuit 61, changes from the low level to the high level (point P3), and each sub-control board such as the symbol control board 32b excluding the payout control board 31 The reset signal 1 changes from the low level to the high level (point P3), the reset state is canceled, and the operation related to the control is started. That is, for all the sub-control boards except the payout control board 31, the reset signal from the power supply board 50 is directly input to the reset terminal of each CPU, and no delay time is set.

  In the timer 1 circuit 63, T3 = about 200 ms elapses after the DC5V power supply voltage becomes the reference value LV2, that is, 100 ms elapses after the CPU reset signal 1 output from the power-on reset circuit 61 changes from low level to high level. The CPU reset signal 2 to be output later is changed from the low level to the high level (point P4). This is set in consideration of the reset signal delay time and the security check time in the payout control board 31. The CPU 67 of the payout control board 31 to which the CPU reset signal 2 is input performs a security check as to whether the program is a normal program over a period of about 320 ms from when the CPU reset signal 2 becomes high level. Later, control related to payout will be executed. Accordingly, the CPU 67 of the payout control board 31 starts up the operation about 520 ms after the voltage of the DC 5V power supply becomes the reference value LV2.

  The timer 2 circuit 64 has T4 = about 300 ms after about 400 ms elapses after the voltage of the DC5V power supply becomes the reference value LV2, that is, after the CPU reset signal 1 output from the power-on reset circuit 61 changes from low level to high level. The CPU reset signal 3 output after the passage is changed from low level to high level (point P5). This is set in consideration of the reset signal delay time and the security check time in the main control board 30. The CPU 66 of the main control board 30 to which the CPU reset signal 3 is inputted performs a security check as to whether or not the program is a normal program over a period of about 200 ms after the CPU reset signal 3 becomes high level. Later, control related to winning detection or the like is executed. Therefore, the CPU 66 of the main control board 30 starts up the operation about 600 ms after the voltage of the DC 5V power supply reaches the reference value LV2.

  Thus, when the CPU 66 of the main control board 30 starts executing the game control according to the program written in the ROM 81, each sub-control board has already executed the game control. As a result, even if the CPU 66 of the main control board 30 transmits data to each sub-control board immediately after the power is turned on, each sub-control board is executing the original control, so that the data can be reliably received. .

Next, an operation when power-on to the pachinko machine 10 is interrupted by a power failure or the like will be described with reference to a timing chart shown in FIG.
When the power supply to the pachinko machine 10 is interrupted by a power failure, the AC voltage A decreases and becomes zero, and the DC 32V, DC 12V, and DC 5V decrease as shown in FIG. The power failure detection signal of the AC voltage monitoring circuit 62 of the power supply board 50 changes from high level to low level. When DC32V is lowered to the backup start voltage level V by the power down reset circuit 65 (point P6), the NMI control signal is reset, and DC32V is lowered to the gaming machine component guaranteed voltage level V1. After a predetermined time T5 (after about 100 ms) from the reset of the NMI control signal, the reset control signal and the CPU reset signal of each board are reset (point P7). This is because the forced reset signal is output after a certain period of time has elapsed since the detection of the power failure detection signal in consideration of the time for software processing. Thereby, the CPU 66 of the main control board 30, the CPU 67 of the payout control board 31, the CPU 70 of the symbol control board 32 b, and other sub-control boards are stopped simultaneously. Thereafter, the DC 32V reaches the switching power supply IC minimum drive voltage level V2, and the DC 5V becomes the CPU operation guaranteed minimum voltage level V3, which attenuates to zero level. Therefore, the forced interrupt terminals NMI of the CPU 66 of the main control board 30 and the CPU 67 of the payout control board 31 are set to the low level, the non-maskable interrupt is applied to the CPUs 66 and 67, and the NMI states of the main control board 30 and the payout control board 31 are changed. Then, after a predetermined time elapses, the CPU operating state of each control board is stopped. As a result, the CPU 66 of the main control board 30 can save the data indicating the current game state and thereafter prohibit access to the RAM 80. Further, the CPU 67 of the payout control board 31 can save the data indicating the current prize ball payout state and the ball lending payout state, and thereafter prohibit the access to the RAM of the payout control board 31.

The CPU reset signal output about 100 ms after the fall of the signal at which the power failure detection signal output from the AC voltage monitoring circuit 62 changes from high level to low level (point P6) is changed from high level to low level (point P7).
Here, as described above, the RAMs of the main control board 30 and the payout control board 31 are backed up by the battery, and the data stored in the RAM is stored for a predetermined time (about 3 days in the present embodiment) even when the power is turned off. Retained.

  As described above, when the power is turned off, the control boards are reset all at once. Moreover, the power failure detection signal output from the AC voltage monitoring circuit 62 is always reset about 100 ms after the high level changes to the low level. Thereby, it is possible to unify the control, and it is possible to prevent the adverse effect that the firing motor 33a is driven even though the operation of the main control board 30 is stopped.

Here, in the present embodiment, the CPU reset signal is output about 100 ms after the power failure detection signal output from the AC voltage monitoring circuit 62 changes from the high level to the low level. Thus, it is calculated.
The CPU 67 of the payout control board 31 executes the power failure processing routine described above when the forced interrupt terminal NMI becomes low level. At this time, the driving of the ball cutting motor 31c and the ball lending motor 31d is also stopped. When there is a game ball that is paid out immediately before the driving of these motors stops, it is necessary to detect the falling game ball by the prize ball payout switch 31a or the ball rental payout switch 31b. Therefore, it is necessary to ensure a time during which the detecting game balls can be detected by the respective detection switches when the driving of the motor is stopped. On the other hand, if this time is ensured too long, the voltage of the 5V power source for driving the IC may be lowered and may not be detected by each detection switch. Therefore, in the present embodiment, about 100 ms is set due to the balance between the two. Therefore, the distance from each motor to the detection switch and the voltage drop state may be changed as appropriate. In short, it may be configured to secure a time for detecting a falling game ball within a time during which driving of the IC is guaranteed after the forced interrupt terminal NMI becomes low level.

  The hardware operation at the time of power failure, power-on, etc. has been described above. Next, the main processing shown in FIG. 10 will be described. This main processing is composed of (1) power-on processing, (2) main processing, (3) residual processing, (4) time-up processing, and (5) power failure processing, as indicated by the dotted line. Is. That is, the power-on process described above is a process executed at power-on reset (steps S1 to S7), this process is a process for executing a game (steps S11 to S18), and the remaining process is a timer reset after the end of this process. The processing executed until this time (steps S20 to S21) and the time-up processing are time-up processing (step S22, S22) in which the timer value is read from the timer circuit 82 to reset the software and repeat this processing every predetermined time. S10), the power failure process is a process of waiting in a loop in response to the power failure detection (steps S19, S23, S24). In other words, this main process consists of this process and the remaining process after the power-on process, that is, the initialization process when the power is turned on, and the backup function is activated when the power is restored and when the power is turned off. The normal processing is performed, and in response to the time-up time (2.731 ms), the normal processing is repeated. If an NMI control signal that is a power failure signal is input, the data is saved and the processing is stopped. is there.

  The purpose of the time-up process is to provide a timer circuit 82 so as to always return to the top of this process when the timer value exceeds a predetermined value. By executing this, it is possible to equalize the scanning timing or random number update timing when the game ball enters each entrance. When the game ball enters the ordinary electric accessory (starting opening) 36 due to such equalization, this is a random timing. The update timing of various random numbers is random, and there is a detrimental effect that it is not clear where the reference is based. Therefore, it is dealt with by executing normal processing at regular intervals. Here, the board is supported by hardware so that the main control board 30 does not run out of control, but if it runs out of control, it is set to forcibly reset by pulling out the manual switch or power plug. is there. If such a forced reset is applied, the above-mentioned battery-backed storage state is all cleared and the process starts from the initialization process. In addition, a reset switch input is provided, and when it is entered, a circuit with a reset is provided to start initialization after the RAM data is backed up by a battery. The required processing will be described in detail below.

First, when processing is started, a stack pointer is set (step S1), and it is determined whether or not the power-on flag is ON (step S2). If the determination is negative (NO), the RAM is initialized (step S5), the power-on flag is set to ON (step S6), and an initialization process for setting an initial value in the work area as a normal power-on process is performed. (Step S7), and the process proceeds to Step S8. If the determination in step S2 is affirmative (YES), it is determined whether the backup release signal is ON (step S3). If the determination is affirmative (YES), steps S5 to S7 are executed, and the process proceeds to step S8. If the determination in step S3 is negative (NO), a backup start setting process for transmitting a command indicating that the backup function has been activated to the lamp control board 34 is performed (step S4), and the process proceeds to step S8.
The backup start setting process is a setting process performed in accordance with data saved when a power failure occurs in order to resume the game from the gaming state at the time of the power failure.

  After the processing of step S4 or S7, the NMI flag is set to OFF (step S8), timer interrupt setting processing for initial setting of the timer circuit 82 and the like is performed (step S9), and an interrupt flag (hereinafter referred to as an INT flag) Is set to OFF (flag is reset) (step S10).

Subsequently, this processing, that is, random number update processing (step S11), input processing (step S12), special electric accessory processing (step S13), ordinary electric accessory processing (step S14), probability variation determination symbol processing (step) S15), information data creation processing (step S16), port output processing (step S17), and timer update processing (step S18).
The random number update process (step S11) performs various random number update processes.
The input process (step S12) monitors inputs from various switches.
In the special electric accessory processing (step S13), the special symbol display device 32 is controlled by performing the special symbol operation control and the big hit operation control.
In the ordinary electric accessory processing (step S14), normal symbol display device 37 is controlled by performing normal symbol operation control and hit operation control.
The probability variation determination symbol process (step S15) controls the operation of the probability variation determination symbol.
The information data creation process (step S16) creates output data of solenoids, information signals, and test apparatus information.
The port output process (step S17) outputs a solenoid, an information signal, and information for a test apparatus, and transmits a command to the payout control board 31, the lamp control board 34, the sound control board 35, and the symbol control board 32b.
The timer update process (step S18) updates the timer circuit 82 for controlling the processing time.

  After the process of step S18, it is determined whether the NMI flag is ON (step S19). If the determination is affirmative (YES), it is determined that a power failure signal has been input, and access to the RAM is prohibited (step S23). The output is turned off (step S24), and the program processing is waited in a loop.

  If the determination in step S19 is negative (NO), it is determined that the power failure signal has not been input, the remaining process, that is, the initial value random number update process (step S20), the symbol random number update process (step S21) is executed, and the INT flag Is determined to be ON, that is, whether the time is up (2.731 ms has elapsed) (step S22). If the determination is negative (NO), the process returns to step S20 to continue the residual processing, and the affirmative determination (YES) ), The remaining process is terminated, and the process proceeds to step S10. As a result, an interrupt is executed by software.

  The time-up setting process in FIG. 11A is a process for setting an INT flag indicating that an interrupt has occurred every 2.731 ms. When the INT flag is set to ON, an affirmative determination is made in step S22 of FIG. 10, and the process proceeds to step S10. The backup setting process in FIG. 11B is a process for setting an NMI flag indicating that an NMI interrupt has occurred because a power failure signal has been input to ON. When the NMI flag is set to ON, an affirmative determination is made in step S19 in FIG. 10, and the process proceeds to steps S23 and S24. In the backup setting process, as shown by the NMI control signal in FIG. 9, the NMI flag is turned ON (set) at the falling edge of the signal that is input from the NMI terminal to the OFF state.

  Next, the module configuration of the program stored in the main control board 30 will be described. 12 through 19 show the main module, and FIG. 20 shows the interrupt module. The main module has a hierarchical structure. That is, the main module sequentially shifts to the lower module, and is executed along a series of processing flows. In some cases, the main routine is executed and a series of flows is executed as it is, or the initial setting is performed and the random number is updated as it is. For example, there is an input process in the main process, but there are a number of subordinate modules in this input process, and they are selected as appropriate in the process flow. Therefore, in normal processing, the accumulated time from the start of processing varies depending on the status.

  More specifically, the first layer includes main processing (MAIN). As the second hierarchy, initialization processing (INTLIZ), backup start setting processing (BKUSTR), timer interrupt setting processing (INTENS), random number update processing (RNDUP), input processing (INPA), special electric accessory processing (TDZ), There are a normal electric accessory process (FDZ), a probability variation determination symbol process (HZCHK), an information data creation process (JYSET), a port output process (POUT), and a timer update process (TMDEC).

The third to fifth layers are as follows. RAM setting process (RAMCHG) under initialization process (INTLIZ), ramp port output process (LMPPTO) under backup start setting process (BKUSTR), initial value random number update process (TZSUP) under random number update process (RNDUP) ), Special symbol random number update processing (TZRUP), jackpot symbol random number update processing (TZAUP), symbol random number update processing (TZCTUP), outlier symbol creation processing (TZJH), probability variation determination symbol random number update processing (HZCTUP) , Normal symbol random number update processing (FZRUP) and variation pattern random number update processing (TZHUP).
Below the input process (INPA), there is an input data creation process (SWDINP), and below that there is an input data creation process 1 (SWCHK1) and an input data creation process 2 (SWCHK2).
Below the input process (INPA) is the symbol switch process (ZSWCK), and further below it is the first type start port switch process (TZSWCK), the normal electric character prescribed winning number monitoring process (STUP), and the normal symbol operation switch process ( FZSWCK).
Under the input process (INPA), the special electric accessory switch process (YSWCK), further below the count switch process (CTSW), the accessory continuous operation switch process (VSW), and further below the RAM setting process (RAMCHG) There is.
Below the input process (INPA), a prize ball update process (SYCTCK), and further below, a prize ball counter 1 update process (SYUP1), a prize ball counter 2 update process (SYUP2), and a prize ball counter 3 update process (SYUP3). is there.
Under the input process (INPA), the prize ball control switch process (PAYIN) is further followed by the prize ball sensor monitoring process (PAYCK1), and further below it is the prize ball sensor counter update process (SNSCHK) and the lamp port output process ( LMPPTO).
Below the prize ball control switch process (PAYIN), there is a ball break switch process (PAYCK2), and further below there is a lamp port output process (LMPPTO) and a prize ball data port output process (PAYPTO).
Below the prize ball control switch process (PAYIN), there is a mantan switch process (PAYCK3), and below that, there is a lamp port output process (LMPPTO) and a prize ball data port output process (PAYPTO).
There is a special symbol process (TZCHK) and a big hit operation process (TDYAK) under the special electric accessory process (TDZ).
Under special symbol processing (TZCHK), there are special symbol waiting processing (TZWAIT), special symbol changing processing (TZHEND), and special symbol stop display processing (TZJUDG). Under these special symbol hold shift processing (TSHFT), jackpot determination processing (TZCHU), special symbol pattern setting processing 1 (TPTST1), RAM setting processing (RAMCHG), special symbol pattern setting processing 2 (TPTST2), and RAM setting processing (RAMCHG).
Under the jackpot action process (TDYAK), there are a jackpot first interval process (TDDFAN), a jackpot release process (TDKAI), a jackpot interval process (TDINT), and a jackpot end process (TDEND). There are processing (OPENST) and RAM setting processing (RAMCHG).
There are a normal symbol process (FZCHK) and a hit action process (FDYAK) under the normal electric accessory process (FDZ).
Under normal symbol processing (FZCHK), there are normal symbol waiting processing (FZWAIT), normal symbol changing processing (FZHEND), and normal symbol stop display processing (FZJUDG). Below these, normal symbol hold shift processing (FZJUDG) FSHFT), hit determination processing (FZCHU), normal symbol pattern setting processing (FPTSET), and RAM setting processing (RAMCHG).
Under the hit operation process (FDYAK), there are a hit interval process (FDFAN), a hit release process (FEND), and a hit end process (FEND).
Under the probability variation determination symbol processing (HZCHK), there are a probability variation determination symbol standby processing (HZWAIT), a probability variation determination symbol variation processing (HZHEND), and a probability variation determination symbol suspension display processing (HZJUDG).
Under the information data creation process (JYSET), there are a start port information creation process (SIDJST), a solenoid data creation process (SOLSET), and a test apparatus information data creation process (TSTJST).
Below the port output process (POUT), an LCD output process (LCDOUT), a sound effect output process (SNDOUT), a ramp data output process (LMPOUT), a hold data command output process (HORDUT), and a prize ball data output process (PAYCHK) Under them, special symbol command transmission processing (TZDOUT), normal symbol command transmission processing (FDOUT), probability variation determination symbol command transmission processing (HZDOUT), ramp port output processing (LMPPTO), prize ball data There is port output processing (PAYPTO).
Furthermore, an LCD port output process (LCDPTO) is provided under the special symbol command transmission process (TZDOUT), the normal symbol command transmission process (FZDOUT), and the probability variation determination symbol command transmission process (HZDOUT).
There are an initial value random number update process (TZSUP) and a design random number update process (TZCTUP) as the third layer under the main process (MAIN).

  As shown in FIG. 20, the interrupt module includes the time-up setting process (INT) and the backup setting process (NMI) described above.

  As described above, according to the present embodiment, the hardware interrupt at the NMI terminal and the hardware INT interrupt do not compete with each other, so that the power failure processing such as backup accompanying power failure detection is properly executed. At the same time, the timing of random number update, timer update, and detection of various switches can be made uniform, and the conventional random number extraction technique can be used as it is.

  As the above-described modification, as shown by the dotted line in FIG. 6, an embodiment in which a watchdog circuit 90 for preventing hardware runaway can be added. The watchdog circuit 90 is connected to the monitoring terminal of the CPU 66 and resets the CPU 66 when the CPU 66 runs out of control if no signal is received within a predetermined time. When the runaway is detected by the watchdog circuit 90, a detection signal is input to the reset terminal and the backup RAM is all cleared, but it may be set so as to return to the main processing.

  As another modification, instead of the INT flag, the processing time of each step of the main processing and the residual processing in FIG. 10 is added, and when the addition time exceeds a predetermined time, the configuration returns to the top of the main processing. good. Since the processing time of each step is generally determined, a processing time is set in advance for each step, and the processing time is added every time each step is completed. Then, the addition processing time is compared with the time-up setting time. When the time-up setting time is exceeded, the remaining processing is aborted, the addition processing time is reset to zero, and the process proceeds to the first processing of this processing. As described above, a preset addition process time may be executed for each step, and as another aspect, for example, a timer is actually counted up from the start to the end of a process and added. You may do it.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and many technical design changes can be made without departing from the technical idea of the present invention. Of course, it can be done.

It is an external appearance perspective view which shows the pachinko machine 10 which employ | adopted this invention. It is the back view which looked at the pachinko machine 10 from the back. 2 is a front view showing a configuration of a game board 22 of the pachinko machine 10. FIG. 2 is a block diagram showing an electrical configuration of a pachinko machine 10. FIG. 3 is a block diagram showing a configuration for supplying power from a power supply board 50. FIG. FIG. 3 is a block diagram showing a relationship between a power supply board 50, a main control board 30 and each sub control board. 3 is a circuit diagram showing a configuration of a power-on reset circuit 61. FIG. It is a timing chart which shows the state at the time of power activation. It is a timing chart which shows the state at the time of power interruption. It is a flowchart which shows "main processing." (A) is a flowchart showing a “time-up setting process”, and (b) is a flowchart showing a “backup setting process”. FIG. 3 is a block diagram (part 1) of a main module of a program stored in a main control board 30; It is a block diagram (the 2) of the main module. It is a block diagram (the 3) of the main module. It is a block diagram (the 4) of the main module. It is a block diagram (the 5) of the main module. It is a block diagram (the 6) of the main module. It is a block diagram (the 7) of the main module. It is a block diagram (the 8) of the main module. 4 is a block diagram of a program interrupt module of the main control board 30. FIG.

Explanation of symbols

10 ... Pachinko machine 13 ... Card reader (prepaid card unit)
DESCRIPTION OF SYMBOLS 22 ... Game board 24 ... Launching handle 24a ... Touch switch 24b ... Launch stop switch 30 ... Main control board 31 ... Discharge control board 31a ... Prize ball payout switch 31b ... Ball rental payout switch 31c ... Ball cutting motor 31d ... Ball rental motor 32 ... Special symbol display device 32a ... LCD panel unit (LCD)
32b ... design display control board (design control board)
33 ... Launch control board 33a ... Launch motor 34 ... Lamp control board 35 ... Sound control board 36 ... Ordinary electric accessory (starting port)
36a ... First-type start opening switch 37 ... Normal symbol display device 40 ... Large prize opening 40a ... Accessory continuous operation switch (VSW)
40b ... count switch (count SW)
45 ... Other prize opening switch 46 ... Ball exit switch 47 ... CR adjustment display board 48 ... Touch lamp 49 ... Speaker 50 ... Power supply board 61 ... Power-on reset circuit 62 ... AC voltage monitoring circuit 63 ... Timer 1 circuit 64 ... Timer 2 circuit 65: Power-down reset circuit 66, 67, 70, 72, 74, 76 ... CPU (one-chip microcomputer)
68, 69, 71, 73, 75, 77 ... OR circuit 80 ... RAM 81 ... ROM 82 ... Timer circuit 90 ... Watchdog circuit

Claims (1)

During a power outage, a power outage process that saves data for resuming the game from the gaming state at the time of the power outage,
A power-on process for executing any of an initialization process for initializing the RAM at the time of power-on, and a backup start setting process for performing a setting process according to the saved data;
After executing the power-on processing, the main processing for performing processing related to the progress of the game, including input processing for monitoring input states of a plurality of switches and random number updating processing;
A residual process for updating the random number after the process is completed;
A gaming machine comprising a main control board having means for executing
The main control board is
Normal time processing execution means for executing normal processing composed of the main processing and the remaining processing after the power-on processing is terminated ;
A backup setting process for setting the NMI flag by changing the NMI control signal input to the forced interrupt terminal;
Timer means for measuring time; and
Time-up determination means for setting an INT flag indicating that the elapsed time from the start of the normal processing timed by the timer means has passed a set time;
A process regression means for forcibly aborting the residual process when the INT flag is set by the time-up determination means, and returning the process after the abort to the head of the normal process;
If the NMI flag is set by executing the process for determining the presence or absence of the NMI flag before the process for determining the presence or absence of the INT flag, the normal time is determined regardless of the presence or absence of the INT flag. Forcibly stopping the processing of the power failure, and shifting to the power failure processing, the power failure processing transition means,
A gaming machine characterized by comprising:

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