JP4717972B2 - 集積回路の製造方法 - Google Patents

集積回路の製造方法 Download PDF

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Publication number
JP4717972B2
JP4717972B2 JP10647399A JP10647399A JP4717972B2 JP 4717972 B2 JP4717972 B2 JP 4717972B2 JP 10647399 A JP10647399 A JP 10647399A JP 10647399 A JP10647399 A JP 10647399A JP 4717972 B2 JP4717972 B2 JP 4717972B2
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Japan
Prior art keywords
dielectric
layer
stop layer
mask
stop
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP10647399A
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English (en)
Japanese (ja)
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JP2000003961A (ja
JP2000003961A5 (enExample
Inventor
クリストファ・ヴェローヴ
Original Assignee
エスティマイクロエレクトロニクス エスエー
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Publication of JP2000003961A5 publication Critical patent/JP2000003961A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
JP10647399A 1998-04-16 1999-04-14 集積回路の製造方法 Expired - Lifetime JP4717972B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9804754 1998-04-16
FR9804754A FR2777697B1 (fr) 1998-04-16 1998-04-16 Circuit integre avec couche d'arret et procede de fabrication associe

Publications (3)

Publication Number Publication Date
JP2000003961A JP2000003961A (ja) 2000-01-07
JP2000003961A5 JP2000003961A5 (enExample) 2006-04-13
JP4717972B2 true JP4717972B2 (ja) 2011-07-06

Family

ID=9525310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10647399A Expired - Lifetime JP4717972B2 (ja) 1998-04-16 1999-04-14 集積回路の製造方法

Country Status (4)

Country Link
US (2) US6410425B1 (enExample)
EP (1) EP0951067B1 (enExample)
JP (1) JP4717972B2 (enExample)
FR (1) FR2777697B1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6309801B1 (en) * 1998-11-18 2001-10-30 U.S. Philips Corporation Method of manufacturing an electronic device comprising two layers of organic-containing material
US6313025B1 (en) * 1999-08-30 2001-11-06 Agere Systems Guardian Corp. Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit
US6812130B1 (en) * 2000-02-09 2004-11-02 Infineon Technologies Ag Self-aligned dual damascene etch using a polymer
KR100366621B1 (ko) * 2000-06-28 2003-01-09 삼성전자 주식회사 반도체 소자의 도전성 콘택체를 형성하는 방법
KR100434511B1 (ko) * 2002-08-12 2004-06-05 삼성전자주식회사 다마신 배선을 이용한 반도체 소자의 제조방법
JP2004274020A (ja) * 2002-09-24 2004-09-30 Rohm & Haas Electronic Materials Llc 電子デバイス製造
KR100538379B1 (ko) * 2003-11-11 2005-12-21 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03203240A (ja) * 1989-12-28 1991-09-04 Fujitsu Ltd 半導体装置の製造方法
FR2663784B1 (fr) * 1990-06-26 1997-01-31 Commissariat Energie Atomique Procede de realisation d'un etage d'un circuit integre.
JPH05326719A (ja) * 1992-05-27 1993-12-10 Oki Electric Ind Co Ltd 半導体素子の製造方法
JPH08139194A (ja) * 1994-04-28 1996-05-31 Texas Instr Inc <Ti> 半導体デバイス上に電気接続を作製する方法および該方法により作製された電気接続を有する半導体デバイス
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US5736457A (en) * 1994-12-09 1998-04-07 Sematech Method of making a damascene metallization
JPH0964179A (ja) * 1995-08-25 1997-03-07 Mitsubishi Electric Corp 半導体装置およびその製造方法
CN1075612C (zh) * 1996-01-11 2001-11-28 三菱自动车工业株式会社 汽车用换档装置
JPH09306988A (ja) * 1996-03-13 1997-11-28 Sony Corp 多層配線の形成方法
US5880018A (en) * 1996-10-07 1999-03-09 Motorola Inc. Method for manufacturing a low dielectric constant inter-level integrated circuit structure
JP3390329B2 (ja) * 1997-06-27 2003-03-24 日本電気株式会社 半導体装置およびその製造方法
JP3300643B2 (ja) * 1997-09-09 2002-07-08 株式会社東芝 半導体装置の製造方法
TW374946B (en) * 1997-12-03 1999-11-21 United Microelectronics Corp Definition of structure of dielectric layer patterns and the manufacturing method

Also Published As

Publication number Publication date
JP2000003961A (ja) 2000-01-07
EP0951067A1 (fr) 1999-10-20
EP0951067B1 (fr) 2018-08-01
US6410425B1 (en) 2002-06-25
US20020127850A1 (en) 2002-09-12
FR2777697B1 (fr) 2000-06-09
FR2777697A1 (fr) 1999-10-22

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