KR100875057B1 - 듀얼 다마신 패턴 형성 방법 - Google Patents
듀얼 다마신 패턴 형성 방법 Download PDFInfo
- Publication number
- KR100875057B1 KR100875057B1 KR1020020040055A KR20020040055A KR100875057B1 KR 100875057 B1 KR100875057 B1 KR 100875057B1 KR 1020020040055 A KR1020020040055 A KR 1020020040055A KR 20020040055 A KR20020040055 A KR 20020040055A KR 100875057 B1 KR100875057 B1 KR 100875057B1
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- South Korea
- Prior art keywords
- trench
- insulating film
- protective layer
- dual damascene
- via hole
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (7)
- 하부 구리 배선을 포함한 기판 상에 층간 절연막을 형성하는 단계;상기 층간 절연막의 일부분을 식각하여 비아홀을 형성하는 단계;상기 비아홀을 포함한 층간 절연막의 표면을 따라 보호층을 형성하는 단계;상기 보호층이 형성된 상태에서 트렌치 식각 공정 및 애싱 공정을 실시하여 트렌치를 형성하는 단계; 및상기 보호층을 제거하여 상기 비아홀 및 상기 트렌치로 된 듀얼 다마신 패턴을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 듀얼 다마신 패턴 형성 방법.
- 제 1 항에 있어서,상기 층간 절연막은 구리 확산 방지 절연막, 비아홀 절연막, 트렌치 식각 정지 절연막, 트렌치 절연막 및 캡핑 절연막이 적층되어 형성되는 것을 특징으로 하는 듀얼 다마신 패턴 형성 방법.
- 제 2 항에 있어서,상기 구리 확산 방지 절연막, 트렌치 식각 정지 절연막 및 캡핑 절연막은 질화물 계통의 절연물질로 형성하는 것을 특징으로 하는 듀얼 다마신 패턴 형성 방법.
- 제 2 항에 있어서,상기 비아홀 절연막 및 트렌치 절연막은 다공성 산화물을 포함하거나, 유전 상수값이 3이하인 저유전 상수값을 갖는 절연물질로 형성하는 것을 특징으로 하는 듀얼 다마신 패턴 형성 방법.
- 제 1 항에 있어서,상기 보호층은 Si, SiO2, SiN, SiON, Ti 및 TiN 중 어느 하나를 사용하여 50 ~ 500Å의 두께로 형성하는 것을 특징으로 하는 듀얼 다마신 패턴 형성 방법.
- 제 1 항에 있어서,상기 보호층은 상기 애싱 공정시에 발생되는 O2 애싱 가스 및 플라즈마로부터 상기 층간 절연막을 보호하는 것을 특징으로 하는 듀얼 다마신 패턴 형성 방법.
- 제 1 항에 있어서,상기 보호층은 습식 식각으로 제거하는 것을 특징으로 하는 듀얼 다마신 패턴 형성 방법.
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KR1020020040055A KR100875057B1 (ko) | 2002-07-10 | 2002-07-10 | 듀얼 다마신 패턴 형성 방법 |
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KR1020020040055A KR100875057B1 (ko) | 2002-07-10 | 2002-07-10 | 듀얼 다마신 패턴 형성 방법 |
Publications (2)
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KR20040005479A KR20040005479A (ko) | 2004-01-16 |
KR100875057B1 true KR100875057B1 (ko) | 2008-12-19 |
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KR1020020040055A KR100875057B1 (ko) | 2002-07-10 | 2002-07-10 | 듀얼 다마신 패턴 형성 방법 |
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20000043063A (ko) * | 1998-12-28 | 2000-07-15 | 김영환 | 반도체 소자의 금속 배선 형성 방법 |
KR20030089564A (ko) * | 2002-05-16 | 2003-11-22 | 주식회사 하이닉스반도체 | 반도체 소자의 다마신 패턴 형성방법 |
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- 2002-07-10 KR KR1020020040055A patent/KR100875057B1/ko active IP Right Grant
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20000043063A (ko) * | 1998-12-28 | 2000-07-15 | 김영환 | 반도체 소자의 금속 배선 형성 방법 |
KR20030089564A (ko) * | 2002-05-16 | 2003-11-22 | 주식회사 하이닉스반도체 | 반도체 소자의 다마신 패턴 형성방법 |
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