JP4703067B2 - IC chip mounting substrate manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a substrate for packaging IC chip that achieves optical communication having excellent connection reliability, and at the same time can contribute to the miniaturization of terminal equipment. SOLUTION: In the method for manufacturing a substrate for packaging IC chip, a substrate 1 for inserting optic elements and a package substrate 21 are manufactured for laminating, and at least following processes (1) to (3) should be performed. In an optic element packaging process (1), the optic elements are electrically connected to a conductor circuit on the package substrate after optic elements 38 and 39 are packaged onto the surface of the package substrate that is exposed from a through hole formed on the substrate for inserting optic elements. In a resin fill layer formation process (2), the through hole that is formed on the substrate for inserting optic elements is filled with a resin composition 41, and a resin fill layer is formed. In a solder resist layer formation process (3), a solder resist layer 34 is formed on the exposure surface of the substrate for inserting optic elements.

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing an IC chip mounting substrate.
[0002]
[Prior art]
In recent years, attention has been focused on optical fibers mainly in the communication field. In particular, in the IT (information technology) field, communication technology using optical fibers is required to develop a high-speed Internet network.
The optical fiber has features such as (1) low loss, (2) high bandwidth, (3) small diameter and light weight, (4) no induction, and (5) resource saving. Compared with communication systems using conventional metallic cables, the number of repeaters can be greatly reduced, making construction and maintenance easier, and making communication systems more economical and more reliable. Can be planned.
[0003]
In addition, optical fibers can simultaneously multiplex and transmit not only one wavelength of light but also many different wavelengths of light with a single optical fiber. It can be realized and can also support video services and the like.
[0004]
Therefore, in such network communication such as the Internet, optical communication using optical fibers is not only communication of the backbone network, but also communication between the backbone network and terminal equipment (PC, mobile, game, etc.) It has also been proposed to be used for communication between each other.
[0005]
As described above, when optical communication is used for communication between the backbone network and the terminal device, an IC that performs information (signal) processing in the terminal device operates with an electrical signal. Therefore, the terminal device includes an optical-to-electric converter, It is necessary to attach a device (hereinafter also referred to as an optical / electrical converter) that converts an optical signal and an electrical signal, such as an electrical-to-optical converter. Therefore, in a conventional terminal device, for example, a package substrate on which an IC chip is mounted, an optical component such as a light receiving element or a light emitting element that processes an optical signal, and the like are separately mounted, and an electrical wiring or an optical waveguide is connected to them, Signal transmission and signal processing were performed.
[0006]
[Problems to be solved by the invention]
In such a conventional terminal device, since the IC mounting package substrate and the optical component are separately mounted, the entire apparatus becomes large, which is a factor that hinders the miniaturization of the terminal device.
Further, in the conventional terminal device, since the distance between the IC mounting package substrate and the optical component is large, the electric wiring distance is long, and a signal error due to crosstalk noise or the like is likely to occur during signal transmission.
[0007]
[Means for Solving the Problems]
Accordingly, the present inventors have conducted extensive studies on a method of manufacturing an IC chip mounting substrate that can achieve optical communication with excellent connection reliability and contribute to downsizing of terminal devices. It is conceived that an IC chip mounting substrate that does not cause the above-described problems can be manufactured by mounting various optical components when manufacturing the substrate, and manufacturing the IC chip mounting substrate of the present invention having the following configuration. Completed the method.
[0008]
That is, the method for manufacturing an IC chip mounting substrate according to the present invention includes: (a) forming a conductor circuit on both surfaces of the substrate a and forming a through-hole that connects between the conductor circuits sandwiching the substrate a; A step, (b) an adhesive layer forming step of forming an adhesive layer on at least a part of the conductor circuit non-forming portion on one side of the substrate a on which the conductor circuit is formed, and (c) a substrate a on which the adhesive layer is formed A through hole forming step for forming a through hole in a part of the optical element insertion substrate,
(A) a first conductor circuit forming step for forming a conductor circuit on both surfaces of the substrate A; (B) an interlayer resin insulation layer having a via hole is formed on the substrate A on which the conductor circuit is formed; A package substrate produced through an interlayer resin insulation layer lamination step for forming a conductor circuit on the resin insulation layer, and a solder resist layer formation step for forming a solder resist layer on the outermost layer (C);
After bonding, at least the following steps (1) to (3) are performed.
(1) An optical element mounting step for electrically connecting the optical element and the conductor circuit of the package substrate after attaching the optical element to the surface of the package substrate exposed from the through hole formed in the optical element insertion substrate. ,
(2) a resin-filled layer forming step of filling a resin composition into a through-hole formed in the optical element insertion substrate and forming a resin-filled layer; and
(3) A solder resist layer forming step of forming a solder resist layer on the exposed surface of the optical element insertion substrate.
[0009]
In the step (1) in the method for manufacturing an IC chip mounting substrate of the present invention, it is desirable to electrically connect the optical element and the package substrate by wire bonding.
Further, the resin-filled layer formed in the step (2) of the method for manufacturing the IC chip mounting substrate has a transmittance of 90% or more of the communication wavelength light in the vertical direction between the upper surface and the lower surface. It is also desirable that the transmittance of light having a communication wavelength per 1 mm length is 90% or more.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
The method for producing an IC chip mounting substrate of the present invention includes: (a) a conductor circuit forming step of forming conductor circuits on both surfaces of the substrate a and forming through holes connecting between the conductor circuits sandwiching the substrate a; (B) an adhesive layer forming step of forming an adhesive layer on at least a part of the conductive circuit non-forming portion on one side of the substrate a on which the conductor circuit is formed; and (c) one of the substrates a on which the adhesive layer is formed. A substrate for inserting an optical element produced through a through-hole forming step for forming a through-hole in a portion;
(A) a first conductor circuit forming step for forming a conductor circuit on both surfaces of the substrate A; (B) an interlayer resin insulation layer having a via hole is formed on the substrate A on which the conductor circuit is formed; A package substrate produced through an interlayer resin insulation layer lamination step for forming a conductor circuit on the resin insulation layer, and a solder resist layer formation step for forming a solder resist layer on the outermost layer (C);
After bonding, at least the following steps (1) to (3) are performed.
(1) An optical element mounting step for electrically connecting the optical element and the conductor circuit of the package substrate after attaching the optical element to the surface of the package substrate exposed from the through hole formed in the optical element insertion substrate. ,
(2) a resin-filled layer forming step of filling a resin composition into a through-hole formed in the optical element insertion substrate and forming a resin-filled layer; and
(3) A solder resist layer forming step of forming a solder resist layer on the exposed surface of the optical element insertion substrate.
[0011]
The steps (1) to (3) do not have to be performed in this order, and the step (2) has to be performed after the step (1). The step (2) may be performed before the step (1) or the step (2).
[0012]
According to the method for manufacturing an IC chip mounting substrate of the present invention, it is possible to manufacture an IC chip mounting substrate that can achieve optical communication excellent in connection reliability and contribute to miniaturization of a terminal device.
[0013]
In the method for manufacturing an IC chip mounting substrate according to the present invention, after the optical element insertion substrate and the package substrate are separately manufactured, they are bonded together and further subjected to a predetermined process. Therefore, in the present specification, first, a method for manufacturing an optical element insertion substrate and a method for manufacturing a package substrate will be described separately in the order of steps, and then both are bonded to form an IC chip mounting substrate. The process will be described.
[0014]
In the production of the optical element insertion substrate, first, in the step (a), that is, a conductor circuit is formed on both surfaces of the substrate a and a through hole is formed to connect between the conductor circuits sandwiching the substrate a. A circuit formation process is performed.
Specifically, for example, after a through hole is formed in the substrate a by drilling, laser processing, or the like, a solid conductor layer is formed by performing an electroless plating process or the like on the entire surface of the substrate a including the wall surface of the through hole. Then, by etching the conductor layer in a pattern, a through hole connecting the conductor circuit and the conductor circuit sandwiching the substrate a can be formed.
In addition, after a through hole is formed in a substrate on which a solid conductor layer is formed in advance, an electroless plating process is performed on the wall surface of the through hole, and further, an etching process is performed on the conductor layer so that a conductor circuit and a through-hole are formed. A hole may be formed.
[0015]
In addition, after forming the through hole in the substrate a, a plating resist is formed on a part of the surface of the substrate a, and then only the electroless plating process or the electroless plating process is performed on the wall surface of the through hole and the plating resist non-forming portion. Alternatively, the conductor layer may be formed by performing electrolytic plating treatment or the like, and further, the conductor circuit and the through hole may be formed by removing the plating resist.
In this step, after the through hole is formed in the substrate a, it is desirable to perform desmear treatment on the through hole. Examples of the desmear treatment include chemical treatment using an oxidizing agent such as permanganic acid and chromic acid, and dry treatment using plasma.
[0016]
Examples of the substrate a include an epoxy resin, a polyester resin, a polyimide resin, a bismaleimide-triazine resin (BT resin), a phenol resin, and a resin in which a reinforcing material such as glass fiber is impregnated with these resins (for example, a glass epoxy). Resin), FR-4 substrate, FR-5 substrate and the like.
Further, a double-sided copper-clad laminate, a single-sided copper-clad laminate, an RCC substrate, or the like may be used as a substrate on which a solid conductor layer is formed.
In addition, using a conformal substrate or a substrate formed by an additive method as a substrate on which a conductor circuit is formed, a process for forming a through hole in the substrate and a process for forming a conductor layer on the wall surface are performed, A through hole may be formed.
[0017]
After forming the through hole, it is desirable to fill the through hole with a resin filler to form a resin filler layer. The resin filler can be filled using, for example, a mask having an opening formed in a portion corresponding to a through hole on a substrate and using a squeegee.
In addition, when filling the resin filler in the through hole, it is desirable to form a roughened surface on the wall surface of the through hole before filling. This is because the adhesion between the through hole and the resin filler layer is further improved.
[0018]
Examples of the resin filler include a resin composition containing an epoxy resin, a curing agent, and inorganic particles.
Although it does not specifically limit as said epoxy resin, At least 1 type selected from the group which consists of a bisphenol-type epoxy resin and a novolak-type epoxy resin is desirable.
The viscosity of bisphenol type epoxy resin can be adjusted without using a diluting solvent by selecting A type or F type resin, and novolac type epoxy resin has high strength, heat resistance and chemical resistance. This is because it is excellent in properties and does not decompose even in a strongly basic solution such as an electroless plating solution, and it is difficult to thermally decompose.
[0019]
As the bisphenol type epoxy resin, a bisphenol A type epoxy resin or a bisphenol F type epoxy resin is desirable, and a bisphenol F type epoxy resin is more desirable because it has a low viscosity and can be used without a solvent.
The novolac epoxy resin is preferably at least one selected from a phenol novolac epoxy resin and a cresol novolac epoxy resin.
[0020]
Further, a bisphenol type epoxy resin and a cresol novolac type epoxy resin may be mixed and used. In this case, the mixing ratio of the bisphenol type epoxy resin and the cresol novolac type epoxy resin is preferably 1/1 to 1/100 by weight.
[0021]
It does not specifically limit as a hardening | curing agent contained in the said resin filler, A conventionally well-known hardening | curing agent can be used, For example, an imidazole type hardening | curing agent, an acid anhydride hardening | curing agent, an amine type hardening | curing agent etc. are mentioned. Of these, imidazole-based curing agents are desirable, and in particular, liquid 1-benzyl-2-methylimidazole, 1-cyanoethyl-2-ethyl-4-methylimidazole, and 4-methyl-2- Ethylimidazole is desirable.
[0022]
Examples of the inorganic particles contained in the resin filler include aluminum compounds such as alumina and aluminum hydroxide, calcium compounds such as calcium carbonate and calcium hydroxide, potassium compounds such as potassium carbonate, magnesia, dolomite, and basic. Examples thereof include magnesium compounds such as magnesium carbonate and talc, silicon compounds such as silica and zeolite, and titanium compounds such as titania. These may be used alone or in combination of two or more.
The inorganic particles may be coated with a silane coupling agent or the like. This is because the adhesion between the inorganic particles and the epoxy resin is improved.
[0023]
The content ratio of the inorganic particles in the resin composition is preferably 10 to 80% by weight, and more preferably 20 to 70% by weight. This is because the thermal expansion coefficient can be matched with the substrate or the like within this range.
[0024]
Moreover, the shape of the said inorganic particle is not specifically limited, A spherical shape, an elliptical spherical shape, a crushed shape, a polyhedron shape, etc. are mentioned. Of these, spherical and elliptical spheres are desirable. This is because the occurrence of cracks due to the shape of the particles can be suppressed.
As for the average particle diameter of the said inorganic particle, 0.01-5.0 micrometers is desirable.
[0025]
Moreover, in the said resin composition, other thermosetting resins, thermoplastic resins, etc. may be contained besides the above-mentioned epoxy resin.
Examples of the thermosetting resin include polyimide resin and phenol resin, and examples of the thermoplastic resin include polytetrafluoroethylene (PTFE), tetrafluoroethylene hexafluoropropylene copolymer (FEP). ) Fluorine resin such as tetrafluoroethylene perfluoroalkoxy copolymer (PFA), polyethylene terephthalate (PET), polysulfone (PSF), polyphenylene sulfide (PPS), thermoplastic polyphenylene ether (PPE), polyether sulfone (PES), polyether imide (PEI), polyphenylene sulfone (PPES), polyethylene naphthalate (PEN), polyether ether ketone (PEEK), polyolefin resin and the like. These may be used alone or in combination of two or more.
Note that these resins may be used instead of the epoxy resin.
[0026]
Moreover, in this conductor circuit formation process, after forming a resin filler layer in a through hole, it is desirable to form a lid plating layer that covers an exposed surface of the resin filler layer from the through hole. By forming the lid plating layer, it is possible to form a solder pad not only on the land of the through hole but also on the lid plating layer, so that the degree of freedom in design is further improved.
[0027]
The lid plating layer is formed by, for example, forming a conductor layer on the surface of the substrate including the exposed surface of the resin filler layer, forming an etching resist on the lid plating layer forming portion, and then performing an etching process or performing lid plating in advance. It can be formed by forming a plating resist in the layer non-forming portion and performing plating treatment and removal of the plating resist.
[0028]
Accordingly, in this conductor circuit forming step, when forming a lid plating layer on the through hole, the conductor circuit and the through hole are simultaneously formed and the lid plating layer is formed by performing the following procedure. be able to.
That is, first, a through hole is formed in the substrate, a conductor layer is formed on the surface of the substrate including the wall surface of the through hole, and then a resin filler is filled in the through hole in which the conductor layer is formed on the wall surface. To do. Further, after a conductor layer is formed by plating on the exposed surface of the resin filler and the conductor layer formed on the substrate surface, the conductor layers in the conductor circuit non-formed part and the through hole non-formed part are removed by etching. Thereby, formation of a conductor circuit and a through hole, and formation of a lid plating layer can be performed simultaneously.
[0029]
Next, the above-described step (b), that is, an adhesive layer forming step for forming an adhesive layer on at least a part of the conductor circuit non-formed portion on one side of the substrate a on which the conductor circuit is formed is performed. In the present specification, the land portion of the through hole is included in the conductor circuit. Accordingly, the land portion of the through hole does not correspond to the conductor circuit non-formation portion.
In this step, an adhesive layer is formed on all or part of the conductor circuit non-forming portion on the side to be bonded to the package substrate of the substrate a. What is necessary is just to apply | coat the said adhesive bond layer so that sufficient adhesiveness with a package substrate may be acquired. Therefore, an adhesive layer may or may not be formed in the portion where the through hole is formed in the step (c) described later.
[0030]
As the adhesive, for example, a thermosetting resin, a thermoplastic resin, a photosensitive resin, a resin in which a part of a thermosetting group is sensitized, or a composite thereof can be used.
Specific examples include epoxy resin, phenol resin, polyimide resin, BT resin, and the like. Moreover, the adhesive previously shape | molded in the sheet form may be used and a prepreg may be used.
[0031]
Next, the step (c), that is, the through hole forming step for forming a through hole in a part of the substrate a on which the adhesive layer is formed is performed. In the through hole formed here, an optical element is disposed in a later step.
The through hole can be formed by, for example, router processing.
Moreover, although the formation position of the said through-hole is not specifically limited, Usually, it forms in the center of a board | substrate.
[0032]
In addition, after forming the through-hole in the through-hole forming step, a chemical treatment or a polishing treatment may be performed in order to remove burrs or the like existing on the through-hole wall surface.
The said chemical | medical solution process can be performed using the oxidizing agent which consists of aqueous solutions, such as chromic acid and permanganate, for example.
The substrate for inserting an optical element can be manufactured through the steps (a) to (c).
[0033]
Next, a method for manufacturing a package substrate will be described.
In manufacturing the package substrate, first, the step (A), that is, the first conductor circuit forming step for forming conductor circuits on both surfaces of the substrate A is performed.
This step can be performed, for example, by the same method as the step (a) of manufacturing the optical element insertion substrate described above.
In addition, as the board | substrate A, the thing similar to the board | substrate a mentioned above can be used, for example.
[0034]
Further, if necessary, through holes for connecting between the conductor circuits sandwiching the substrate A may be formed.
The through hole is formed by forming a through hole in the substrate A by drilling, laser processing or the like and then subjecting the wall surface of the through hole to electroless plating. Further, when a through hole is formed, it is desirable to fill the through hole with a resin filler. The resin filler can be filled using, for example, a mask having an opening formed in a portion corresponding to a through hole on a substrate and using a squeegee.
[0035]
Further, the surface of the conductor circuit (including the land surface of the through hole) may be roughened. This is because by making the surface of the conductor circuit a roughened surface, it is possible to improve the adhesion with the interlayer resin insulating layer formed in a later step.
Examples of the roughening treatment include blackening (oxidation) -reduction treatment, etching treatment using an etchant containing a cupric complex and an organic acid salt, and treatment by Cu—Ni—P needle-like alloy plating. Etc.
The roughening process may be performed before the resin filler is filled in the through hole, and a roughened surface may be formed on the wall surface of the through hole. This is because the adhesion between the through hole and the resin filler is improved.
[0036]
Examples of the resin filler that fills the through hole include the same resin filler that is used when filling the through hole in the step of manufacturing the optical element insertion substrate.
[0037]
Next, in the step (B), that is, an interlayer resin insulation layer having a via hole is formed on the substrate A on which the conductor circuit is formed, and an interlayer resin for forming a conductor circuit on the interlayer resin insulation layer An insulating layer lamination process is performed.
Specifically, it can be performed, for example, through the following steps (i) to (vi).
That is, (i) First, an uncured resin layer made of a thermosetting resin or a resin composite is formed on a substrate A on which a conductor circuit is formed, or a resin layer made of a thermoplastic resin is formed.
The uncured resin layer may be formed by applying uncured resin with a roll coater, curtain coater, or the like, or may be formed by thermocompression bonding of an uncured (semi-cured) resin film. . Furthermore, you may affix the resin film in which metal layers, such as copper foil, were formed in the single side | surface of an uncured resin film.
The resin layer made of a thermoplastic resin is preferably formed by thermocompression bonding a resin molded body formed into a film shape.
[0038]
In the case of applying the uncured resin, the resin is applied and then heat treatment is performed.
By performing the heat treatment, the uncured resin can be thermoset.
In addition, you may perform the said thermosetting after forming the opening for via holes mentioned later.
[0039]
Specific examples of the thermosetting resin used in the formation of such a resin layer include, for example, epoxy resins, phenol resins, polyimide resins, polyester resins, bismaleimide resins, polyolefin resins, polyphenylene ether resins, and the like.
[0040]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0041]
Examples of the polyolefin resin include polyethylene, polystyrene, polypropylene, polyisobutylene, polybutadiene, polyisoprene, cycloolefin resin, and copolymers of these resins.
[0042]
Examples of the thermoplastic resin include phenoxy resin, polyether sulfone, and polysulfone.
Further, the composite of the thermosetting resin and the thermoplastic resin (resin composite) is not particularly limited as long as it includes a thermosetting resin and a thermoplastic resin. Specific examples thereof include, for example, Examples thereof include a resin composition for forming a roughened surface.
[0043]
Examples of the roughened surface-forming resin composition include, in an uncured heat-resistant resin matrix that is hardly soluble in a roughened liquid consisting of at least one selected from an acid, an alkali, and an oxidizing agent. And a material in which a substance soluble in a roughening liquid comprising at least one selected from oxidizing agents is dispersed.
As used herein, the terms “slightly soluble” and “soluble” refer to those having a relatively high dissolution rate as “soluble” for convenience when immersed in the same roughening solution for the same time. The slow one is called “slightly soluble” for convenience.
[0044]
The heat resistant resin matrix is preferably one that can maintain the shape of the roughened surface when the roughened surface is formed on the interlayer resin insulating layer using the roughening liquid, for example, a thermosetting resin, a thermoplastic resin. Examples thereof include resins and composites thereof. Photosensitive resin may also be used. This is because the opening can be formed by exposure and development processing in a step of forming a via hole opening to be described later.
[0045]
Examples of the thermosetting resin include an epoxy resin, a phenol resin, a polyimide resin, a polyolefin resin, and a fluororesin. Further, resins obtained by imparting photosensitivity to these thermosetting resins, that is, resins obtained by (meth) acrylation reaction of thermosetting groups using methacrylic acid or acrylic acid may be used. Specifically, (meth) acrylate of an epoxy resin is desirable, and an epoxy resin having two or more epoxy groups in one molecule is more desirable.
[0046]
Examples of the thermoplastic resin include phenoxy resin, polyether sulfone, polysulfone, polyphenylene sulfone, polyphenylene sulfide, polyphenyl ether, polyether imide, and the like. These may be used alone or in combination of two or more.
[0047]
Examples of the soluble substance include inorganic particles, resin particles, metal particles, rubber particles, liquid phase resins, and liquid phase rubbers. These may be used alone or in combination of two or more.
[0048]
Examples of the inorganic particles include aluminum compounds such as alumina and aluminum hydroxide; calcium compounds such as calcium carbonate and calcium hydroxide; potassium compounds such as potassium carbonate; magnesium compounds such as magnesia, dolomite, basic magnesium carbonate, and talc. A silicon compound such as silica and zeolite; and a titanium compound such as titania. These may be used alone or in combination of two or more.
The alumina particles can be dissolved and removed with hydrofluoric acid, and calcium carbonate can be dissolved and removed with hydrochloric acid. Sodium-containing silica and dolomite can be dissolved and removed with an alkaline aqueous solution.
[0049]
Examples of the resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When the resin particles are immersed in a roughening solution made of at least one selected from an acid, an alkali, and an oxidizing agent, the heat resistance It is not particularly limited as long as it has a faster dissolution rate than the resin matrix. Specifically, for example, amino resins (melamine resins, urea resins, guanamine resins, etc.), epoxy resins, phenol resins, phenoxy resins, polyimide resins, Examples include those made of polyphenylene resin, polyolefin resin, fluororesin, bismaleimide-triazine resin and the like. These may be used alone or in combination of two or more.
The resin particles must be previously cured. If not cured, the resin particles are dissolved in a solvent that dissolves the resin matrix, so they are uniformly mixed, and only the resin particles cannot be selectively dissolved and removed with an acid or an oxidizing agent. is there.
[0050]
As said metal particle, what consists of gold, silver, copper, tin, zinc, stainless steel, aluminum, nickel, iron, lead etc. is mentioned, for example. These may be used alone or in combination of two or more.
In addition, the metal particles may be coated with a resin or the like in order to ensure insulation.
[0051]
(Ii) Next, when forming an interlayer resin insulation layer using a thermosetting resin or a resin composite as the material, the uncured resin layer is subjected to a curing treatment and a via hole opening is formed. And an interlayer resin insulation layer.
The via hole opening is preferably formed by laser processing. The laser treatment may be performed before the curing treatment or after the curing treatment.
When an interlayer resin insulating layer made of a photosensitive resin is formed, a via hole opening may be provided by performing exposure and development processes. In this case, the exposure and development processes are performed before the curing process.
[0052]
When an interlayer resin insulation layer using a thermoplastic resin as the material is formed, a via hole opening can be formed in the resin layer made of the thermoplastic resin by laser processing to form an interlayer resin insulation layer. .
[0053]
At this time, examples of the laser to be used include a carbon dioxide laser, an excimer laser, a UV laser, and a YAG laser. These may be used properly in consideration of the shape of the via hole opening to be formed.
[0054]
In the case of forming the via hole openings, a large number of via hole openings can be formed at a time by irradiating a laser beam by a hologram type excimer laser through a mask.
In addition, when a via hole opening is formed using a short pulse carbon dioxide laser, there is little resin residue in the opening, and damage to the resin at the periphery of the opening is small.
[0055]
When laser light is irradiated through the optical system lens and the mask, a large number of via hole openings can be formed at one time.
This is because laser light having the same intensity and the same irradiation angle can be simultaneously irradiated to a plurality of portions through the optical system lens and the mask.
[0056]
(Iii) Next, a roughened surface is formed on the surface of the interlayer resin insulating layer including the inner wall of the via hole opening using an acid or an oxidizing agent as necessary.
This roughened surface is formed in order to improve the adhesion between the interlayer resin insulation layer and the thin film conductor layer formed thereon, and provides sufficient adhesion between the interlayer resin insulation layer and the thin film conductor layer. If there is a property, it may not be formed.
[0057]
Examples of the acid include sulfuric acid, nitric acid, hydrochloric acid, phosphoric acid, formic acid, and examples of the oxidizing agent include permanganates such as chromic acid, chromium sulfuric acid, and sodium permanganate.
In addition, after the roughened surface is formed, it is desirable to neutralize the surface of the interlayer resin insulation layer using an aqueous solution such as an alkali or a neutralizing solution.
This is because the next step can be prevented from being affected by an acid or an oxidizing agent.
In addition, the roughened surface may be formed using plasma treatment or the like.
[0058]
The maximum roughness Rmax of the roughened surface is preferably 0.1 to 20 μm. This is because if the Rmax exceeds 20 μm, the roughened surface itself is easily damaged or peeled off, and if the Rmax is less than 0.1 μm, sufficient adhesion to the conductor circuit may not be obtained. In particular, when the conductor circuit is formed by a semi-additive method, the maximum roughness Rmax is preferably 0.1 to 5 μm. This is because sufficient adhesion with the thin film conductor layer can be ensured and the thin film conductor layer can be easily removed.
[0059]
(Iv) Next, a thin film conductor layer is formed on the surface of the interlayer resin insulation layer provided with the via hole opening.
The thin film conductor layer can be formed using a method such as electroless plating, sputtering, or vapor deposition. When the roughened surface is not formed on the surface of the interlayer resin insulating layer, the thin film conductor layer is preferably formed by sputtering.
In addition, when forming a thin film conductor layer by electroless plating, the catalyst is previously provided to the to-be-plated surface. Examples of the catalyst include palladium chloride.
[0060]
The thickness of the thin film conductor layer is not particularly limited, but when the thin film conductor layer is formed by electroless plating, 0.6 to 1.2 μm is desirable, and when formed by sputtering, 0.1 to 0.1 μm is preferable. 1.0 μm is desirable.
Examples of the material for the thin film conductor layer include Cu, Ni, P, Pd, Co, and W. Of these, Cu and Ni are desirable.
[0061]
(V) Next, a plating resist is formed on a part of the thin film conductor layer by using a dry film, and then electrolytic plating is performed using the thin film conductor layer as a plating lead. Form.
[0062]
Also, in this step, the via hole opening may be filled with electrolytic plating to form a via-hole structure, and a via hole having a depression on the upper surface is formed once, and then the conductivity is formed in the depression. A field via structure may be formed by filling the paste. Alternatively, after forming a via hole having a depression on the upper surface, the depression may be filled with a resin filler, and a lid plating layer may be further formed thereon to form a via hole having a flat upper surface. By making the via hole structure a field via structure, a via hole can be formed immediately above the via hole.
[0063]
(Vi) Further, the plating resist is peeled off, and the thin film conductor layer existing under the plating resist is removed by etching to form an independent conductor circuit. Examples of the etchant include sulfuric acid-hydrogen peroxide aqueous solution, persulfate aqueous solution such as ammonium persulfate, ferric chloride, cupric chloride, hydrochloric acid and the like. Moreover, you may use the mixed solution containing the cupric complex mentioned above and organic acid as etching liquid.
[0064]
Moreover, after forming a plating resist on the above-described thin film conductor layer and forming an electrolytic plating layer on the plating resist non-forming portion, the following method is used instead of the method of removing the plating resist and the thin film conductor layer. Thus, a conductor circuit may be formed.
That is, after an electrolytic plating layer is formed on the entire surface of the thin film conductor layer, an etching resist is formed on a part of the electrolytic plating layer using a dry film, and then the electrolytic plating layer under the etching resist non-forming portion and An independent conductor circuit may be formed by removing the thin film conductor layer by etching and further removing the etching resist.
[0065]
By using such a method, an interlayer resin insulation layer having a via hole can be formed, and an interlayer resin insulation layer laminating step for forming a conductor circuit on the interlayer resin insulation layer can be performed. In the production method of the present invention, this interlayer resin insulation layer lamination step was performed only once. However, depending on the IC chip mounting substrate to be produced, the interlayer resin insulation layer lamination step may be repeated a plurality of times, Two or more resin insulation layers and conductor circuits may be laminated and formed.
[0066]
Next, the step (C), that is, a solder resist layer forming step of forming a solder resist layer on the outermost layer is performed.
Specifically, an uncured solder resist composition is applied by a roll coater, a curtain coater, or the like, or a solder resist composition formed into a film shape is pressure-bonded, and then subjected to a curing treatment to form a solder resist layer. Form.
[0067]
The solder resist layer can be formed using, for example, a solder resist composition containing a polyphenylene ether resin, a polyolefin resin, a fluororesin, a thermoplastic elastomer, an epoxy resin, a polyimide resin, or the like.
[0068]
Examples of solder resist compositions other than those described above include, for example, (meth) acrylates of novolak epoxy resins, imidazole curing agents, bifunctional (meth) acrylic acid ester monomers, and (meth) acrylic acid having a molecular weight of about 500 to 5,000. Examples include paste polymers containing ester polymers, thermosetting resins composed of bisphenol-type epoxy resins, photosensitive monomers such as polyvalent acrylic monomers, glycol ether solvents, and the viscosity at 25 ° C. It is desirable that the pressure is adjusted to 1 to 10 Pa · s.
The solder resist composition may contain an elastomer or an inorganic filler.
Moreover, you may use a commercially available soldering resist composition as a soldering resist composition.
[0069]
In addition, solder bump forming openings are formed in the solder resist layer as necessary by laser processing or exposure development processing. In this case, examples of the laser used include those similar to the laser used when forming the above-described via hole opening.
[0070]
Next, if necessary, a metal layer is formed on the surface of the conductor circuit exposed at the bottom surface of the solder bump forming opening.
The metal layer can be formed by coating the surface of the conductor circuit with a corrosion-resistant metal such as nickel, palladium, gold, silver, or platinum.
Specifically, it is desirable to form with a metal such as nickel-gold, nickel-silver, nickel-palladium, nickel-palladium-gold.
The solder pad can be formed by using, for example, a method such as plating, vapor deposition, or electrodeposition. Among these, plating is preferable because the uniformity of the coating layer is excellent.
Further, in the solder resist layer formed in this step, an alignment mark or the like used for bonding to the optical element insertion substrate may be formed in a later-described step.
A package substrate can be manufactured through such steps (A) to (C).
[0071]
Next, the optical element insertion substrate has the optical element insertion substrate produced through the steps (a) to (c) and the package substrate produced through the steps (A) to (C). A method of forming an IC chip mounting substrate through the steps (1) to (3) after bonding through the agent layer will be described.
[0072]
The bonding of the optical element insertion substrate and the package substrate can be performed using, for example, a pin laminating method or a mass laminating method.
Specifically, after aligning the two, the temperature is raised to a temperature at which the adhesive layer is softened (usually about 60 to 200 ° C.), and then pressed at a pressure of about 1 to 10 MPa. The element insertion substrate and the package substrate are bonded together.
[0073]
First, after the optical element is attached to the surface of the package substrate exposed from the through hole formed in the optical element insertion substrate, that is, the optical element and the conductor circuit of the package substrate are electrically connected. The optical element mounting process to be connected is performed.
[0074]
As optical elements to be mounted in this process, for example, light receiving elements such as PD (photodiode) and APD (avalanche photodiode), LD (semiconductor laser), DFB-LD (distributed feedback type-semiconductor laser), LED (light emission). Light-emitting elements such as diodes).
[0075]
Examples of the material of the light receiving element include Si, Ge, InGaAs, and the like. Of these, InGaAs is desirable because of its excellent light receiving sensitivity.
Examples of the material of the light emitting element include a compound of gallium, arsenic and phosphorus (GaAsP), a compound of gallium, aluminum and arsenic (GaAlAs), a compound of gallium and arsenic (GaAs), a compound of indium, gallium and arsenic. (InGaAs), indium, gallium, arsenic and phosphorus compounds (InGaAsP). These may be properly used in consideration of the communication wavelength. For example, when the communication wavelength is 0.85 μm band, GaAlAs can be used, and when the communication wavelength is 1.3 μm band or 1.55 μm band. InGaAs or InGaAsP can be used.
[0076]
The optical element can be attached by, for example, a eutectic bonding method, a solder bonding method, a resin bonding method, or the like. Moreover, you may attach an optical element using a silver paste and a gold paste.
In the above resin bonding method, a thermosetting resin such as an epoxy resin or a polyimide resin is used as a main ingredient, and a paste containing a curing agent, a filler, a solvent, etc. in addition to these resin components is applied on a package substrate, and then optical After placing the element on the paste, the optical element is attached by heat-curing the paste.
The paste can be applied by, for example, a dispensing method, a stamping method, a screen printing method, or the like.
In the case of using a silver paste, the silver paste is applied on the package substrate, and then the optical element is placed on the paste, and then the silver paste is baked to attach the optical element.
[0077]
As a method of electrically connecting the optical element and the conductor circuit of the package substrate, it is desirable to use wire bonding. This is because the degree of freedom of design when attaching the optical element is great and it is economically advantageous.
As the wire bonding, a conventionally known method, that is, a nail head bonding method or a wedge bonding method can be used.
The optical element and the package substrate may be connected by tape bonding or flip chip bonding.
[0078]
Next, the step (2), that is, the resin filling layer forming step of filling the resin composition into the through-hole formed in the optical element insertion substrate and forming the resin filling layer is performed.
Examples of the resin composition include a thermosetting resin, a thermoplastic resin, a photosensitive resin, a resin in which a part of the thermosetting resin is sensitized, a composite of these, and the like as resin components. Specific examples of the resin component include an epoxy resin, a phenol resin, a polyimide resin, an olefin resin, and a BT resin.
In addition to the resin component, the resin composition may contain particles such as resin particles, inorganic particles, and metal particles. By including these particles, the thermal expansion coefficient can be matched between the resin-filled layer, the substrate, the solder resist layer, the interlayer resin insulating layer, and the like. It can also be granted.
[0079]
Examples of the resin particles include a thermosetting resin, a thermoplastic resin, a photosensitive resin, a resin in which a part of the thermosetting resin is made photosensitive, a resin composite of a thermosetting resin and a thermoplastic resin, Examples include a composite of a photosensitive resin and a thermoplastic resin.
[0080]
Specifically, for example, thermosetting resins such as epoxy resins, phenol resins, polyimide resins, bismaleimide resins, polyphenylene resins, polyolefin resins, fluororesins; thermosetting groups of these thermosetting resins (for example, epoxy resins) (Epoxy group) in which methacrylic acid or acrylic acid is reacted to give an acrylic group; phenoxy resin, polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), Examples thereof include thermoplastic resins such as polyphenyl ether (PPE) and polyetherimide (PI); photosensitive resins such as acrylic resins.
Moreover, the resin composite of the said thermosetting resin and the said thermoplastic resin, the resin to which the said acrylic group was provided, the said photosensitive resin, and the said thermoplastic resin can also be used.
Moreover, as the resin particles, resin particles made of rubber can be used.
[0081]
Examples of the inorganic particles include aluminum compounds such as alumina and aluminum hydroxide, calcium compounds such as calcium carbonate and calcium hydroxide, potassium compounds such as potassium carbonate, magnesium compounds such as magnesia, dolomite, and basic magnesium carbonate. And silicon compounds such as silica and zeolite, and titanium compounds such as titania.
Moreover, what consists of phosphorus or a phosphorus compound can also be used as said inorganic particle.
[0082]
Examples of the metal particles include Au, Ag, Cu, Pd, Ni, Pt, Fe, Zn, Pb, Al, Mg, and Ca.
These resin particles, inorganic particles, and metal particles may be used alone or in combination of two or more.
[0083]
Moreover, the shape of the said particle | grain is not specifically limited, For example, spherical shape, elliptical spherical shape, crushed shape, polyhedral shape etc. are mentioned.
The particle size of the particles (the length of the longest part of the particles) is preferably shorter than the wavelength of communication light. This is because if the particle size is longer than the wavelength of communication light, transmission of an optical signal may be hindered.
[0084]
The method for filling the resin composition is not particularly limited, and for example, a method such as printing or potting can be used. Moreover, you may fill what was made into the tablet shape using a plunger. Moreover, after filling the resin-filled layer, a curing process or the like is performed as necessary.
[0085]
In addition, the resin-filled layer formed in this step desirably has a transmittance of 90% or more for the communication wavelength light in the vertical direction between the upper surface and the lower surface. This is because if the transmittance is less than 90%, transmission of communication light is hindered, and inconvenience may occur in communication of optical signals via the optical element.
In the present specification, the transmittance (%) of the communication wavelength light in the vertical direction between the upper surface and the lower surface of the resin-filled layer is the intensity of the incident light in the vertical direction to the resin-filled layer.₁The intensity of light that has passed through the resin-filled layer is expressed as I₂Is a value calculated from the following formula (1).
[0086]
Transmittance (%) = (I₂/ I₁) × 100 (1)
[0087]
In addition, it is desirable that the resin-filled layer has a transmittance of light having a communication wavelength per 1 mm length of 90% or more.
In consideration of the thickness of the resin-filled layer formed in this step, the resin-filled layer having the transmittance in the above range is sufficiently excellent in transmission of communication light.
[0088]
In this specification, the transmittance (%) of communication wavelength light per 1 mm length is the strength I₃Is incident on the resin-filled layer, and when the light passes through the resin-filled layer by 1 mm, the intensity of the emitted light is I₄Is a value calculated by the following equation (2).
[0089]
Transmittance (%) = (I₄/ I₃) × 100 (2)
[0090]
In addition, when filling the resin composition in this step, different resin compositions may be filled in a plurality of times to form a resin layer composed of a plurality of layers in the through hole.
Specifically, for example, in a region up to the height of the light receiving surface of the light receiving element and the light emitting surface of the light emitting element, a resin composition excellent in properties for protecting wire bonding and its connection area, and particularly excellent in heat resistance. For example, a resin-filled layer is formed in a region higher than the light-receiving surface and the light-emitting surface using a resin composition that is particularly excellent in transmission of communication light.
[0091]
Furthermore, in this step, it is desirable that the exposed surface of the resin composition exposed from the through hole is subjected to a polishing process to flatten the exposed surface. This is because by flattening the exposed surface, there is less possibility that transmission of communication light is hindered.
The polishing treatment can be performed by, for example, buffing, polishing with sandpaper, mirror polishing, clean polishing, lapping, or the like. Further, chemical polishing using an acid, an oxidizing agent, a chemical solution, or the like may be performed. Moreover, you may perform a grinding | polishing process combining 2 or more types of these methods.
[0092]
Further, after forming the resin-filled layer, if necessary, a through hole penetrating the optical element insertion substrate and the package substrate may be formed.
Specifically, first, a through-hole through hole that penetrates the optical element insertion substrate and the package substrate is formed by drilling, laser processing, or the like. Next, a thin film conductor layer is formed on the exposed surface of the optical element insertion substrate including the wall surface of the through hole for through holes and the exposed surface of the package substrate by electroless plating, sputtering, or the like. Furthermore, after forming a plating resist on the substrate having a thin film conductor layer formed on the surface, an electrolytic plating layer is formed on the plating resist non-forming portion, and then the plating resist and the thin film conductor under the plating resist are formed. By removing the layer, a through hole penetrating the optical element insertion substrate and the package substrate can be formed.
[0093]
Moreover, after forming a plating resist as described above, instead of the method of forming an electrolytic plating layer, an electrolytic plating layer is formed on the entire surface of the thin film conductor layer, and then an etching resist or a solder plating layer is formed on the electrolytic plating layer. Further, a through-hole penetrating the optical element insertion substrate and the package substrate can be formed even by using a method of performing an etching process.
In addition, after forming a through hole, it is desirable to fill the through hole with a resin filler.
Further, when forming a through hole penetrating the optical element insertion substrate and the package substrate, the through hole may be formed before mounting the optical element or before forming the resin filling layer. .
[0094]
Next, the step (3), that is, a solder resist layer forming step for forming a solder resist layer on the exposed surface of the optical element insertion substrate is performed.
In this step, specifically, an uncured solder resist composition is applied by a roll coater, a curtain coater, or the like, or a solder resist composition formed into a film shape is pressure-bonded and then subjected to a curing treatment. A solder resist layer is formed.
As said solder resist composition, the thing similar to the solder resist composition used when producing a package board | substrate can be used, for example.
[0095]
In this solder resist layer forming step, it is not necessary to form a solder resist layer on the resin-filled layer formed in the step (2).
In addition, since the solder resist layer is already formed on the exposed surface of the package substrate before performing this step, it is not necessary to form the solder resist layer in this step.
[0096]
In addition, solder bump forming openings are formed in the solder resist layer as necessary by laser processing or exposure development processing. In this case, examples of the laser used include those similar to the laser used when forming the above-described via hole opening.
[0097]
Further, as described above, this solder resist layer forming step need not be performed after performing the steps (1) and (2), but before performing the step (1), that is, the optical element mounting step. It may be performed before the step (2), that is, the resin-filled layer forming step. In addition, when performing this soldering resist layer formation process before performing said process of (1) and (2), the through-hole formed in order to mount an optical element is formed in the exposed surface of the optical element insertion board | substrate. Wall surfaces are not included.
Further, when the through hole penetrating the optical element insertion substrate and the package substrate as described in the step (2) is formed, the solder resist layer forming step is performed after the through hole is formed. .
[0098]
Next, if necessary, a metal layer is formed on the surface of the conductor circuit exposed at the bottom surface of the solder bump forming opening.
The metal layer can be formed by coating the surface of the conductor circuit with a corrosion-resistant metal such as nickel, palladium, gold, silver, or platinum.
Specifically, it is desirable to form with a metal such as nickel-gold, nickel-silver, nickel-palladium, nickel-palladium-gold.
Moreover, although the said metal layer can be formed using methods, such as plating, vapor deposition, and electrodeposition, for example, plating is desirable from the point that the uniformity of a coating layer is excellent. This metal layer serves as a solder pad when forming solder bumps and the like in a later process.
[0099]
Further, if necessary, the solder bump forming opening is filled with solder paste through a mask in which an opening is formed in a portion corresponding to the solder bump forming opening, and then reflowed for flip chip use. Solder bumps and BGA (Ball Grid Array) solder bumps are formed.
An IC chip mounting substrate can be manufactured through such a series of steps.
[0100]
The IC chip mounting substrate manufactured by the manufacturing method of the present invention is usually mounted with an IC chip after manufacturing.
For example, when the flip-chip solder bump is formed, the IC chip is flip-chip mounted through the solder bump, and then the IC chip and the IC chip are mounted as necessary. This is performed by sealing with a resin substrate.
Further, the IC chip may be mounted by wire bonding. Of course, in this case, it is not necessary to form solder bumps for flip chip.
[0101]
In the above-described method for manufacturing an IC chip mounting substrate according to the present invention, flip chip solder bumps for mounting the IC chip and BGA for connecting the IC chip mounting substrate to another substrate (such as a motherboard). However, the two types of solder bumps may not be formed in the same process. For example, first, only the flip chip solder bump is formed and the solder bump is interposed. After mounting the IC chip, BGA solder bumps may be formed using solder paste or solder balls.
[0102]
【Example】
Hereinafter, the present invention will be described in more detail.
Example 1
A. Fabrication of optical element substrate
[0103]
(A) Preparation of resin filler
100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell Co., Ltd., molecular weight: 310, YL983U), SiO having an average particle diameter of 1.6 μm and a maximum particle diameter of 15 μm or less coated with a silane coupling agent on the surface₂When 72 parts by weight of spherical particles (manufactured by Adtech, CRS 1101-CE) and 1.5 parts by weight of a leveling agent (Perenol S4, manufactured by San Nopco) are placed in a container and stirred and mixed, the viscosity is 30 to 1 at 23 ± 1 ° C. A 60 Pa · s resin filler was prepared.
As the curing agent, 6.5 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) was used.
[0104]
(B) Manufacturing of optical element insertion substrate
(1) A double-sided copper-clad laminate in which 18 μm copper foil 8 is laminated on both sides of an insulating substrate 1 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.8 mm was used as a starting material ( FIG. 1 (a)). First, the copper-clad laminate was drilled and subjected to electroless plating to form a conductor layer 12 on the surface (including the wall surface of the through hole) (see FIG. 1B).
[0105]
(2) Next, the substrate 1 on which the conductor layer 12 is formed is washed with water and dried, followed by NaOH (10 g / l), NaClO.₂(40 g / l), Na₃PO₄Blackening treatment using an aqueous solution containing (6 g / l) as a blackening bath (oxidation bath), and NaOH (10 g / l), NaBH₄A reduction treatment using an aqueous solution containing (6 g / l) as a reduction bath was performed to form a roughened surface (not shown) on the surface of the conductor layer 12.
[0106]
(3) Next, after the resin filler described in the above (a) is prepared, the resin filler 10 ′ is placed in the through hole in which the conductor layer 12 is formed on the wall surface within 24 hours after the preparation by the following method. Layers were formed.
That is, the resin filler was pushed into the through-hole using a squeegee and then dried at 100 ° C. for 20 minutes (see FIG. 1C).
[0107]
(4) The exposed surface of the layer of the resin filler 10 'and the conductor layer are subjected to belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.) The surface of No. 12 was polished so as to be flat, and then buffed to remove scratches due to the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate.
Next, heat treatment was performed at 100 ° C. for 1 hour, 120 ° C. for 3 hours, 150 ° C. for 1 hour, and 180 ° C. for 7 hours to form a resin filler layer 10 (see FIG. 1D).
[0108]
(5) Next, a conductive layer 14 was formed by performing electroless plating on one side of the substrate on which the conductive layer 12 was formed (see FIG. 1 (e)).
In addition, a palladium catalyst is provided in advance on the surface on which the conductor layer 14 is formed, and a plating resist is formed on the surface on which the conductor layer 14 is not formed, whereby the conductor layer is formed on one surface of the substrate. 14 was formed.
[0109]
(6) An etching resist (not shown) is formed on a portion corresponding to a portion where a conductor circuit (including a land portion of a through hole) is formed on the substrate on which the conductor layer 12 or the conductor layer 14 is formed, and then an etching process is performed. As a result, a through-hole 6 having a resin filler layer 10 formed therein and a lid plating layer 16 formed thereon and a conductor circuit (not shown) were formed (see FIG. 1 (f)). ).
[0110]
The etching resist is formed by pasting a commercially available photosensitive dry film and placing a mask on it to 100 mJ / cm.²And developed with a 0.8% aqueous sodium carbonate solution.
Etching was performed using a mixed solution of sulfuric acid and hydrogen peroxide.
[0111]
(7) Next, the adhesive layer (not shown) was formed by apply | coating an epoxy resin-type adhesive agent to the conductor circuit non-formation part of the one side of a board | substrate.
(8) Further, a through hole 9 was formed in the center of the substrate by router processing to form an optical element insertion substrate (see FIG. 1 (g)).
[0112]
B. Fabrication of package substrate
(A) Preparation of resin film for interlayer resin insulation layer
30 parts by weight of bisphenol A type epoxy resin (epoxy equivalent 469, Epicoat 1001 manufactured by Yuka Shell Epoxy Co., Ltd.), 40 parts by weight of cresol novolac type epoxy resin (epoxy equivalent 215, Epiklon N-673 manufactured by Dainippon Ink and Chemicals, Inc.), triazine 30 parts by weight of a structure-containing phenol novolac resin (phenolic hydroxyl group equivalent 120, Phenolite KA-7052 manufactured by Dainippon Ink & Chemicals, Inc.) was dissolved in 20 parts by weight of ethyl diglycol acetate and 20 parts by weight of solvent naphtha with stirring. Thereto, terminal epoxidized polybutadiene rubber (Nagase Kasei Kogyo Denarex R-45EPT) 15 parts by weight, 2-phenyl-4,5-bis (hydroxymethyl) imidazole pulverized product 1.5 parts by weight, finely pulverized silica 2 parts by weight , Silicon Added to prepare an epoxy resin composition agent 0.5 parts by weight.
The obtained epoxy resin composition was applied on a PET film having a thickness of 38 μm using a roll coater so that the thickness after drying was 50 μm, and then dried at 80 to 120 ° C. for 10 minutes, whereby an interlayer resin was obtained. A resin film for an insulating layer was produced.
[0113]
(B) Preparation of resin filler
This was carried out in the same manner as the step (a) in the production of the optical element insertion substrate.
[0114]
(C) Production of package substrate
(1) A double-sided copper-clad laminate in which 18 μm copper foil 28 is laminated on both sides of an insulating substrate 21 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.8 mm was used as a starting material ( (See FIG. 2 (a)). First, this copper-clad laminate was drilled, subjected to electroless plating, and etched into a pattern, thereby forming lower conductor circuits 24 and through holes 29 on both sides of the substrate (FIG. 2B). reference).
[0115]
(2) The substrate 21 on which the lower conductor circuit 24 is formed is washed with water and dried, followed by NaOH (10 g / l), NaClO₂(40 g / l), Na₃PO₄Blackening treatment using an aqueous solution containing (6 g / l) as a blackening bath (oxidation bath), and NaOH (10 g / l), NaBH₄A reduction treatment using an aqueous solution containing (6 g / l) as a reduction bath was performed to form a roughened surface (not shown) on the surface of the lower conductor circuit 24.
[0116]
(3) Next, after preparing the resin filler described in (b) above, within 24 hours after preparation by the following method, the conductor circuit non-formed portion and the lower layer conductor in the through hole 29 and on one side of the substrate 21 are prepared. A layer of a resin filler 30 ′ was formed on the outer edge of the circuit 24.
That is, first, a resin filler was pushed into a through hole using a squeegee, and then dried under conditions of 100 ° C. and 20 minutes. Next, a mask having an opening corresponding to the conductor circuit non-formed part is placed on the substrate, and the conductor circuit non-formed part which is a recess is filled with a resin filler using a squeegee, A layer of the resin filler 30 'was formed by drying for 20 minutes (see FIG. 2C).
[0117]
(4) The surface of the conductor circuit 24 or the land surface of the through hole 29 is applied to one surface of the substrate after the processing of (3) by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.). Polishing was performed so that the resin filler 30 'did not remain, and then buffing was performed to remove scratches due to the belt sander polishing. Such a series of processing was similarly performed on the other surface of the substrate.
Subsequently, the heat processing of 100 degreeC for 1 hour, 120 degreeC for 3 hours, 150 degreeC for 1 hour, and 180 degreeC for 7 hours was performed, and the resin filler layer 30 was formed.
[0118]
In this way, the surface layer portion of the resin filler layer 30 and the surface of the conductor circuit 24 formed in the through hole 29 and the conductor circuit non-forming portion are flattened, and the resin filler layer 30 and the side surface of the conductor circuit 24 are roughened. An insulating substrate in which the inner wall surface of the through hole 29 and the resin filler layer 30 are in close contact with each other through a roughened surface (not shown) is firmly attached through a roughened surface (not shown). Obtained (see FIG. 2 (d)). By this step, the surface of the resin filler layer 30 and the surface of the conductor circuit 24 are flush with each other.
[0119]
(5) After washing the substrate with water and acid degreasing, soft etching is performed, and then an etching solution is sprayed on both surfaces of the substrate to spray the surface of the conductor circuit 24 and the land surface of the through hole 29, thereby providing a conductor. A roughened surface (not shown) was formed on the entire surface of the circuit 24. As an etching solution, an etching solution containing 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride (MEC Etch Bond, manufactured by MEC) was used.
[0120]
(6) Next, the resin film for the interlayer resin insulation layer produced in the above (a) is laminated by vacuum compression bonding at 0.5 MPa while raising the temperature to 50 to 150 ° C., and the resin film layer 22α is attached. It formed (refer FIG.2 (e)).
[0121]
(7) Next, CO2 having a wavelength of 10.4 μm is passed through a mask in which a through hole having a thickness of 1.2 mm is formed on the resin film layer 22α.₂With a gas laser, a via hole opening 26 having a diameter of 80 μm is formed in the resin film layer 22α under the conditions of a beam diameter of 4.0 mm, a top hat mode, a pulse width of 8.0 μsec, a mask through-hole diameter of 1.0 mm, and one shot. To form an interlayer resin insulation layer 22 (see FIG. 3A).
[0122]
(8) The substrate on which the via hole opening 26 is formed is immersed in an 80 ° C. solution containing 60 g / l permanganic acid for 10 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulating layer 22. As a result, a roughened surface (not shown) was formed on the surface of the interlayer resin insulating layer 22 including the inner wall surface of the via hole opening 26.
[0123]
(9) Next, the substrate after the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and washed with water.
Further, by applying a palladium catalyst to the surface of the roughened substrate (roughening depth 3 μm), a catalyst nucleus is formed on the surface of the interlayer resin insulation layer 22 (including the inner wall surface of the via hole opening 26). Was attached (not shown). That is, the substrate is made of palladium chloride (PdCl₂) And stannous chloride (SnCl)₂The catalyst was imparted by immersing it in a catalyst solution containing) and depositing palladium metal.
[0124]
(10) Next, the substrate is immersed in an electroless copper plating solution having the following composition, and a thickness of 0.6 to 3 is formed on the surface of the interlayer resin insulating layer 22 (including the inner wall surface of the via hole opening 26). An electroless copper plating film (thin film conductor layer) 32 having a thickness of 0.0 μm was formed (see FIG. 3B).
[Electroless plating solution]
NiSO₄                  0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 100 mg / l
Polyethylene glycol (PEG) 0.10 g / l
[Electroless plating conditions]
40 minutes at a liquid temperature of 34 ° C
[0125]
(11) Next, a commercially available photosensitive dry film is pasted on the substrate on which the electroless copper plating film 32 is formed, and a mask is placed thereon, and 100 mJ / cm.²Then, a plating resist 23 was provided by developing with a 0.8% aqueous sodium carbonate solution (see FIG. 3C).
[0126]
(12) Next, the substrate is washed with 50 ° C. water and degreased, washed with 25 ° C. water and further washed with sulfuric acid, and then subjected to electrolytic plating under the following conditions to form a plating resist 23 non-formed portion. Then, an electrolytic copper plating film 33 was formed (see FIG. 3D).
[Electrolytic plating solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
(Manufactured by Atotech Japan, Kaparaside GL)
[Electrolytic plating conditions]
Current density 1 A / dm²
65 minutes
Temperature 22 ± 2 ° C
[0127]
(13) Further, after removing the plating resist 23 with 5% KOH, the electroless plating film under the plating resist 23 is removed by dissolution treatment by etching with a mixed solution of sulfuric acid and hydrogen peroxide. 25 (including the via hole 27) (see FIG. 4A).
[0128]
(14) Next, the substrate on which the upper layer conductor circuit 25 and the like were formed was immersed in an etching solution to form a roughened surface (not shown) on the surface of the upper layer conductor circuit 25 (including the via hole 27). As an etchant, MEC Etch Bond manufactured by MEC was used.
[0129]
(15) Next, the photosensitizing property obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight: 4000), 80% by weight of bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) dissolved in methyl ethyl ketone, 15.0 parts by weight, imidazole curing agent (Shikoku Kasei Co., Ltd., trade name: 2E4MZ-CN) 1.6 parts by weight, photofunctional monomer bifunctional acrylic monomer (Nippon Kayaku Co., Ltd., trade name: R604) 4.5 parts by weight, also polyvalent acrylic monomer ( Kyoei Chemical Co., Ltd., trade name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (San Nopco, S-65) Take 1 part by weight in a container, stir and mix to prepare a mixed composition. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photopolymerization initiator for this mixed composition, as a photosensitizer By adding 0.2 part by weight of Michler's ketone (manufactured by Kanto Chemical Co., Inc.), a solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C. was obtained.
Moreover, the viscosity measurement was performed at 60 rpm (min^-1), Rotor No. 4, 6 rpm (min^-1), Rotor No. 3 according.
In addition, as a soldering resist composition, a commercially available soldering resist composition can also be used.
[0130]
(16) Next, the above solder resist composition is applied to both surfaces of the substrate on which the upper layer conductor circuit 25 and the like are formed, and dried at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes. An object layer 34α was formed (see FIG. 4B). Next, a photomask having a thickness of 5 mm on which the pattern of the opening was drawn was brought into close contact with the layer 34α of the solder resist composition to be 1000 mJ / cm.²Were exposed to ultraviolet light and developed with DMTG solution to form openings 31.
Further, the solder resist composition layer 34α is cured by heating at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours. A solder resist layer 34 was formed (see FIG. 4C).
[0131]
(17) Next, the substrate on which the solder resist layer 34 is formed is made of nickel chloride (2.3 × 10^-1mol / l), sodium hypophosphite (2.8 × 10^-1mol / l), sodium citrate (1.6 × 10^-1The nickel plating layer having a thickness of 5 μm was formed on a part of the opening 31 by immersing in an electroless nickel plating solution containing 0.5 mol / l) of pH = 4.5. Further, the substrate was made of potassium gold cyanide (7.6 × 10 6^-3mol / l), ammonium chloride (1.9 × 10^-1mol / l), sodium citrate (1.2 × 10^-1mol / l), sodium hypophosphite (1.7 × 10^-1mol / l) is immersed in an electroless gold plating solution at 80 ° C. for 7.5 minutes to form a 0.03 μm-thick gold plating layer on the nickel plating layer to obtain a package substrate (see FIG. 4 (d)). In the figure, the nickel plating layer and the gold plating layer are collectively shown as a plating layer 36.
[0132]
C. Fabrication of IC chip mounting substrate
(1) A lamination press by a mass laminating method is performed, and the optical element insertion substrate produced in A and the package substrate produced in B are bonded together via an adhesive layer formed on the optical element insertion substrate. A substrate was obtained (see FIG. 5A). That is, after aligning both, it heated up to 150 degreeC, and also the board | substrate for optical element insertion and the package board | substrate were bonded together by pressing with the pressure of 5 Mpa.
[0133]
(2) Next, the light receiving element 38 and the light emitting element 39 are exposed on the surface of the package substrate exposed from the through hole 9 formed in the optical element insertion substrate, and the light receiving part 38a and the light emitting part 39a are exposed upward. Attached using silver paste.
The light receiving element 38 was made of InGaAs, and the light emitting element 39 was made of InGaAsP.
[0134]
(3) Next, the electrodes of the light receiving element 38 and the light emitting element 39 were connected to the plating layer 36 on the surface of the package substrate exposed from the through hole 9 by wire bonding (see FIG. 5B). Here, as the wire 40, a wire made of Au was used.
[0135]
(4) Next, a resin composition containing an epoxy resin was filled into the through holes 9 formed in the optical element insertion substrate by printing, and then the resin composition was dried.
Further, the exposed surface of the resin composition was subjected to buffing and mirror polishing. Thereafter, heat treatment was performed to obtain a resin-filled layer 41 (see FIG. 5C).
The resin-filled layer 41 has a transmittance of 93% in the vertical direction for light having a wavelength of 0.85 μm between the upper surface and the lower surface.
[0136]
(5) Next, a resin composition similar to the solder resist composition prepared in the step (15) of manufacturing the package substrate is prepared, and this is applied to the optical element insertion substrate side of the substrate. And 20 minutes at 70 ° C. for 30 minutes to form a solder resist composition layer 54α (see FIG. 6A). Here, the solder resist composition was not applied to the surface of the resin filling layer 41.
Next, a photomask having a thickness of 5 mm on which the pattern of the opening was drawn was brought into close contact with the layer 54α of the solder resist composition and 1000 mJ / cm.²Were exposed to ultraviolet light and developed with DMTG solution to form openings 51.
Further, the solder resist composition layer 54α is cured by heating at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours. A solder resist layer 54 was formed (see FIG. 6B). Therefore, when this step is finished, the solder resist layer 54 is formed on the optical element insertion substrate side, and the solder resist layer 34 is formed on the package substrate side.
[0137]
(6) Next, the substrate on which the solder resist layer 54 is formed is nickel chloride (2.3 × 10^-1mol / l), sodium hypophosphite (2.8 × 10^-1mol / l), sodium citrate (1.6 × 10^-1The nickel plating layer 55 having a thickness of 5 μm was formed in a part of the opening 51 by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6^-3mol / l), ammonium chloride (1.9 × 10^-1mol / l), sodium citrate (1.2 × 10^-1mol / l), sodium hypophosphite (1.7 × 10^-1The gold plating layer 56 having a thickness of 0.03 μm was formed on the nickel plating layer 55 by immersing in an electroless gold plating solution containing 1 mol / l) at 80 ° C. for 7.5 minutes.
[0138]
(7) Next, solder paste (Sn / Ag = 96.5 / 3.5) is printed on the opening 31 formed in the solder resist layer 34 and the opening 51 formed in the solder resist layer 54, and reflowed at 250 ° C. As a result, flip-chip solder bumps 57 and BGA solder bumps 58 were formed, and an IC chip mounting substrate was obtained (see FIG. 6C).
[0139]
For the IC chip mounting substrate thus obtained, an IC chip is mounted by flip chip mounting, and an end face of the optical fiber is disposed at a position facing the light receiving portion of the light receiving element, and the light emitting portion of the light emitting element is disposed. Attach the detector to the opposite position, then send the optical signal through the optical fiber, calculate with the IC chip, then detect the optical signal with the detector, the desired optical signal could be detected .
[0140]
【The invention's effect】
As described above, in the method for manufacturing an IC chip mounting substrate of the present invention, an IC chip mounting substrate that can achieve optical communication excellent in connection reliability and contribute to downsizing of a terminal device is suitably used. Can be manufactured.
[Brief description of the drawings]
FIGS. 1A to 1C are partial cross-sectional views schematically showing a process for producing an optical element insertion substrate in a method for producing an IC chip mounting substrate of the present invention.
FIGS. 2A to 2E are partial cross-sectional views schematically showing a part of a process for producing a package substrate in the method for producing an IC chip mounting substrate of the present invention. FIGS.
FIGS. 3A to 3D are partial cross-sectional views schematically showing a part of a process of manufacturing a package substrate in the method for manufacturing an IC chip mounting substrate according to the present invention. FIGS.
FIGS. 4A to 4D are partial cross-sectional views schematically showing a part of a process for producing a package substrate in the method for producing an IC chip mounting substrate of the present invention. FIGS.
FIGS. 5A to 5C are partial cross-sectional views schematically showing a part of the method for manufacturing an IC chip mounting substrate according to the present invention. FIGS.
FIGS. 6A to 6C are partial cross-sectional views schematically showing a part of the method for manufacturing an IC chip mounting substrate according to the present invention. FIGS.
[Explanation of symbols]
1,21 Insulating substrate
8, 28 Copper foil
4, 24 Lower layer conductor circuit
6, 29 Through hole
9 Through hole
10, 30 Resin filler layer
12 Conductor layer
14 Conductor layer
16 Lid plating layer
22 Interlayer resin insulation layer
23 Plating resist
25 Conductor circuit
27 Bahia Hall
32 Thin film conductor layer
33 Electrolytic plating film
34, 54 Solder resist layer
36 Plating layer
38 Light receiving element
39 Light Emitting Element
40 wires
41 Resin filled layer
57 Solder bump for flip chip
58 BGA solder bumps

Claims (4)

(A) a conductor circuit forming step for forming a conductor circuit on both surfaces of the substrate a and forming a through hole for connecting between the conductor circuits sandwiching the substrate a; (b) one side of the substrate a on which the conductor circuit is formed; An adhesive layer forming step of forming an adhesive layer on at least a part of the conductor circuit non-forming portion; and (c) a through hole forming step of forming a through hole in a part of the substrate a on which the adhesive layer is formed. An optical element insertion substrate fabricated through
(A) a first conductor circuit forming step for forming a conductor circuit on both surfaces of the substrate A; (B) an interlayer resin insulation layer having a via hole is formed on the substrate A on which the conductor circuit is formed; A package substrate produced through an interlayer resin insulation layer lamination step for forming a conductor circuit on the resin insulation layer, and a solder resist layer formation step for forming a solder resist layer on the outermost layer (C);
After bonding together, at least the following steps (1) to (3) are performed.
(1) An optical element mounting step of electrically connecting the optical element and a conductor circuit of the package substrate after attaching the optical element to the surface of the package substrate exposed from the through hole formed in the optical element insertion substrate. ,
(2) a resin-filled layer forming step of filling a resin composition into a through-hole formed in the optical element insertion substrate and forming a resin-filled layer; and
(3) A solder resist layer forming step of forming a solder resist layer on the exposed surface of the optical element insertion substrate. 2. The method for manufacturing an IC chip mounting substrate according to claim 1, wherein in the step (1), the optical element and the package substrate are electrically connected by wire bonding. 3. The IC chip mounting substrate according to claim 1, wherein the resin-filled layer formed in the step (2) has a transmittance of 90% or more of light in the vertical direction between the upper surface and the lower surface. Manufacturing method. The method for producing an IC chip mounting substrate according to claim 1 or 2, wherein the resin-filled layer formed in the step (2) has a transmittance of light having a communication wavelength per 1 mm length of 90% or more.

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