JP4827809B2 - IC chip mounting board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for mounting IC chips with excellent electric signal transmission reliability, the substrate being a component for optical communication in which an IC chip and an optical component are integrated and the distance between the IC chip and an optical component is short. <P>SOLUTION: In the substrate for mounting IC chips, in which a conductive circuit and an interlayer resin insulating layer are laminated and formed on both surfaces of the substrate, the substrate for mounting IC chips has: one surface thereof where a light receiving element and a light emitting element are built-in or incorporated so that a light receiving portion and a light emitting portion are exposed; and the other surface thereof where a portion is provided for mounting the IC chips. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

The present invention relates to an IC chip mounting substrate.

In recent years, attention has been focused on optical fibers mainly in the communication field. In particular, in the IT (information technology) field, communication technology using optical fibers is required to develop a high-speed Internet network.
The optical fiber has features such as (1) low loss, (2) high bandwidth, (3) small diameter and light weight, (4) non-induction, and (5) resource saving. Compared with communication systems using conventional metallic cables, the number of repeaters can be greatly reduced, making construction and maintenance easier, and making communication systems more economical and more reliable. Can be planned.

In addition, since optical fibers can simultaneously multiplex and transmit not only light of one wavelength but also light of many different wavelengths using a single optical fiber, a large-capacity transmission line that can be used for a variety of applications. It can be realized and can also support video services and the like.

Therefore, in such network communication such as the Internet, optical communication using an optical fiber is not only performed for communication of the backbone network, but also for communication between the backbone network and terminal devices (PC, mobile, game, etc.) It has also been proposed to be used for communication between each other.

As described above, when optical communication is used for communication between the backbone network and the terminal device, an IC that performs information (signal) processing in the terminal device operates with an electrical signal. Therefore, the terminal device includes an optical-to-electric converter, It is necessary to attach a device (hereinafter also referred to as an optical / electrical converter) that converts an optical signal and an electrical signal, such as an electrical-to-optical converter. Therefore, in a conventional terminal device, for example, a package substrate on which an IC chip is mounted, an optical component such as a light receiving element or a light emitting element that processes an optical signal, and the like are separately mounted, and an electrical wiring or an optical waveguide is connected to them, Signal transmission and signal processing were performed.

In such a conventional terminal device, since the IC mounting package substrate and the optical component are separately mounted, the entire apparatus becomes large, which is a factor that hinders the miniaturization of the terminal device.
Further, in the conventional terminal device, since the distance between the IC mounting package substrate and the optical component is large, the electric wiring distance is long, and a signal error due to crosstalk noise or the like is likely to occur during signal transmission.

Accordingly, the present inventors have intensively studied an IC chip mounting substrate that can achieve optical communication with excellent connection reliability and contribute to miniaturization of terminal equipment. It was conceived that the above-mentioned problems can be solved by mounting components, and the IC chip mounting substrate of the present invention having the following configuration was completed.
In the present specification, the first invention, the second invention, and the third invention will be described. The present invention is the second and third inventions among these first to third inventions. It is this invention.

That is, the IC chip mounting substrate according to the first aspect of the present invention is an IC chip mounting substrate in which a conductor circuit and an interlayer resin insulating layer are laminated on both sides of the substrate,
A light receiving element and a light emitting element are mounted on one surface of the IC chip mounting substrate so that the light receiving part and the light emitting part are exposed, respectively.

The IC chip mounting substrate of the second aspect of the present invention is an IC chip mounting substrate in which a conductor circuit and an interlayer resin insulating layer are laminated on both surfaces of the substrate,
On one surface side of the IC chip mounting substrate, a light receiving element and a light emitting element are incorporated or housed so that the light receiving part and the light emitting part are exposed, respectively.
The other surface side of the IC chip mounting substrate is provided with a portion to which an IC chip is attached.

The IC chip mounting substrate of the third aspect of the present invention is an IC chip mounting substrate in which a conductor circuit and an interlayer resin insulating layer are laminated on both sides of the substrate,
A light receiving element and a light emitting element are embedded on one surface side of the IC chip mounting substrate, an optical path connecting the light receiving part of the light receiving element and an optical signal, and the light emitting part of the light emitting element and the optical signal An optical path to connect the
The other surface side of the IC chip mounting substrate is provided with a portion to which an IC chip is attached.
The optical path in the IC chip mounting substrate of the third aspect of the present invention is preferably an optical path opening.

In the IC chip mounting substrates of the first to third inventions, a solder resist layer is formed on the outermost layer on at least one surface side of the IC chip mounting substrate, and solder bumps are formed on the solder resist layer. Is preferably formed.
In the IC chip mounting substrates of the first to third aspects of the present invention, the solder resist layer may be formed or may not be formed.

In the IC chip mounting substrates of the first to third inventions, the conductor circuits sandwiching the substrate are connected via through holes, and the conductor circuits sandwiching the interlayer resin insulation layer are via holes. It is desirable to be connected via

In the IC chip mounting substrates of the first to third aspects of the present invention, it is desirable that the light receiving element and the light emitting element can be solder-connected.
Examples of the light-receiving element and the light-emitting element that can be solder-connected include (1) flip chip type components, which are mounted on the IC chip mounting substrate by solder pads provided on the same side as the light-receiving surface and the light-emitting surface. It is mounted and electrically connected. (2) A flip chip type component which is mounted on the IC chip mounting substrate and electrically connected by a solder pad provided on the opposite side of the light receiving surface and the light emitting surface. (3) Wire-bonding-type components, which are mounted on the IC chip mounting substrate by solder pads provided on the same side as the light receiving surface and the light emitting surface, and wire bonding provided on the opposite side of the light receiving surface and the light emitting surface. Electrically connected by wire bonding to a pad for use. (4) Wire-bonding-type components, which are mounted on the IC chip mounting substrate by solder pads provided on the opposite side of the light receiving surface and the light emitting surface, and wire bonding provided on the same side as the light receiving surface and the light emitting surface. Examples thereof include those that are electrically connected by wire bonding to a pad for use.
Among these, the above (1) or (2) is desirable. Using the self-alignment effect of the solder, the position of the light receiving element and the light emitting element (light receiving part and light emitting part) can be accurately aligned with the light guide path (optical waveguide etc.) of an external substrate such as a motherboard. In addition, since the positioning accuracy of the light emitting element is excellent and wire bonding is unnecessary, it can be easily mounted on the IC chip mounting substrate. The light receiving element and the light emitting element mounted on the IC chip mounting substrate of the present invention do not need to be any one of those listed in the above (1) to (4), and the above (1) to (4 Two or more of those listed above may be present.

Since the substrate for mounting an IC chip according to the first to third aspects of the present invention has the above-described configuration, since the light receiving element and the light emitting element are mounted on the surface of the substrate, the IC chip is mounted on the substrate. The distance between the chip and the optical component is short, and the electrical signal transmission reliability is excellent.
In the IC chip mounting substrates of the first to third aspects of the present invention, electronic components and optical components necessary for optical communication can be integrated by mounting the IC chip. This can contribute to downsizing.

In the IC chip mounting substrates of the first to third aspects of the invention, a solder resist layer is formed on the outermost layer on the side where the light receiving element and the light emitting element are mounted, and solder bumps are formed on the solder resist layer. In this case, since the IC chip mounting substrate can be connected to the external substrate through the solder bumps, the IC chip mounting substrate can be disposed at a predetermined position by the self-alignment effect possessed by the solder. In addition, an accurate optical signal can be transmitted between the IC chip mounting substrate of the first to third aspects of the invention and the external substrate.

First, the IC chip mounting substrate according to the first aspect of the present invention will be described.
The IC chip mounting substrate of the first aspect of the present invention is an IC chip mounting substrate in which a conductor circuit and an interlayer resin insulating layer are laminated on both sides of the substrate,
A light receiving element and a light emitting element are mounted on one surface of the IC chip mounting substrate so that the light receiving part and the light emitting part are exposed, respectively.

In the IC chip mounting substrate of the first invention, since the light receiving element and the light emitting element are mounted on the surface of the substrate, when the IC chip is mounted on the substrate, the distance between the IC chip and the optical component is short, Excellent electrical signal transmission reliability.
Further, the IC chip mounting substrate of the present invention on which the IC chip is mounted can contribute to the miniaturization of the optical communication terminal device because the electronic component and the optical component necessary for optical communication can be integrated. .

In the IC chip mounting substrate according to the first aspect of the present invention, a solder resist layer is formed on the outermost layer on the side where the light receiving element or the like is mounted, and solder bumps are formed on the solder resist layer. In this case, the IC chip mounting substrate can be connected to an external substrate through solder bumps. In this case, the IC chip mounting substrate is disposed at a predetermined position by the self-alignment action of the solder. be able to.

The self-alignment action refers to an action in which the solder resist layer repels solder, so that the solder tends to exist in a more stable shape near the center of the solder bump forming opening due to its own fluidity during reflow processing. When this self-alignment action is used, when the IC chip mounting substrate is connected to the external substrate via the solder bumps, even if a positional deviation occurs between both before reflow, The IC chip mounting substrate moves, and the IC chip mounting substrate can be attached to an accurate position on the external substrate.
Therefore, when transmitting an optical signal via a light receiving element or light emitting element mounted on the IC chip mounting substrate and an optical component (such as an optical waveguide) mounted on the external substrate, the IC chip is used. If the mounting position of the light receiving element and the light emitting element mounted on the mounting substrate is accurate, it is possible to accurately transmit an optical signal between the IC chip mounting substrate and the external substrate.

In the IC chip mounting substrate of the first aspect of the present invention, the light receiving element and the light emitting element are mounted on one surface thereof so that the light receiving part and the light emitting part are exposed.
Examples of the light receiving element include PD (photodiode), APD (avalanche photodiode), and the like.
These may be properly used in consideration of the configuration of the IC chip mounting substrate, required characteristics, and the like.
Examples of the material for the light receiving element include Si, Ge, and InGaAs.
Of these, InGaAs is desirable because of its excellent light receiving sensitivity.

Examples of the light emitting element include LD (semiconductor laser), DFB-LD (distributed feedback type-semiconductor laser), LED (light emitting diode), and the like.
These may be properly used in consideration of the configuration and required characteristics of the IC chip mounting substrate.

Examples of the material of the light emitting element include a compound of gallium, arsenic and phosphorus (GaAsP), a compound of gallium, aluminum and arsenic (GaAlAs), a compound of gallium and arsenic (GaAs), a compound of indium, gallium and arsenic (InGaAs), Indium, gallium, arsenic and phosphorus compounds (InGaAsP) can be used.
These may be properly used in consideration of the communication wavelength (in the range of 0.6 to 1.6 μm). For example, when the communication wavelength is in the 0.85 μm band, GaAlAs can be used, and the communication wavelength is 1 In the case of the .3 μm band or the 1.55 μm band, InGaAs or InGaAsP can be used.
In addition, as said light receiving element and said light emitting element, what is marketed as an optical element can also be used, As the magnitude | size, the length of the one side which has a light-receiving part and a light-emitting part is 2-15 mm. A degree is desirable.

Hereinafter, an embodiment of an IC chip mounting substrate according to the first aspect of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view schematically showing an embodiment of an IC chip mounting substrate according to the first aspect of the present invention. FIG. 1 shows an IC chip mounting substrate on which an IC chip is mounted.

As shown in FIG. 1, the IC chip mounting substrate 120 includes a conductive circuit 124 (124a to 124d) and an interlayer resin insulating layer 122 laminated on both surfaces of the substrate 121, and between the conductive circuits sandwiching the substrate 121, and The conductor circuits sandwiching the interlayer resin insulation layer 122 are electrically connected by through holes 129 (129a, 129b) and via holes 127 (127a to 127h), respectively. A solder resist layer 134 is formed on the outermost layer.
Further, the light receiving element 138 and the light emitting element 139 are mounted on one surface of the IC chip mounting substrate 120 so that the light receiving section 138a and the light emitting section 139a are exposed, respectively, and in addition, the light receiving element 138 and the like are mounted. Solder bumps 137 are formed on the solder resist layer on the other side, and the IC chip 140 is mounted on the other surface of the IC chip mounting substrate 120 via the solder connection portions 143 (143a, 143b). ing.

In the IC chip mounting substrate 120 having such a configuration, an optical signal transmitted from the outside via an optical fiber, an optical waveguide, or the like (not shown) is received by the light receiving element 138 (light receiving unit 138a). The light receiving element 138 converts the electric signal into an electric signal, and further passes through the conductive layer 142a-conductor circuit 124a-via hole 127a, 127b-through hole 129a-via hole 127c, 127d-conductor circuit 124b-solder connection part 143a via the IC chip. 140.

Also, the electrical signal sent from the IC chip 140 is transmitted through the solder connection portion 143b-conductor circuit 124c-via hole 127e, 127f-through hole 129b-via hole 127g, 127h-conductor circuit 124d-conductive layer 142b. After being sent to 139, it is converted into an optical signal by the light emitting element 139, and this optical signal is transmitted from the light emitting element 139 (light emitting portion 139a) to an optical fiber or an optical waveguide.

In the IC chip mounting substrate according to the first aspect of the present invention, since the light / electric element conversion is performed in the light receiving element and the light emitting element mounted at positions close to the IC chip, the transmission distance of the electric signal is short, and the signal transmission reliability is reduced. It can be used for higher speed communication.

Further, since the solder bump 137 is formed on the solder resist layer on one surface side in the IC chip mounting substrate 120, the electrical signal sent from the IC chip 140 is converted into an optical signal as described above. Thereafter, it is not only sent to the outside via an optical waveguide or the like, but also sent to an external substrate via a solder bump.
In addition, it is possible to supply power necessary for driving the IC chip from the outside of the IC chip mounting substrate 120 via the solder bump 137.

Next, a method for manufacturing the IC chip mounting substrate of the first invention will be described.
(1) Using an insulating substrate as a starting material, first, a conductor circuit is formed on the insulating substrate.
Examples of the insulating substrate include a glass epoxy substrate, a polyester substrate, a polyimide substrate, a bismaleimide-triazine (BT) resin substrate, a thermosetting polyphenylene ether substrate, a copper clad laminate, and an RCC substrate.
Further, a ceramic substrate such as an aluminum nitride substrate or a silicon substrate may be used.
The conductor circuit can be formed, for example, by forming a solid conductor layer on the surface of the insulating substrate by electroless plating or the like and then performing an etching process. Moreover, you may form by performing an etching process to a copper clad laminated board or a RCC board | substrate.

In addition, in the case where connection between conductor circuits sandwiching the insulating substrate is performed through holes, for example, after forming a through hole in the insulating substrate using a drill or a laser, an electroless plating process or the like is performed. Through holes are formed by applying. In addition, the diameter of the said through-hole is 100-300 micrometers normally.
Further, when a through hole is formed, it is desirable to fill the through hole with a resin filler.

(2) Next, the surface of the conductor circuit is roughened as necessary.
Examples of the roughening treatment include blackening (oxidation) -reduction treatment, etching treatment using an etchant containing a cupric complex and an organic acid salt, and treatment by Cu—Ni—P needle-like alloy plating. Etc.
Here, when a roughened surface is formed, normally, the lower limit of the average roughness of the roughened surface is preferably 0.1 μm, and the upper limit is preferably 5 μm. Considering the adhesion between the conductor circuit and the interlayer resin insulation layer, the influence on the electric signal transmission ability of the conductor circuit, etc., the lower limit of the roughened surface is more preferably 2 μm, and the upper limit is more preferably 4 μm.
The roughening process may be performed before the resin filler is filled in the through hole, and a roughened surface may be formed on the wall surface of the through hole. This is because the adhesion between the through hole and the resin filler is improved.

(3) Next, from a substrate on which a conductor circuit is formed, a thermosetting resin, a photosensitive resin, a resin in which a part of the thermosetting resin is acrylated, or a resin composite including these and a thermoplastic resin. An uncured resin layer is formed, or a resin layer made of a thermoplastic resin is formed.
The uncured resin layer can be formed by applying uncured resin with a roll coater, curtain coater, or the like, or thermocompression bonding an uncured (semi-cured) resin film.
Moreover, the resin layer which consists of the said thermoplastic resin can be formed by thermocompression-bonding the resin molded object shape | molded on the film.

Among these, a method of thermocompression bonding an uncured (semi-cured) resin film is desirable, and the resin film can be crimped using, for example, a vacuum laminator or the like.
In addition, the pressure bonding conditions are not particularly limited, and may be appropriately selected in consideration of the composition of the resin film. Usually, the pressure is 0.25 to 1.0 MPa, the temperature is 40 to 70 ° C., the degree of vacuum is 13 to 1300 Pa, It is desirable to carry out under conditions of a time of about 10 to 120 seconds.

Examples of the thermosetting resin include epoxy resins, phenol resins, polyimide resins, polyester resins, bismaleimide resins, polyolefin resins, polyphenylene ether resins, polyphenylene resins, and fluorine resins.
Specific examples of the epoxy resin include, for example, novolak type epoxy resins such as phenol novolak type and cresol novolak type, dicyclopentadiene-modified alicyclic epoxy resins, and the like.

As said photosensitive resin, an acrylic resin etc. are mentioned, for example.
Moreover, as resin which acrylated a part of said thermosetting resin, what made the acrylate reaction of the thermosetting group of the above-mentioned thermosetting resin, methacrylic acid, and acrylic acid etc. are mentioned, for example.

Examples of the thermoplastic resin include phenoxy resin, polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS) polyphenylene sulfide (PPES), polyphenylene ether (PPE) polyetherimide (PI), and the like. It is done.

The resin composite is not particularly limited as long as it includes a thermosetting resin or a photosensitive resin (including a resin obtained by acrylating a part of the thermosetting resin) and a thermoplastic resin. Specific examples of the combination of the curable resin and the thermoplastic resin include phenol resin / polyether sulfone, polyimide resin / polysulfone, epoxy resin / polyether sulfone, and epoxy resin / phenoxy resin. Specific examples of the combination of the photosensitive resin and the thermoplastic resin include an acrylic resin / phenoxy resin, an epoxy resin in which a part of the epoxy group is acrylated, and polyether sulfone.

In addition, the blending ratio of the thermosetting resin or the photosensitive resin and the thermoplastic resin in the resin composite is preferably thermosetting resin or photosensitive resin / thermoplastic resin = 95/5 to 50/50. This is because a high toughness value can be ensured without impairing heat resistance.

The resin layer may be composed of two or more different resin layers.
Specifically, for example, the lower layer is formed from a thermosetting resin or a resin composite of photosensitive resin / thermoplastic resin = 50/50, and the upper layer is a thermosetting resin or photosensitive resin / thermoplastic resin = 90/50. It is formed from 10 resin composites.
With such a configuration, it is possible to ensure excellent adhesion with the substrate and ease of formation when forming a via hole opening or the like in a later step.

Moreover, you may form the said resin layer using the resin composition for roughening surface formation.
The roughened surface-forming resin composition is, for example, an acid, an alkali, in an uncured heat-resistant resin matrix that is hardly soluble in a roughened liquid consisting of at least one selected from acids, alkalis and oxidizing agents. And a substance soluble in a roughening liquid comprising at least one selected from oxidizing agents.
As used herein, the terms “slightly soluble” and “soluble” refer to those having a relatively high dissolution rate as “soluble” for convenience when immersed in the same roughening solution for the same time. The slow one is called “slightly soluble” for convenience.

The heat-resistant resin matrix is preferably one that can maintain the shape of the roughened surface when the roughened surface is formed on the interlayer resin insulation layer using the roughening liquid, for example, a thermosetting resin. , Thermoplastic resins, and composites thereof. Further, by using a photosensitive resin, the via hole opening may be formed in the interlayer resin insulating layer by exposure and development processing.

Examples of the thermosetting resin include an epoxy resin, a phenol resin, a polyimide resin, a polyolefin resin, and a fluororesin. Moreover, when sensitizing the said thermosetting resin, methacrylic acid, acrylic acid, etc. are used, and a thermosetting group is (meth) acrylated.

Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.

Examples of the thermoplastic resin include phenoxy resin, polyether sulfone, polysulfone, polyphenylene sulfone, polyphenylene sulfide, polyphenyl ether, polyether imide, and the like. These may be used alone or in combination of two or more.

The substance soluble in the roughening liquid comprising at least one selected from the acid, alkali and oxidizing agent is preferably at least one selected from inorganic particles, resin particles and metal particles.

Examples of the inorganic particles include aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds. These may be used alone or in combination of two or more.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate, and talc. Examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.

The alumina particles can be dissolved and removed with hydrofluoric acid, and calcium carbonate can be dissolved and removed with hydrochloric acid. Sodium-containing silica and dolomite can be dissolved and removed with an alkaline aqueous solution.

Examples of the resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When the resin particles are immersed in a roughening solution made of at least one selected from an acid, an alkali, and an oxidizing agent, the heat resistance It is not particularly limited as long as it has a faster dissolution rate than the resin matrix. Specifically, for example, amino resins (melamine resins, urea resins, guanamine resins, etc.), epoxy resins, phenol resins, phenoxy resins, polyimide resins, Examples include polyphenylene resin, polyolefin resin, fluororesin, and bismaleimide-triazine resin. These may be used alone or in combination of two or more.
The resin particles must be previously cured. This is because if the resin is not cured, the resin particles will be dissolved in a solvent for dissolving the resin matrix.

Further, as the resin particles, rubber particles, liquid phase resin, liquid phase rubber, or the like may be used.
Examples of the rubber particles include acrylonitrile-butadiene rubber, polychloroprene rubber, polyisoprene rubber, acrylic rubber, polysulfuric rigid rubber, fluorine rubber, urethane rubber, silicone rubber, and ABS resin.
Further, for example, various modified polybutadiene rubbers such as polybutadiene rubber, epoxy modification, urethane modification, (meth) acrylonitrile modification, (meth) acrylonitrile / butadiene rubber containing a carboxyl group, and the like may be used.

As the liquid phase resin, an uncured solution of the thermosetting resin can be used. As a specific example of such a liquid phase resin, for example, a mixed liquid of an uncured epoxy oligomer and an amine curing agent. Etc.
Examples of the liquid phase rubber include, but are not limited to, polybutadiene rubber, epoxy-modified, urethane-modified, various modified polybutadiene rubbers such as (meth) acrylonitrile modification, uncured solutions such as (meth) acrylonitrile / butadiene rubbers containing carboxyl groups, etc. Can be used.

When preparing the photosensitive resin composition using the liquid phase resin or liquid phase rubber, so that the heat resistant resin matrix and the soluble substance are not compatible with each other uniformly (that is, so as to phase-separate), It is necessary to select these substances.
By mixing the heat-resistant resin matrix selected according to the above criteria and a soluble substance, the liquid-phase resin or liquid-phase rubber “islands” are dispersed in the “sea” of the heat-resistant resin matrix. Alternatively, it is possible to prepare a photosensitive resin composition in which “islands” of a heat-resistant resin matrix are dispersed in a “sea” of a liquid phase resin or a liquid phase rubber.
And after hardening the photosensitive resin composition of such a state, a roughened surface can be formed by removing the liquid phase resin or liquid phase rubber of "the sea" or "the island".

Examples of the metal particles include gold, silver, copper, tin, zinc, stainless steel, aluminum, nickel, iron, lead, and the like. These may be used alone or in combination of two or more.
In addition, the metal particles may be coated with a resin or the like in order to ensure insulation.

When two or more kinds of the above-mentioned soluble substances are used in combination, the combination of the two kinds of soluble substances to be mixed is preferably a combination of resin particles and inorganic particles. Since both have low electrical conductivity, the insulation of the interlayer resin insulation layer can be ensured, and the thermal expansion can be easily adjusted with the poorly soluble resin, and the interlayer resin is made of a roughened surface-forming resin composition. This is because no crack occurs in the insulating layer, and no peeling occurs between the interlayer resin insulating layer and the conductor circuit.

Examples of the acid used as the roughening solution include phosphoric acid, hydrochloric acid, sulfuric acid, nitric acid, and organic acids such as formic acid and acetic acid. Among these, it is desirable to use an organic acid. This is because when the roughening treatment is performed, the metal conductor layer exposed from the via hole is hardly corroded.
As the oxidizing agent, for example, an aqueous solution of chromic acid, chromium sulfuric acid, alkaline permanganate (such as potassium permanganate), or the like is preferably used.
Moreover, as said alkali, aqueous solution, such as sodium hydroxide and potassium hydroxide, is desirable.

The average particle size of the soluble substance is desirably 10 μm or less.
Further, a relatively large coarse particle having an average particle diameter of 2 μm or less and a fine particle having a relatively small average particle diameter may be used in combination. That is, a soluble substance having an average particle diameter of 0.1 to 0.5 μm and a soluble substance having an average particle diameter of 1 to 2 μm are combined.

Thus, by combining the average particles, relatively large coarse particles, and fine particles having a relatively small average particle diameter, the dissolution residue of the thin film conductor layer is eliminated, and the amount of palladium catalyst under the plating resist is reduced. A shallow and complicated roughened surface can be formed.
Furthermore, by forming a complicated roughened surface, a practical peel strength can be maintained even if the roughened surface has small irregularities.
The coarse particles preferably have an average particle size of more than 0.8 μm and less than 2.0 μm, and the fine particles preferably have an average particle size of 0.1 to 0.8 μm.

(4) Next, when forming an interlayer resin insulation layer using a thermosetting resin or a resin composite as the material, the uncured resin insulation layer is cured and a via hole opening is formed. And an interlayer resin insulation layer. In this step, a through hole may be formed as necessary.
The via hole opening is preferably formed by laser processing. Further, when a photosensitive resin is used as the material for the interlayer resin insulation layer, it may be formed by exposure and development processing.

When an interlayer resin insulating layer using a thermoplastic resin as the material is formed, a via hole opening is formed in the resin layer made of the thermoplastic resin to form an interlayer resin insulating layer. In this case, the via hole opening can be formed by performing laser treatment.
Further, when forming a through hole in this step, the through hole may be formed by drilling or laser processing.

Examples of the laser used for the laser treatment include a carbon dioxide laser, an ultraviolet laser, and an excimer laser. Among these, an excimer laser and a short pulse carbon dioxide laser are desirable.

Among excimer lasers, it is desirable to use a hologram type excimer laser. The hologram method is a method of irradiating a target object with laser light through a hologram, a condensing lens, a laser mask, a transfer lens, and the like. Can be formed efficiently.

When using a carbon dioxide laser, the pulse interval is preferably 10 ⁻⁴ to 10 ⁻⁸ seconds. Moreover, it is desirable that the time for irradiating the laser for forming the opening is 10 to 500 μsec.
In addition, by irradiating laser light through an optical system lens and a mask, a large number of openings for via holes can be formed at one time. This is because laser light having the same intensity and the same irradiation intensity can be irradiated to a plurality of portions through the optical system lens and the mask.
After forming the via hole opening in this manner, desmear treatment may be performed as necessary.

(5) Next, a conductor circuit is formed on the surface of the interlayer resin insulation layer including the inner wall of the via hole opening.
In forming the conductor circuit, first, a thin film conductor layer is formed on the surface of the interlayer resin insulation layer.
The thin film conductor layer can be formed by a method such as electroless plating or sputtering.

Examples of the material for the thin film conductor layer include copper, nickel, tin, zinc, cobalt, thallium, lead, and the like.
Among these, those made of copper, copper and nickel are desirable from the viewpoint of excellent electrical characteristics, economical efficiency, and the like.
Moreover, as for the thickness of the thin film conductor layer, when the thin film conductor layer is formed by electroless plating, the lower limit thereof is desirably 0.3 μm, and more desirably 0.6 μm. The upper limit is desirably 2.0 μm, and more desirably 1.2 μm. Moreover, when forming by sputtering, 0.1-1.0 micrometer is desirable.

In addition, a roughened surface may be formed on the surface of the interlayer resin insulation layer before forming the thin film conductor layer. By forming the roughened surface, the adhesion between the interlayer resin insulation layer and the thin film conductor layer can be improved. In particular, when an interlayer resin insulation layer is formed using a roughened surface forming resin composition, it is desirable to form a roughened surface using an acid, an oxidizing agent, or the like.

Further, when the through hole is formed in the step (4), when the thin film conductor layer is formed on the interlayer resin insulation layer, the through hole is formed by forming the thin film conductor layer on the wall surface of the through hole. Also good.

(6) Next, a plating resist is formed on the substrate on which the thin film conductor layer is formed.
The plating resist can be formed, for example, by sticking a photosensitive dry film, placing a photomask made of a glass substrate or the like on which a plating resist pattern is drawn, and performing exposure and development processing.

(7) Thereafter, electroplating is performed using the thin film conductor layer as a plating lead, and an electroplating layer is formed in the plating resist non-forming portion. As the electroplating, copper plating is desirable.
The thickness of the electroplating layer is preferably 5 to 20 μm.

Then, a conductor circuit (including a via hole) can be formed by removing the plating resist and the thin film conductor layer under the plating resist.
The plating resist may be removed using, for example, an alkaline aqueous solution, and the thin film conductor layer may be removed using a mixed solution of sulfuric acid and hydrogen peroxide, sodium persulfate, ammonium persulfate, ferric chloride, chloride. What is necessary is just to perform using etching liquid, such as cupric.
Moreover, after forming the said conductor circuit, you may remove the catalyst on an interlayer resin insulation layer using an acid or an oxidizing agent as needed. This is because deterioration of electrical characteristics can be prevented.
Moreover, after forming this plating resist, it replaces with the method (process (6) and (7)) which forms an electroplating layer, forms an electroplating layer on the whole surface on a thin film conductor layer, and performs an etching process. A conductor circuit may be formed using a method.

Further, when a through hole is formed in the steps (4) and (5), a resin filler may be filled in the through hole.
Moreover, when the resin filler is filled in the through hole, a lid plating layer that covers the surface portion of the resin filler layer may be formed by performing electroless plating, if necessary.

(8) Next, when a lid plating layer is formed, if necessary, the surface of the lid plating layer is subjected to a roughening treatment, and further, if necessary, steps (3) to (7) Is repeated to form an interlayer resin insulation layer and a conductor circuit on both surfaces. In this step, a through hole may be formed or may not be formed.

(9) Next, if necessary, a solder resist layer is formed on the outermost layer of the substrate on which the conductor circuit and the interlayer resin insulating layer are formed.
The solder resist layer can be formed using, for example, a solder resist composition made of polyphenylene ether resin, polyolefin resin, fluororesin, thermoplastic elastomer, epoxy resin, polyimide resin, or the like.

Examples of solder resist compositions other than those described above include, for example, (meth) acrylates of novolak epoxy resins, imidazole curing agents, bifunctional (meth) acrylic acid ester monomers, and (meth) acrylic acid having a molecular weight of about 500 to 5,000. Examples include paste polymers containing ester polymers, thermosetting resins composed of bisphenol-type epoxy resins, photosensitive monomers such as polyvalent acrylic monomers, glycol ether solvents, and the viscosity at 25 ° C. It is desirable that the pressure is adjusted to 1 to 10 Pa · s.
The lower limit of the thickness of the solder resist layer is preferably 10 μm, more preferably 15 μm, and the upper limit is preferably 30 μm, more preferably 25 μm. The thickness of the solder resist layer is most preferably 20 μm.

(10) Next, a solder bump forming opening and an optical element mounting opening are formed in the solder resist layer.
The solder bump forming opening and the optical element mounting opening can be formed by a method similar to the method of forming the via hole opening, that is, exposure development processing or laser processing.
Moreover, when forming a solder resist layer, a solder film having openings for forming solder bumps and openings for mounting optical elements is prepared by preparing a resin film having openings at desired positions in advance and pasting the resin film. A resist layer may be formed. The opening diameter of the optical element mounting opening includes a pitch between solder pads (connection terminals) of the light receiving element and the light emitting element (for example, 100 to 250 μm), and a diameter of the solder pad (for example, 50 to 200 μm). For example, the diameter may be substantially the same as the diameter of the solder pad, or may be approximately 10 to 30 μm larger than the diameter of the solder pad. When the diameter is larger than the diameter of the solder pad, the bonding strength of the solder can be improved.

(11) Next, the conductor circuit portion exposed by forming the solder bump forming openings is covered with a corrosion-resistant metal such as nickel, palladium, gold, silver, platinum, or the like as necessary to form a solder pad. . In these, it is desirable to form a coating layer with metals, such as nickel-gold, nickel-silver, nickel-palladium, nickel-palladium-gold.
The coating layer can be formed by, for example, plating, vapor deposition, electrodeposition, or the like. Among these, it is desirable to form by plating from the viewpoint that the uniformity of the coating layer is excellent.
In this step, it is desirable to form a coating layer also on the conductor circuit portion exposed by forming the optical element mounting opening.

(12) Next, a solder bump is formed by reflowing after filling the solder pad with a solder paste through a mask in which an opening is formed in a portion corresponding to the solder pad.
Examples of the composition of the solder paste include Sn: Ag (weight ratio) = 96.5: 3.5 (melting point 221 ° C., eutectic).
The other composition of the solder paste is, for example, SnAgCu series such as Sn: Ag: Cu (weight ratio) = 96.5: 3.0: 0.5, Sn: Cu (weight ratio) = 99. Examples include SnCu series such as 3: 0.7, SnSb series such as Sn: Sb (weight ratio) = 95.0: 5.0, and the like.

(13) Further, an optical element (light receiving element and light emitting element) is mounted on the solder resist layer. The optical element is mounted by, for example, filling the optical element mounting opening with solder paste in the step (12), and aligning and attaching the optical element when performing reflow. Mounting may be performed via solder (conductive layer).
Further, the optical element may be mounted using a conductive adhesive or the like instead of the solder.
When these methods are used, the light receiving element and the light emitting element are mounted on the surface of the solder resist layer.
Through such steps, the IC chip mounting substrate of the first aspect of the present invention can be manufactured.

Next, an IC chip mounting substrate according to the second aspect of the present invention will be described.
The IC chip mounting substrate of the second aspect of the present invention is an IC chip mounting substrate in which a conductor circuit and an interlayer resin insulating layer are laminated on both surfaces of the substrate,
On one surface side of the IC chip mounting substrate, a light receiving element and a light emitting element are incorporated or housed so that the light receiving part and the light emitting part are exposed, respectively.
The other surface side of the IC chip mounting substrate is provided with a portion to which an IC chip is attached.

In the IC chip mounting substrate of the second aspect of the present invention, since the light receiving element and the light emitting element are mounted on the surface of the substrate, when the IC chip is mounted on the substrate, the distance between the IC chip and the optical component is short, Excellent electrical signal transmission reliability.
Further, the IC chip mounting substrate of the present invention on which the IC chip is mounted can contribute to the miniaturization of the optical communication terminal device because the electronic component and the optical component necessary for optical communication can be integrated. .

Also, in the IC chip mounting substrate of the second aspect of the present invention, a solder resist layer is formed on the outermost layer on the side where the light receiving element or the like is mounted, and solder bumps are formed on the solder resist layer. In this case, the IC chip mounting substrate can be connected to the external substrate via a solder bump. In this case, the IC chip mounting substrate is disposed at a predetermined position by the self-alignment action of the solder. Therefore, accurate optical signal transmission can be performed.

The IC chip mounting substrate of the second aspect of the present invention differs from the IC chip mounting substrate of the first aspect of the present invention in the mounting method of the light receiving element and the light emitting element. That is, in the IC chip mounting substrate of the first invention, the light receiving element and the light emitting element are mounted on one surface of the IC chip mounting substrate, whereas the IC chip mounting board of the second invention is mounted. In the substrate, the light receiving element and the light emitting element are built in or housed (hereinafter simply referred to as housing together) so that the light receiving part and the light emitting part are respectively exposed on one surface side of the IC chip mounting substrate. Yes.

Hereinafter, an embodiment of an IC chip mounting substrate according to the second aspect of the present invention will be described with reference to the drawings.
FIG. 2 is a cross-sectional view schematically showing one embodiment of the IC chip mounting substrate of the second invention. FIG. 2 shows the IC chip mounting substrate on which the IC chip is mounted.

As shown in FIG. 2, the IC chip mounting substrate 220 has a conductive circuit 224 and an interlayer resin insulation layer 222 formed on both surfaces of the substrate 221, and between the conductor circuits sandwiching the substrate 221 and between the interlayer resin insulation layers. The conductor circuits sandwiching 222 are electrically connected by through holes 229 and via holes 227, respectively.
The light receiving element 238 and the light emitting element 239 are housed in the solder resist layer 234 so that the light receiving part 238a and the light emitting part 239a are exposed on one surface side of the IC chip mounting substrate 220, respectively. The light emitting element 239 is connected to the conductor circuit 224 through the conductor layer 242.
Also, solder bumps 237 are formed on the solder resist layer 234 on the side where the light receiving elements 238 and the like are accommodated, and the IC chip 240 is provided on the other surface of the IC chip mounting substrate 220 via the solder connection portion 243. Has been implemented.

In the IC chip mounting substrate of the second aspect of the present invention, since the light / electric element conversion is performed in the light receiving element and the light emitting element mounted at positions close to the IC chip, the transmission distance of the electric signal is short, and the signal transmission reliability It can be used for higher speed communication.

Further, since the solder bump 237 is formed on the solder resist layer on the one surface side in the IC chip mounting substrate 220, the electric signal sent from the IC chip is sent to the external substrate through the solder bump 237. be able to.
Further, it is possible to supply power necessary for driving the IC chip from the outside of the IC chip mounting substrate 220 via the solder bump 237.

Examples of the light receiving element and the light emitting element mounted on the IC chip mounting substrate of the second aspect of the present invention include, for example, the light receiving element and the light emitting element mounted on the IC chip mounting substrate of the first aspect of the present invention. And the like.

Next, a method for manufacturing the IC chip mounting substrate of the second aspect of the present invention will be described.
(1) First, using the same method as the steps (1) to (8) for manufacturing the IC chip mounting substrate of the first invention, a conductor circuit and an interlayer resin insulation layer are laminated on both sides. At the same time, a substrate in which via holes and through holes are formed is manufactured.

(2) Next, a solder resist layer is formed on the outermost layer of the substrate on which the conductor circuit and the interlayer resin insulating layer are formed.
The solder resist layer can be formed using a method similar to the step (9) of the IC chip mounting substrate according to the first aspect of the present invention.
The exposed surface of the solder resist layer forms the same surface as the light receiving surface of the light receiving element and the light emitting surface of the light emitting element. For example, the thickness of the light receiving element and the light emitting element is 300 μm. When the solder connection height is 50 μm, the thickness of the solder resist layer is 350 μm. However, depending on the case, the thickness of the solder resist layer does not need to be strictly 350 μm, and may be, for example, 300 to 400 μm.

(3) Next, an opening for forming solder bumps and an opening for housing optical elements are formed in the solder resist layer.
The opening for forming the solder bump is formed by using the same method as the step (10) for manufacturing the IC chip mounting substrate of the first aspect of the invention, that is, the same method as the method for forming the via hole opening. Can be done.
The opening for storing the optical element can be formed by using the same method as that for forming the opening for forming solder bumps.
Also, when forming the solder resist layer, a solder film having an opening for forming a solder bump and an opening for housing an optical element is prepared by preparing a resin film having an opening at a desired position in advance and pasting the resin film. A resist layer may be formed.

(4) Next, the conductor circuit portion exposed by forming the opening for forming the solder bump is covered as necessary to form a solder pad. Specifically, for example, the coating layer is formed using the same method as the step (11) of the IC chip mounting substrate according to the first aspect of the present invention.
In this step, it is desirable to form a coating layer also on the conductor circuit portion exposed by forming the optical element storage opening.

(5) Next, a solder bump is formed by reflowing after filling the solder pad with a solder paste through a mask in which an opening is formed in a portion corresponding to the solder pad.

(6) Further, the light receiving element and the light emitting element are accommodated in the solder resist layer so that the light receiving part and the light emitting part are exposed, respectively. For mounting the optical elements (light receiving element and light emitting element), for example, the optical element housing opening is filled with solder paste in the step (5), and the optical element is attached when reflowing is performed. Therefore, it may be mounted via solder (conductive layer).
Further, the optical element may be mounted using a conductive adhesive or the like instead of the solder.

Further, in the method of performing the steps (2) to (5), after forming the solder resist layer, the optical element is housed. Instead of such a method, the following method is used. Storage of the optical element and formation of solder bumps may be performed.
That is, after the step (1) is performed, a conductor circuit and an interlayer resin insulating layer are laminated and formed on both sides of the substrate, and a via hole and a through hole are formed. The optical element is attached to the conductor circuit via the adhesive.
Next, by applying the solder resist composition to the non-mounting portion of the optical element, or by pressure-bonding the solder resist composition formed into a film having an opening in a portion corresponding to the portion storing the optical element. A solder resist layer in which is stored is formed.

Further, in the same manner as the above steps (3) to (5), solder bumps are formed by forming openings for forming solder bumps, forming a coating layer if necessary, and filling with solder paste.

When these methods are used, a light receiving element and a light emitting element are incorporated or housed on one surface side of the IC chip mounting substrate.
Through such steps, the IC chip mounting substrate of the second aspect of the present invention can be manufactured.

Next, an IC chip mounting substrate according to the third aspect of the present invention will be described.
The IC chip mounting substrate of the third aspect of the present invention is an IC chip mounting substrate in which a conductor circuit and an interlayer resin insulating layer are laminated on both sides of the substrate,
A light receiving element and a light emitting element are embedded on one surface side of the IC chip mounting substrate, an optical path connecting the light receiving part of the light receiving element and an optical signal, and the light emitting part of the light emitting element and the optical signal An optical path to connect the
The other surface side of the IC chip mounting substrate is provided with a portion to which an IC chip is attached.

In the IC chip mounting substrate of the third invention, since the light receiving element and the light emitting element are mounted on the surface of the substrate, when the IC chip is mounted on the substrate, the distance between the IC chip and the optical component is short, Excellent electrical signal transmission reliability.
Further, the IC chip mounting substrate of the present invention on which the IC chip is mounted can contribute to the miniaturization of the optical communication terminal device because the electronic component and the optical component necessary for optical communication can be integrated. .

Also, in the IC chip mounting substrate of the third aspect of the present invention, when a solder resist layer is formed on the outermost layer on the side where the light receiving element or the like is mounted, and solder bumps are formed on the solder resist layer The IC chip mounting substrate can be connected to an external substrate through solder bumps. In this case, the IC chip mounting substrate is disposed at a predetermined position by the self-alignment action of the solder. Therefore, accurate optical signal transmission can be performed.

The IC chip mounting substrate of the third aspect of the present invention differs from the IC chip mounting substrate of the first aspect of the present invention in the mounting method of the light receiving element and the light emitting element. That is, in the IC chip mounting substrate of the first invention, the light receiving element and the light emitting element are mounted on one surface of the IC chip mounting substrate, whereas the IC chip mounting board of the third invention is mounted. In the substrate, a light receiving element and a light emitting element are embedded on one surface side of the IC chip mounting substrate, and an optical path for connecting an optical signal to the light receiving part of the light receiving element and the light emitting part of the light emitting element is secured. Yes.

Hereinafter, an embodiment of a substrate for mounting an IC chip according to a third aspect of the present invention will be described with reference to the drawings.
FIG. 3 is a cross-sectional view schematically showing an embodiment of an IC chip mounting substrate according to the third aspect of the present invention. FIG. 3 shows the IC chip mounting substrate on which the IC chip is mounted.

As shown in FIG. 3, the IC chip mounting substrate 320 has a conductive circuit 324 and an interlayer resin insulation layer 322 laminated on both surfaces of the substrate 321, and between the conductor circuits sandwiching the substrate 321 and between the interlayer resin insulation layers. Conductor circuits sandwiching 322 are electrically connected through through holes 329 and via holes 327, respectively.
In addition, a light receiving element 338 and a light emitting element 339 are respectively embedded in one surface side of the IC chip mounting substrate 320, and are connected to the conductor circuit 324 through the conductor layer 342, and the light receiving unit 338a and the light emitting unit 339a. And an optical path opening 340 for connecting the optical signals.

In the substrate for mounting an IC chip according to the third aspect of the present invention, since the light / electric signal conversion is performed in the light receiving element and the light emitting element mounted at positions close to the IC chip, the transmission distance of the electric signal is short, and the signal transmission reliability is reduced. It can be used for higher speed communication.

Further, since the solder bump 337 is formed on the solder resist layer on one surface side in the IC chip mounting substrate 320, the electric signal sent from the IC chip is sent to the external substrate through the solder bump 337. be able to.
Further, it is possible to supply power necessary for driving the IC chip from the outside of the IC chip mounting substrate 320 via the solder bump 337.

In the IC chip mounting substrate 320, the optical element embedding opening provided for embedding the light receiving element 338 and the light emitting element 339 becomes the optical path opening 340 (340a, 340b) as it is, and the light receiving element 338 and the light emitting element 339 are provided. The optical path opening may be provided only in the light receiving element, the light receiving part of the light emitting element, and the part facing the light emitting part.
In the IC chip mounting substrate 320, the light receiving element 338 and the light emitting element 339 are embedded in the solder resist layer, but the embedded position of the optical element such as the light receiving element is not limited to the solder resist layer, and an optical path is secured. If so, it may be embedded in an interlayer resin insulating layer or a substrate, or may be embedded so as to extend over a plurality of layers.

The optical path may be filled with a resin or the like. In this case, there is no possibility of dust adhering to the light receiving part or the light emitting part or scratching, and the high connection reliability of the optical signal can be ensured more reliably.
The material for filling the optical path is not particularly limited as long as it has low absorption in the communication wavelength band. For example, epoxy resin; UV curable epoxy resin; polyolefin resin; PMMA (polymethyl methacrylate), Examples thereof include acrylic resins such as deuterated PMMA and deuterated fluorinated PMMA; polyimide resins such as fluorinated polyimide; silicone resins such as deuterated silicone resin; polymers produced from benzocyclobutene.

Examples of the light receiving element and light emitting element mounted on the IC chip mounting substrate of the third aspect of the present invention include, for example, the light receiving element and light emitting element mounted on the IC chip mounting substrate of the first aspect of the present invention. And the like.

Next, a method for manufacturing the IC chip mounting substrate of the third aspect of the present invention will be described.
(1) First, using the same method as the steps (1) to (8) for manufacturing the IC chip mounting substrate of the first invention, a conductor circuit and an interlayer resin insulation layer are laminated on both sides. At the same time, a substrate in which via holes and through holes are formed is manufactured.

(2) Next, a solder resist layer is formed on the outermost layer of the substrate on which the conductor circuit and the interlayer resin insulating layer are formed.
The solder resist layer can be formed using a method similar to the step (9) of the IC chip mounting substrate according to the first aspect of the present invention.
In addition, when the light receiving element and the light emitting element are flip chip type components, the thickness of the solder resist layer is larger than the combined thickness of the light receiving element and the light emitting element and their solder connection heights. In the case where the light receiving element and the light emitting element are wire bonding type parts, the thickness of the light receiving element and the light emitting element, and the thickness of the solder connection and the height of the wire portion should be larger than the combined thickness. What is necessary is just to make about 100 micrometers thicker than the case of the said flip chip type | mold component.

(3) Next, an opening for forming a solder bump and an opening for embedding an optical element are formed in the solder resist layer.
The opening for forming the solder bump is formed by using the same method as the step (10) for manufacturing the IC chip mounting substrate of the first aspect of the invention, that is, the same method as the method for forming the via hole opening. Can be done.
The opening for embedding the optical element can be formed using the same method as the formation of the opening for forming the solder bump.
Further, when forming a solder resist layer, a solder film having openings for forming solder bumps and openings for embedding optical elements is prepared by preparing a resin film having openings at desired positions in advance and pasting the resin film. A resist layer may be formed.

(4) Next, the conductor circuit portion exposed by forming the opening for forming the solder bump is covered as necessary to form a solder pad. Specifically, for example, the coating layer is formed using the same method as the step (11) of the IC chip mounting substrate according to the first aspect of the present invention.
In this step, it is desirable to form a coating layer also on the conductor circuit portion exposed by forming the optical element embedding opening.

(5) Next, a solder bump is formed by reflowing after filling the solder pad with a solder paste through a mask in which an opening is formed in a portion corresponding to the solder pad.

(6) Further, the light receiving element and the light emitting element are embedded in the optical resist embedding opening in the solder resist layer. Specifically, in the step (5), the optical element embedding opening is filled with solder paste, and when reflowing is performed, the optical element is attached to the opening through the solder (conductive layer). Just implement it.
Further, the optical element may be mounted using a conductive adhesive or the like instead of the solder.
When the light receiving element and the light emitting element are wire bonding type parts, the wire portion is sealed with a resin, and particularly when the wire portion is a light receiving surface and a light emitting surface, the resin filling the optical path described above is used. Seal.

Moreover, in the method of performing the above steps (2) to (5), after forming the solder resist layer, the optical element is embedded. Instead of such a method, the following method is used. The embedding of the optical element and the formation of solder bumps may be performed. In particular, when an optical path is formed only in a part facing the light receiving part or the light emitting part of the optical element, it is desirable to use the following method.

That is, after the step (1) is performed, a conductor circuit and an interlayer resin insulating layer are laminated and formed on both sides of the substrate, and a via hole and a through hole are formed. The optical element is attached to the conductor circuit via the adhesive.
Next, the solder resist composition is formed by applying the solder resist composition to the non-mounting portion of the optical element or pressing the solder resist composition formed into a film having an opening in the portion corresponding to the optical element. .

Further, in the same manner as the above steps (3) to (5), an optical element is formed by forming a solder bump forming opening and an optical path opening, forming a coating layer if necessary, and filling a solder paste. And embedding solder bumps.
When an optical element is embedded using this method, it is desirable to use a photosensitive resin composition for the solder resist composition and to form an optical path opening by exposure and development. This is because when the optical path opening is formed by laser processing, the surface of the optical element, in particular, the light receiving portion or the light emitting portion may be damaged.
Further, other than the solder resist layer, for example, when an optical element is embedded in an interlayer resin insulation layer, the optical element is mounted when forming the interlayer resin insulation layer, and after the solder resist layer is laminated, What is necessary is just to form an optical path.

When these methods are used, a light receiving element and a light emitting element are embedded on one surface side of the IC chip mounting substrate.
By passing through such a process, the IC chip mounting substrate of the third aspect of the present invention can be manufactured.

Hereinafter, the present invention will be described in more detail.
Example 1
A. Preparation of resin film for interlayer resin insulation layer 30 parts by weight of bisphenol A type epoxy resin (epoxy equivalent 469, Epicoat 1001 manufactured by Yuka Shell Epoxy), cresol novolac type epoxy resin (epoxy equivalent 215, manufactured by Dainippon Ink and Chemicals, Inc.) N-673) 40 parts by weight, triazine structure-containing phenol novolak resin (phenolic hydroxyl group equivalent 120, Phenolite KA-7052 made by Dainippon Ink & Chemicals, Inc.), ethyl diglycol acetate 20 parts by weight, solvent naphtha 20 parts by weight The solution was dissolved by heating with stirring to 15 parts by weight, and 15 parts by weight of terminal epoxidized polybutadiene rubber (Danalex R-45EPT manufactured by Nagase Kasei Kogyo Co., Ltd.) and pulverized 2-phenyl-4,5-bis (hydroxymethyl) imidazole 1.5 Part by weight, fine Crushed silica 2 parts by weight, it was added 0.5 part by weight of silicon antifoaming agent to prepare an epoxy resin composition.
The obtained epoxy resin composition was applied on a PET film having a thickness of 38 μm using a roll coater so that the thickness after drying was 50 μm, and then dried at 80 to 120 ° C. for 10 minutes, whereby an interlayer resin was obtained. A resin film for an insulating layer was produced.

B. Preparation of resin composition for filling through-hole 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell Co., Ltd., molecular weight: 310, YL983U), the average particle diameter coated with a silane coupling agent is 1.6 μm, By taking 170 parts by weight of SiO ₂ spherical particles having a maximum particle diameter of 15 μm or less (manufactured by Adtech, CRS 1101-CE) and 1.5 parts by weight of a leveling agent (Senopco Perenol S4) in a container, and stirring and mixing, A resin filler having a viscosity of 45 to 49 Pa · s at 23 ± 1 ° C. was prepared.
As the curing agent, 6.5 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) was used.

C. Manufacture of IC chip mounting substrate (1) Copper-clad laminate in which 18 μm copper foil 28 is laminated on both surfaces of an insulating substrate 21 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.8 mm As a starting material (see FIG. 4A). First, the copper-clad laminate was drilled, subjected to electroless plating, and etched into a pattern to form conductor circuits 24 and through holes 29 on both surfaces of the substrate 21.

(2) An aqueous solution containing NaOH (10 g / l), NaClO ₂ (40 g / l), and Na ₃ PO ₄ (6 g / l) after washing and drying the substrate on which the through hole 29 and the conductor circuit 24 are formed. Conductive circuit including through-hole 29 by performing blackening treatment using as a blackening bath (oxidation bath) and reduction treatment using an aqueous solution containing NaOH (10 g / l) and NaBH ₄ (6 g / l) as a reducing bath A roughened surface (not shown) was formed on the surface of 24 (see FIG. 4B).

(3) After preparing the resin filler described in B above, within 24 hours after preparation by the following method, the conductor circuit non-formed part on one side of the through hole 29 and the substrate 21 and the outer edge part of the conductor circuit 24 A layer of resin filler 30 'was formed on the substrate.
That is, first, a resin filler was pushed into a through hole using a squeegee, and then dried under conditions of 100 ° C. and 20 minutes. Next, a mask having an opening corresponding to the conductor circuit non-formed part is placed on the substrate, and the conductor circuit non-formed part which is a recess is filled with a resin filler using a squeegee, A layer of the resin filler 30 'was formed by drying for 20 minutes (see FIG. 4C).

(4) The surface of the conductor circuit 24 or the land surface of the through hole 29 is applied to one surface of the substrate after the processing of (3) by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.). Polishing was performed so that the resin filler 30 'did not remain, and then buffing was performed to remove scratches due to the belt sander polishing. Such a series of processing was similarly performed on the other surface of the substrate.
Subsequently, the heat processing of 100 degreeC for 1 hour, 120 degreeC for 3 hours, 150 degreeC for 1 hour, and 180 degreeC for 7 hours was performed, and the resin filler layer 30 was formed.

In this way, the surface layer portion of the resin filler 30 and the surface of the conductor circuit 24 formed in the through hole 29 and the conductor circuit non-forming portion are flattened, and the resin filler 30 and the side surface of the conductor circuit 24 are roughened. An insulating substrate was obtained in which the inner wall surface of the through hole 29 and the resin filler 30 were firmly adhered via a roughened surface (not shown) (not shown). (Refer FIG.4 (d)). By this step, the surface of the resin filler layer 30 and the surface of the conductor circuit 24 are flush with each other.

(5) After washing the substrate with water and acid degreasing, soft etching is performed, and then an etching solution is sprayed on both surfaces of the substrate to spray the surface of the conductor circuit 24, the land surface of the through hole 29, and the inner wall. A roughened surface (not shown) on the entire surface of the conductor circuit 24. As an etching solution, an etching solution containing 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride (MEC Etch Bond, manufactured by MEC) was used.

(6) Next, a resin film for an interlayer resin insulation layer that is slightly larger than the substrate prepared in A is placed on the substrate and temporarily bonded under the conditions of a pressure of 0.4 MPa, a temperature of 80 ° C., and a bonding time of 10 seconds. After being cut, the interlayer resin insulating layer 22 was further formed by sticking using a vacuum laminator apparatus by the following method (see FIG. 4E).
That is, a resin film for an interlayer resin insulation layer was subjected to main pressure bonding on a substrate under conditions of a degree of vacuum of 65 Pa, a pressure of 0.4 MPa, a temperature of 80, and a time of 60 seconds, and then thermally cured at 170 ° C. for 30 minutes.

(7) Next, with a CO ₂ gas laser having a wavelength of 10.4 μm through a mask in which a through hole having a thickness of 1.2 mm is formed on the interlayer resin insulating layer 22, a beam diameter of 4.0 mm and a top hat A via hole opening 26 having a diameter of 80 μm was formed in the interlayer resin insulation layer 22 under the conditions of mode, pulse width 8.0 μsec, mask through-hole diameter 1.0 mm, and one shot (see FIG. 5A). .

(8) The substrate on which the via hole opening 26 is formed is immersed in an 80 ° C. solution containing 60 g / l permanganic acid for 10 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulating layer 22. As a result, a roughened surface (not shown) was formed on the surface including the inner wall surface of the opening 26 for the via hole.

(9) Next, the substrate after the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and washed with water.
Further, a catalyst is applied to the surface of the lower interlayer resin insulation layer 22 (including the inner wall surface of the via hole opening 26) by applying a palladium catalyst to the surface of the substrate that has been roughened (roughening depth 3 μm). Nuclei were attached (not shown). That is, the substrate was immersed in a catalyst solution containing palladium chloride (PdCl ₂ ) and stannous chloride (SnCl ₂ ), and the catalyst was applied by depositing palladium metal.

(10) Next, the substrate is immersed in an electroless copper plating aqueous solution having the following composition, and the surface of the interlayer resin insulation layer 22 (including the inner wall surface of the via hole opening 26) and the wall surface of the through hole 29 A thin film conductor layer (electroless copper plating film) 32 having a thickness of 0.6 to 3.0 μm was formed (see FIG. 5B).
[Electroless plating aqueous solution]
NiSO ₄ 0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 100 mg / l
Polyethylene glycol (PEG) 0.10 g / l
[Electroless plating conditions]
40 minutes at a liquid temperature of 30 ° C

(11) Next, a commercially available photosensitive dry film is attached to the substrate on which the thin film conductor layer (electroless copper plating film) 32 is formed, a mask is placed, and exposure is performed at 100 mJ / cm ^2. A plating resist 23 having a thickness of 20 μm was provided by developing with a% sodium carbonate aqueous solution (see FIG. 5C).

(12) Next, the substrate is washed with 50 ° C. water and degreased, washed with 25 ° C. water and further washed with sulfuric acid, and then subjected to electrolytic plating under the following conditions to form a plating resist 23 non-formed portion. Then, an electrolytic copper plating film 33 having a thickness of 20 μm was formed (see FIG. 5D).
[Electrolytic plating solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
(Manufactured by Atotech Japan, Kaparaside HL)
[Electrolytic plating conditions]
Current density 1 A / dm ²
Time 65 minutes Temperature 22 ± 2 ℃

(13) Further, after removing the plating resist 23 with 5% NaOH, the thin film conductor layer under the plating resist 23 is etched and removed with a mixed solution of sulfuric acid and hydrogen peroxide to remove the thin film conductor layer ( A conductor circuit 25 (including via hole 27) having a thickness of 18 μm formed of an electroless copper plating film 32 and an electrolytic copper plating film 33 was formed (see FIG. 6A).

(14) Next, by repeating the steps (5) to (13) above, an upper interlayer resin insulation layer and a conductor circuit were formed in layers (see FIGS. 6B to 6C). ). Further, a roughened surface was formed on the outermost conductor circuit using the same method as used in the step (5).

(15) Next, the photosensitizing property obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight: 4000), 80% by weight of bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) dissolved in methyl ethyl ketone, 15.0 parts by weight, imidazole curing agent (Shikoku Kasei Co., Ltd., trade name: 2E4MZ-CN) 1.6 parts by weight, photofunctional monomer bifunctional acrylic monomer (Nippon Kayaku Co., Ltd., trade name: R604) 4.5 parts by weight, also polyvalent acrylic monomer ( Kyoei Chemical Co., Ltd., trade name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (San Nopco, S-65) Take 1 part by weight in a container, stir and mix to prepare a mixed composition. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photopolymerization initiator for this mixed composition, as a photosensitizer By adding 0.2 part by weight of Michler's ketone (manufactured by Kanto Chemical Co., Inc.), a solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C. was obtained.
The viscosity measurements, B-type viscometer (Tokyo Keiki Co., DVL-B type) when at ^60min -1 of (rpm) Rotor No. In the case of 4, 6 min ⁻¹ (rpm), the rotor No. 3 according.

(16) Next, the solder resist composition is applied in a thickness of 30 μm on both surfaces of the substrate on which the interlayer resin insulation layer 22 and the conductor circuit 25 (including the via hole 27) are formed, and is performed at 70 ° C. for 20 minutes. A drying process was performed at 70 ° C. for 30 minutes to form a solder resist composition layer.

(17) Next, a photomask having a thickness of 5 mm on which a pattern of openings for forming solder bumps is drawn is brought into close contact with the solder resist composition layer on the IC chip mounting side, and exposed to 1000 mJ / cm ² of ultraviolet light to obtain a DMTG solution. And an opening having a diameter of 200 μm was formed.
In addition, a 5 mm thick photomask on which a pattern of solder bump forming openings and optical element mounting openings is drawn is adhered to the layer of the solder resist composition on the optical element mounting side, and exposure is performed under the conditions described above. By performing development processing, an opening having a diameter of 200 μm and an opening having a diameter of 180 μm were formed.
Further, the solder resist composition layer is cured by heating at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours, respectively. A solder resist layer having a thickness of 20 μm, a solder bump forming opening 35 and an optical element mounting opening 31, and a solder resist layer 34 having a thickness of 20 μm (see FIG. 7). (See (a)). In addition, as said solder resist composition, a commercially available solder resist composition can also be used.

(18) Next, the substrate on which the solder resist layer 34 is formed is made of nickel chloride (2.3 × 10 ⁻¹ mol / l), sodium hypophosphite (2.8 × 10 ⁻¹ mol / l), It is immersed in an electroless nickel plating solution having pH = 4.5 containing sodium acid (1.6 × 10 ⁻¹ mol / l) for 20 minutes, and the solder bump forming opening 35 and the optical element mounting opening 31 have a thickness. A 5 μm nickel plating layer was formed. Furthermore, the substrate gold potassium cyanide ^{(7.6 × 10 -3 mol / l} ), ammonium chloride ^{(1.9 × 10 -1 mol / l} ), sodium citrate (1.2 × ¹⁰ -1 mol / l) Immerse in an electroless gold plating solution containing sodium hypophosphite (1.7 × 10 ⁻¹ mol / l) at 80 ° C. for 7.5 minutes to form a thickness of 0 on the nickel plating layer. A 0.03 μm gold plating layer was formed to form solder pads 36.

(19) Next, a solder paste is printed on the solder bump forming opening 35 and the optical element mounting opening 31 formed in the solder resist layer 34, and further, the light receiving element is applied to the solder paste printed on the optical element mounting opening 31. 38 and the light-receiving portion 38a and the light-emitting portion 39a of the light-emitting element 39 are mounted while being aligned, and reflowed at 200 ° C., thereby mounting the light-receiving element 38 and the light-emitting element 39 and solder bumps in the solder bump forming openings 35. 37 was formed as an IC chip mounting substrate.
The light receiving element 38 was made of InGaAs, and the light emitting element 39 was made of InGaAsP (see FIG. 7B).
Through this process, in this example, an IC chip mounting substrate on which the light receiving element and the light emitting element were mounted was manufactured so that the light receiving part and the light emitting part were exposed on one surface thereof.

(Example 2)
(1) First, a substrate having an interlayer resin insulating layer and a conductor circuit laminated on both surfaces thereof was manufactured using the same method as the steps (1) to (14) of Example 1.
(2) Next, a layer of a solder resist composition was formed using the same method as in steps (15) and (16) of Example 1.

(3) Further, a photomask having a thickness of 5 mm on which a pattern of openings for forming solder bumps is drawn is brought into close contact with the solder resist composition layer on the IC chip mounting side, and exposed to 1000 mJ / cm ² of ultraviolet light to obtain a DMTG solution. And an opening having a diameter of 200 μm was formed.
In addition, a 5 mm thick photomask on which a pattern of solder bump forming openings and optical element storage openings is drawn is adhered to the layer of the solder resist composition on the optical element mounting side, and exposure is performed under the above-described conditions. By performing development processing, an opening for forming solder bumps (diameter: 200 μm) and an opening for storing optical elements were formed.
Further, the solder resist composition layer is cured under the same conditions as in (17) of Example 1, and has a solder bump forming opening having a thickness of 20 μm, a solder bump forming opening, A solder resist layer 34 having an optical element storage opening and a thickness of 20 μm was formed.

(4) Next, a coating layer (solder pad) was formed on the solder bump forming opening and the optical element housing opening using the same method as in step (18) of Example 1.
(5) Next, an amount of solder paste required to form solder bumps was printed in the solder bump forming openings formed in the solder resist layer, and the solder paste was also printed in the optical element housing openings. Further, the light receiving element and the light emitting element were housed in the optical element housing opening and reflowed at 200 ° C., whereby the light receiving element and the light emitting element were mounted and solder bumps were formed to form an IC chip mounting substrate. The light receiving element and the light emitting element were the same as those in Example 1.
Through this process, in this embodiment, the IC chip mounting substrate in which the light receiving element and the light emitting element are housed so that the light receiving part and the light emitting part are exposed on one surface side (see FIG. 2). ) Was manufactured.

(Example 3)
(1) First, a substrate having an interlayer resin insulating layer and a conductor circuit laminated on both surfaces thereof was manufactured using the same method as the steps (1) to (14) of Example 1.
(2) Next, a light receiving element and a light emitting element were attached to predetermined positions of the outermost conductor circuit via a conductive adhesive. The light receiving element and the light emitting element were the same as those in Example 1.
(3) Next, a solder resist composition was prepared using the same method as in step (15) of Example 1.
Furthermore, after affixing a resist to the light receiving element and the light receiving part and the light emitting part of the light emitting element attached to the conductor circuit in the step (2), the solder resist composition is applied, and 70 ° C. for 20 minutes, 70 ° C. Then, a drying treatment was performed for 30 minutes to form a layer of the solder resist composition. The thickness of the light receiving element and the light emitting element was 300 μm.

(4) Further, a photomask having a thickness of 5 mm on which a pattern of openings for forming solder bumps is drawn is brought into close contact with the layer of the solder resist composition on the IC chip mounting side, under the same conditions as (17) of Example 1. Exposure and development processes were performed to form solder bump forming openings with a diameter of 200 μm. Similarly, openings for forming solder bumps were formed in the layer of the solder resist composition on the optical element mounting side.
Next, the resist attached to the light receiving part and the light emitting part in the step (3) is removed, and the solder resist composition layer is cured under the same conditions as in (17) of Example 1 to form solder bumps. A solder resist layer having an optical path and an optical path opening formed in a portion facing the light receiving portion and the light emitting portion and having the optical element completely embedded therein was formed. The solder resist layer has a thickness of 450 μm on the IC chip mounting side and 450 μm on the optical element mounting side.

(5) Next, a coating layer (solder pad) was formed in the solder bump forming opening using the same method as in the step (18) of Example 1.
(6) Next, an amount of solder paste necessary for forming the solder bumps was printed in the solder bump forming openings, and solder bumps were formed by reflowing at 250 ° C. to obtain an IC chip mounting substrate.
Through this process, in this embodiment, the light receiving element and the light emitting element are embedded on the one surface side, and the light receiving part of the light receiving element and the light emitting part of the light emitting element are connected to the optical signal. An IC chip mounting substrate with an optical path secured was manufactured.

For the IC chip mounting substrates of Examples 1 to 3 thus obtained, the end face of the optical fiber is disposed at a position facing the light receiving portion of the light receiving element, and the detector is positioned at the position facing the light emitting portion of the light emitting element. After that, after sending an optical signal through an optical fiber and calculating with an IC chip, the optical signal was detected with a detector, and a desired optical signal could be detected.

It is sectional drawing which shows typically one Embodiment of the board | substrate for IC chip mounting of 1st this invention. It is sectional drawing which shows typically one Embodiment of the board | substrate for IC chip mounting of 2nd this invention. It is sectional drawing which shows typically one Embodiment of the board | substrate for IC chip mounting of 3rd this invention. It is sectional drawing which shows typically a part of process of manufacturing the board | substrate for IC chip mounting of 1st this invention. It is sectional drawing which shows typically a part of process of manufacturing the board | substrate for IC chip mounting of 1st this invention. It is sectional drawing which shows typically a part of process of manufacturing the board | substrate for IC chip mounting of 1st this invention. It is sectional drawing which shows typically a part of process of manufacturing the board | substrate for IC chip mounting of 1st this invention.

Explanation of symbols

20 IC chip mounting substrate 21 Substrate 22 Interlayer resin insulating layer 24 Conductor circuit 27 Via hole 29 Through hole 31 Optical element mounting opening 34 Solder resist layer 38 Light receiving element 39 Light emitting element 120, 220, 320 IC chip mounting substrate 121, 221, 321 Substrate 122, 222, 322 Interlayer resin insulation layer 124, 224, 324 Conductor circuit 127, 227, 327 Via hole 129, 229, 329 Through hole 131, 231, 331 Optical element opening 134, 234, 334 Solder resist Layer 138, 238, 338 Light receiving element 139, 239, 338 Light emitting element 140, 240, 340 IC chip 142, 242, 342 Conductive layer

Claims (8)

An IC chip mounting substrate in which a conductor circuit and an interlayer resin insulating layer are laminated on both sides of a substrate,
On one surface side of the IC chip mounting substrate,
On the outermost interlayer resin insulation layer, the outermost conductor circuit electrically connected to the lower conductor circuit through the via hole is formed.
An outermost solder resist layer is formed on the outermost interlayer resin insulation layer and the outermost conductor circuit,
In the optical element storage opening formed in the outermost solder resist layer, the light receiving element and the light emitting element are respectively stored.
The light receiving part of the light receiving element and the light emitting part of the light emitting element are exposed to the outside of the IC chip mounting substrate,
The light receiving element and the light emitting element are each electrically connected to the outermost conductor circuit via a conductor layer,
An IC chip mounting substrate comprising a portion to which an IC chip is attached on the other surface side of the IC chip mounting substrate. The thickness of the solder resist layer is the same as the total thickness of the light receiving element or the light emitting element, the thickness of the outermost conductor circuit, and the thickness of the conductor layer, or the total The IC chip mounting substrate according to claim 1, wherein the substrate is thicker than the measured thickness. The substrate for mounting an IC chip according to claim 1 or 2, wherein an optical path for connecting an optical signal with a light receiving portion of the light receiving element and an optical path for connecting an optical signal with the light emitting portion of the light emitting element are secured. The IC chip mounting substrate according to claim 3, wherein the optical path is an optical path opening. The IC chip mounting substrate according to claim 1, wherein solder bumps are formed on the solder resist layer. The conductor circuit which pinched | interposed the said board | substrate is connected via the through hole, and the conductor circuit which pinched | interposed the said interlayer resin insulation layer is connected via the via hole. IC chip mounting substrate. The IC chip mounting substrate according to claim 1, wherein the light receiving element can be soldered. The substrate for mounting an IC chip according to claim 1, wherein the light emitting element can be soldered.

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