JP4687819B2 - ポストチャージロジックを備えるデータ伝達装置 - Google Patents
ポストチャージロジックを備えるデータ伝達装置 Download PDFInfo
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- JP4687819B2 JP4687819B2 JP2009224251A JP2009224251A JP4687819B2 JP 4687819 B2 JP4687819 B2 JP 4687819B2 JP 2009224251 A JP2009224251 A JP 2009224251A JP 2009224251 A JP2009224251 A JP 2009224251A JP 4687819 B2 JP4687819 B2 JP 4687819B2
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
- H03K19/0966—Self-timed logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Dram (AREA)
- Dc Digital Transmission (AREA)
- Small-Scale Networks (AREA)
Description
20、50 受信部
30、32、60、62 ポストチャージロジック回路部
70 ポストチャージロジック手段
N1、N2、N3、N4 データ駆動素子
Claims (3)
- 増幅されたデータを出力する複数個のデータバスセンスアンプと、
複数個のデータラインそれぞれと接地電源との間につながり、前記複数個のデータバスセンスアンプにより動作する複数個の駆動手段と、
前記複数個の駆動手段が駆動されるに伴い前記複数個のデータバスセンスアンプから印加されたデータを伝送する複数個のデータライン対と、
前記複数個のデータライン対を介し、前記複数個の駆動手段につながる複数個のデータ受信手段と、
前記複数個のデータライン対のうちいずれか一対のみのデータライン上にある一対のデータを受信し、前記複数個のデータライン対の全てに対しポストチャージ動作を行うポストチャージロジック手段とを備え、
前記ポストチャージロジック手段は
前記複数個のデータライン対のうちいずれか一対のデータラインの電圧レベルを検出する検出手段と、
前記検出手段からの出力に応じ、前記複数個のデータライン対の電圧レベルを初期化する初期化手段とを備え、
前記複数個のデータバスセンスアンプそれぞれは一対の駆動手段とつながることを特徴とするポストチャージロジックを備えるデータ伝達装置。 - 前記検出手段は、前記一対のデータラインの電圧レベルを受信するNAND手段と、
前記NAND手段からの出力信号を遅延させる遅延手段と、
前記遅延手段の出力信号を反転させ、前記初期化手段へ伝達するインバータ手段とを備えることを特徴とする請求項1記載のポストチャージロジックを備えるデータ伝達装置。 - 前記初期化手段は複数個のPMOSトランジスタを含み、前記複数個のPMOSトランジスタそれぞれは電源電圧と複数個のデータラインの間にそれぞれ接続されることを特徴とする請求項1又は2記載のポストチャージロジックを備えるデータ伝達装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR24837/1998 | 1998-06-29 | ||
KR10-1998-0024837A KR100365561B1 (ko) | 1998-06-29 | 1998-06-29 | 포스트차지 로직을 갖춘 데이터 전달장치 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11175335A Division JP2000224203A (ja) | 1998-06-29 | 1999-06-22 | ポストチャ―ジロジックを備えるデ―タ伝達装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009303272A JP2009303272A (ja) | 2009-12-24 |
JP4687819B2 true JP4687819B2 (ja) | 2011-05-25 |
Family
ID=19541356
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11175335A Pending JP2000224203A (ja) | 1998-06-29 | 1999-06-22 | ポストチャ―ジロジックを備えるデ―タ伝達装置 |
JP2009224251A Expired - Fee Related JP4687819B2 (ja) | 1998-06-29 | 2009-09-29 | ポストチャージロジックを備えるデータ伝達装置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11175335A Pending JP2000224203A (ja) | 1998-06-29 | 1999-06-22 | ポストチャ―ジロジックを備えるデ―タ伝達装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US6211700B1 (ja) |
JP (2) | JP2000224203A (ja) |
KR (1) | KR100365561B1 (ja) |
TW (1) | TW423222B (ja) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63229511A (ja) * | 1987-03-19 | 1988-09-26 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
JPH0879043A (ja) * | 1994-08-18 | 1996-03-22 | Internatl Business Mach Corp <Ibm> | セルフ・リセット論理回路 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5479646A (en) | 1993-02-19 | 1995-12-26 | Intergraph Corporation | Method and apparatus for obtaining data from a data circuit utilizing alternating clock pulses to gate the data to the output |
US5532622A (en) * | 1995-04-24 | 1996-07-02 | International Business Machines Corporation | Multi-input transition detector with a single delay |
KR0146169B1 (ko) | 1995-06-30 | 1998-12-01 | 김주용 | 포스트 차지 로직에 의한 펄스 전달 장치 |
US6087855A (en) * | 1998-06-15 | 2000-07-11 | International Business Machines Corporation | High performance dynamic multiplexers without clocked NFET |
-
1998
- 1998-06-29 KR KR10-1998-0024837A patent/KR100365561B1/ko not_active IP Right Cessation
-
1999
- 1999-06-22 JP JP11175335A patent/JP2000224203A/ja active Pending
- 1999-06-29 US US09/342,068 patent/US6211700B1/en not_active Expired - Lifetime
- 1999-06-29 TW TW088110955A patent/TW423222B/zh not_active IP Right Cessation
-
2009
- 2009-09-29 JP JP2009224251A patent/JP4687819B2/ja not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63229511A (ja) * | 1987-03-19 | 1988-09-26 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
JPH0879043A (ja) * | 1994-08-18 | 1996-03-22 | Internatl Business Mach Corp <Ibm> | セルフ・リセット論理回路 |
Also Published As
Publication number | Publication date |
---|---|
US6211700B1 (en) | 2001-04-03 |
JP2009303272A (ja) | 2009-12-24 |
KR20000003577A (ko) | 2000-01-15 |
TW423222B (en) | 2001-02-21 |
KR100365561B1 (ko) | 2003-02-19 |
JP2000224203A (ja) | 2000-08-11 |
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