JP4687414B2 - Power semiconductor module - Google Patents

Power semiconductor module Download PDF

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JP4687414B2
JP4687414B2 JP2005332461A JP2005332461A JP4687414B2 JP 4687414 B2 JP4687414 B2 JP 4687414B2 JP 2005332461 A JP2005332461 A JP 2005332461A JP 2005332461 A JP2005332461 A JP 2005332461A JP 4687414 B2 JP4687414 B2 JP 4687414B2
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capacitor
semiconductor module
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power semiconductor
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JP2007142073A (en
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拡 田久保
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Fuji Electric Co Ltd
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Fuji Electric Systems Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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Description

この発明は、産業用交流モータドライブ向け電力変換装置、いわゆるインバータや無停電電源装置（ＵＰＳ）などに用いるパワー半導体モジュールの構成に関する。   The present invention relates to a power semiconductor module used for an industrial AC motor drive power converter, a so-called inverter, uninterruptible power supply (UPS), and the like.

インバータやＵＰＳなどでは、パワー半導体素子をスイッチングすることにより、電力変換を行なっている。電力変換装置の一般的な例を図４ａ，図４ｂに示す。これらは、いずれも多相電源の例として３相交流電源に接続された場合の例である。
すなわち、３相交流電源６は、ダイオード（８ａ〜８ｆ）のブリッジ回路で一旦直流に変換される。整流された直流電源を、電力用半導体素子としての例えばＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）１０ａ〜１０ｆにより、上下アーム交互にスイッチングして交流電力に変換し、負荷であるモータ３に交流電力を供給することにより、モータ３を可変周波数で駆動することができる。 In an inverter or UPS, power conversion is performed by switching a power semiconductor element. A typical example of a power converter is shown in FIGS. 4a and 4b. These are all examples when connected to a three-phase AC power source as an example of a multi-phase power source.
That is, the three-phase AC power supply 6 is once converted into DC by a bridge circuit of diodes (8a to 8f). The rectified DC power source is switched to AC power by alternately switching the upper and lower arms by, for example, IGBTs (insulated gate bipolar transistors) 10a to 10f as power semiconductor elements, and AC power is supplied to the motor 3 as a load. By doing so, the motor 3 can be driven at a variable frequency.

なお、素子１０ａ〜１０ｆにはそれぞれ逆並列にダイオード（ＦＷＤ）１１ａ〜１１ｆが接続されており、１０ａ〜１０ｆがオフした際には負荷電流を還流させる動作をすることが良く知られている。
ＩＧＢＴのスイッチング方法としては、基準正弦波５ａと出力電圧指令５ｂとの大小関係を比較演算部５ｃにて演算させて、スイッチングパターンを決定するＰＷＭ（パルス幅変調）制御が一般に行なわれ、その結果決定されるスイッチングパターンに基づき、駆動回路４を介してＩＧＢＴ素子１０ａ〜１０ｆをスイッチングさせる。 It is well known that diodes (FWD) 11a to 11f are connected in reverse parallel to the elements 10a to 10f, respectively, and operate to return the load current when 10a to 10f are turned off.
As a switching method of the IGBT, PWM (pulse width modulation) control for determining a switching pattern by causing the comparison operation unit 5c to calculate the magnitude relationship between the reference sine wave 5a and the output voltage command 5b is generally performed. Based on the determined switching pattern, the IGBT elements 10 a to 10 f are switched via the drive circuit 4.

一方、上記ＩＧＢＴやＦＷＤなどの電力用半導体素子（チップ）は、１つのモジュール容器２内に実装することで、装置構成・組み立ての簡素化や素子冷却の簡素化が図られている。図４ａ，４ｂでは、点線で示す部分がモジュール容器２内に実装されていることを示すが、整流部８ａ〜８ｆとインバータ回路部１０ａ〜１１ｆを分離して２つ以上のモジュールで構成しても良いし、整流部・インバータ部の中でも各相ごとに分割してモジュール化される場合もある。このモジュール容器２には、多相交流電源６からの入力接続端子２ａ、多相交流を直流に整流した直流出力端子２ｂ、直流電源をインバータ回路側へ接続する端子２ｃおよび負荷３への接続端子２ｄが設けられている。   On the other hand, power semiconductor elements (chips) such as IGBTs and FWDs are mounted in one module container 2, thereby simplifying device configuration / assembly and element cooling. 4a and 4b show that the part indicated by the dotted line is mounted in the module container 2, but the rectifying units 8a to 8f and the inverter circuit units 10a to 11f are separated and configured by two or more modules. In some cases, the rectification unit / inverter unit may be divided into modules for each phase. The module container 2 includes an input connection terminal 2a from the multiphase AC power supply 6, a DC output terminal 2b obtained by rectifying the multiphase AC to DC, a terminal 2c for connecting the DC power supply to the inverter circuit side, and a connection terminal to the load 3. 2d is provided.

図５に図４ａまたは図４ｂの回路パターン例を示す。
１５は放熱板、１６ａ，１６ｂは例えばセラミックス製の絶縁基板を示す。ここでは、絶縁基板１６ａには半導体素子８ａ〜８ｆからなる整流回路部が形成され、絶縁基板１６ｂには半導体素子１０ａ〜１０ｆ，１１ａ〜１１ｆからなるインバータ回路部が形成される。なお、７１ａ〜７１ｅは整流回路部の回路パターン、７２ａ〜７２ｅはインバータ回路部の回路パターンをそれぞれ示している。２ａ〜２ｄは上記の各端子である。 FIG. 5 shows an example of the circuit pattern of FIG. 4a or 4b.
Reference numeral 15 denotes a heat dissipation plate, and 16a and 16b denote insulating substrates made of ceramics, for example. Here, a rectifier circuit unit composed of semiconductor elements 8a to 8f is formed on the insulating substrate 16a, and an inverter circuit unit composed of semiconductor elements 10a to 10f and 11a to 11f is formed on the insulating substrate 16b. 71a to 71e are circuit patterns of the rectifier circuit unit, and 72a to 72e are circuit patterns of the inverter circuit unit. 2a to 2d are the above terminals.

電力変換装置およびパワーモジュールは以上のように構成されるが、これには下記のような問題がある。
すなわち、落雷などによる雷サージや、同系統に接続されている機器の動作に伴う商用電源側からの大きなコモンモードノイズ電流がインバータ機器に印加される場合があり、このコモンモードノイズによりインバータの制御回路が誤動作する場合が生じる。このようなノイズによる誤動作を防止するために、インバータの交流電源入力側にノイズ吸収用コンデンサ（Ｃｉｎ）を接続するのが一般的である。図４ａでは、このようなコモンモードノイズ電流Ｉｓの経路を点線矢印Ｌで示し、コンデンサＣｉｎを符号１４ａ〜１４ｃで示している。 The power conversion device and the power module are configured as described above, but this has the following problems.
In other words, lightning surges caused by lightning strikes, etc., and large common mode noise current from the commercial power supply side due to the operation of equipment connected to the same system may be applied to the inverter equipment. There are cases where the circuit malfunctions. In order to prevent such malfunction due to noise, it is common to connect a noise absorbing capacitor (Cin) to the AC power supply input side of the inverter. In FIG. 4a, the path of such a common mode noise current Is is indicated by a dotted arrow L, and the capacitor Cin is indicated by reference numerals 14a to 14c.

コンデンサ１４ａ〜１４ｃの容量は、産業用等において通常２２００ｐＦないし４７００ｐＦ／相が適用され、その最大コンデンサ容量は、装置において許容される漏洩電流の上限値で規定され、漏洩電流の上限値は電気用品について技術基準を制定した、いわゆる電気用品安全法により１ｍＡ以内と規定されている。例えば、３相交流電源、線間電圧２３０Ｖ、電源周波数６０Ｈｚとすると、漏れ電流値ｉは、
ｉ＝√３×２３０×２π×６０×Ｃｉｎ…（１）
により算出される。例えば、Ｃｉｎ＝４７００（ｐＦ）とすると、ｉ＝０．７ｍＡとなる。 The capacities of the capacitors 14a to 14c are usually 2200pF to 4700pF / phase for industrial use, and the maximum capacitor capacity is defined by the upper limit value of the leakage current allowed in the apparatus. Is defined as 1 mA or less by the so-called Electrical Appliance and Material Safety Law, which established technical standards. For example, assuming a three-phase AC power supply, a line voltage of 230 V, and a power supply frequency of 60 Hz, the leakage current value i is
i = √3 × 230 × 2π × 60 × Cin (1)
Is calculated by For example, when Cin = 4700 (pF), i = 0.7 mA.

一方、図４ｂには、交流モータ３側でのコモンモード高周波漏れ電流（Ｉｍ）の、交流電源側への流出を防止するためのフィルタ回路が示されている。このフィルタ回路はコモンモード直流リアクトル１２およびフィルタコンデンサ１４ｄ，１４ｅから構成され、ＬＣフィルタとして動作する。このフィルタ回路により、ＩＧＢＴが高速スイッチングすることによって発生するモータ側浮遊容量を介する高周波漏れ電流（Ｉｍ）を低減させ、多相交流電源６側に高周波電流が漏洩するのを抑制している。   On the other hand, FIG. 4b shows a filter circuit for preventing the common mode high-frequency leakage current (Im) on the AC motor 3 side from flowing out to the AC power supply side. This filter circuit is composed of a common mode DC reactor 12 and filter capacitors 14d and 14e, and operates as an LC filter. With this filter circuit, the high-frequency leakage current (Im) generated through the motor-side stray capacitance generated by the high-speed switching of the IGBT is reduced, and the leakage of the high-frequency current to the multiphase AC power supply 6 side is suppressed.

以上のように、主回路周辺に設置するフィルタコンデンサ類を、モジュール容器内に内蔵させることで小型化を図るようにしているが、これに類する技術として、例えば特許文献１，２に示すものがある。
特開２０００−３３３４７６号公報 特開２００４−３３５６２５号公報 As described above, the filter capacitors installed around the main circuit are designed to be miniaturized by incorporating them in the module container. As similar techniques, for example, those shown in Patent Documents 1 and 2 are disclosed. is there.
JP 2000-333476 A JP 2004-335625 A

上記特許文献１には、インバータ回路の直流回路部に設置される平滑コンデンサ部（図４ａ，４ｂの符号１に相当）をチップ形状のセラミックコンデンサとし、パワーモジュール内部に配置することにより、配線のインダクタンスを低減する技術が開示されている。しかし、この例では、コンデンサ部品を単にモジュール内に設置するもので、使用する部品点数が増加したり、部品を設置するスペースを必要とするため、パワーモジュール容器が大型化するという問題がある。
また、耐熱性の良い（半導体の使用温度は一般に最大１５０℃であるため、周辺に設置される部品も同じ温度仕様の部品が必要となる）高価なコンデンサが必要になるという問題もある。 In the above-mentioned Patent Document 1, a smoothing capacitor portion (corresponding to reference numeral 1 in FIGS. 4a and 4b) installed in a DC circuit portion of an inverter circuit is a chip-shaped ceramic capacitor, and is arranged inside a power module, thereby A technique for reducing inductance is disclosed. However, in this example, since the capacitor parts are simply installed in the module, the number of parts to be used is increased, and a space for installing the parts is required, so that there is a problem that the power module container is enlarged.
In addition, there is a problem that an expensive capacitor is required which has good heat resistance (the operating temperature of the semiconductor is generally a maximum of 150 ° C., so that the parts installed in the periphery also require parts having the same temperature specifications).

一方、上記特許文献２には、コンデンサ類をモジュール容器内に実装する技術が開示されているが、これも特許文献１と同様にコンデンサのためにパッケージ容器が大型化するという問題がある。
したがって、この発明の課題は、フィルタとして使用するコンデンサを不要とすることで、部品を削減し装置の小型化を図ることにある。 On the other hand, Patent Document 2 discloses a technique for mounting capacitors in a module container. However, similarly to Patent Document 1, there is a problem that the package container is enlarged due to the capacitor.
Accordingly, an object of the present invention is to eliminate the need for a capacitor to be used as a filter, thereby reducing the number of parts and reducing the size of the apparatus.

このような課題を解決するため、請求項１の発明では、単相または多相交流電源に接続され、樹脂ケース内部に半導体素子を内蔵したパワー半導体モジュールであって、放熱用金属ベースと前記半導体素子とを一枚または複数枚の絶縁基板により絶縁する構造を備え、この絶縁基板上に配置される交流入力側回路パターンの交流各相の電極面積の大きさの差が互いに±１０％以内に収まるようにするとともに、前記絶縁基板を、その表面と裏面にそれぞれ導電パターンを有するセラミックス基板とし、その表面と裏面の導電パターンで各相ごとにコンデンサを形成し、裏面の導電パターンにより各相コンデンサの一方の電極を共通に接続して接地し、コモンモードノイズ吸収用フィルタを形成することを特徴とする。
In order to solve such a problem, the invention of claim 1 is a power semiconductor module that is connected to a single-phase or multi-phase AC power source and has a semiconductor element built in a resin case, wherein the metal base for heat dissipation and the semiconductor It has a structure that insulates the element with one or more insulating substrates, and the difference in the electrode area size of each AC phase of the AC input side circuit pattern arranged on this insulating substrate is within ± 10% of each other The insulating substrate is a ceramic substrate having conductive patterns on its front and back surfaces, and a capacitor is formed for each phase with the conductive patterns on the front and back surfaces. One of the electrodes is commonly connected and grounded to form a common mode noise absorbing filter .

請求項２の発明では、直流電源に接続され、樹脂ケース内部に半導体素子を内蔵したパワー半導体モジュールであって、放熱用金属ベースと前記半導体素子とを一枚または複数枚の絶縁基板により絶縁する構造を備え、この絶縁基板上に配置された回路パターンの直流入力の正極側電極および負極側電極面積の大きさの差が互いに±１０％以内に収まるようにするとともに、前記絶縁基板を、その表面と裏面にそれぞれ導電パターンを有するセラミックス基板とし、その表面と裏面の導電パターンで各相ごとにコンデンサを形成し、裏面の導電パターンにより各相コンデンサの一方の電極を共通に接続して接地し、コモンモードノイズ吸収用フィルタを形成することを特徴とする。
上記請求項１および請求項２の発明に記載のパワー半導体モジュールを、共通の樹脂ケース内に収納することができる（請求項３の発明）。
According to a second aspect of the present invention, there is provided a power semiconductor module connected to a direct current power source and having a semiconductor element built in a resin case, wherein the heat radiating metal base and the semiconductor element are insulated by one or a plurality of insulating substrates. A difference in size of the positive electrode side electrode and the negative electrode side electrode area of the DC input of the circuit pattern disposed on the insulating substrate is within ± 10% of each other, and the insulating substrate is A ceramic substrate with conductive patterns on the front and back surfaces is formed, and a capacitor is formed for each phase with the conductive patterns on the front and back surfaces, and one electrode of each phase capacitor is connected in common with the conductive pattern on the back surface and grounded. A common mode noise absorbing filter is formed .
The power semiconductor module according to the first and second aspects of the invention can be housed in a common resin case (the third aspect of the invention).

この発明によれば、パワー半導体モジュールにおける絶縁基板のセラミック層の厚みや材料（比誘電率）を選び、電極パターン面積をほぼ同じとなるようにすることで、絶縁基板の浮遊容量をコンデンサとし各相ごとの容量アンバランスを無くすことにより、従来フィルタとして使用しているコンデンサを不要とし、部品の削減と装置の小型化を図ることができる。   According to the present invention, the thickness and material (relative permittivity) of the ceramic layer of the insulating substrate in the power semiconductor module are selected, and the electrode pattern areas are made substantially the same, whereby the stray capacitance of the insulating substrate is used as a capacitor. Eliminating the capacitance imbalance for each phase eliminates the need for a capacitor that has been used as a conventional filter, thereby reducing the number of parts and the size of the apparatus.

図１はこの発明の実施の形態を示す構成図、図１ａはこの発明による３相インバータを示す回路図である。
図１は、先に図５で説明した３相インバータに対する回路パターン例のうち、特に３相交流電源入力部の回路パターンに特徴を持たせたものである。すなわち、３相交流電源入力部の回路パターン７１ｂ〜７１ｄの面積を互いにほぼ等しくなるように、つまり互いの面積がコンデンサ部品の一般的な精度である±１０％以内に収まるようにしたもので、このことは図５の３相交流電源入力部と比較すれば明瞭である。 FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 1a is a circuit diagram showing a three-phase inverter according to the present invention.
FIG. 1 shows the circuit pattern of the three-phase AC power input unit, among the circuit pattern examples for the three-phase inverter described in FIG. That is, the areas of the circuit patterns 71b to 71d of the three-phase AC power supply input unit are made substantially equal to each other, that is, the areas of each other are kept within ± 10%, which is a general accuracy of the capacitor component, This is clear when compared with the three-phase AC power supply input section of FIG.

これにより、この３相交流電源入力部の回路パターン７１ｂ〜７１ｄと絶縁セラミックス基板１６を挟んで対向する裏面の導体パターンとの間で、図１ａに示すようにそれぞれコンデンサ９１ａ〜９１ｃが形成されることになる。裏面の導体パターンについては後述する。しかも、これらのコンデンサは一方の電極が、絶縁セラミックス基板１６の裏面の導体パターンによって相互に接続された構成となるので、図４ａに示すコンデンサ１４ａ〜１４ｃに相当する。したがって、これまで高価なコンデンサ部品としてモジュール内に設置していた図４ａのコンデンサ１４ａ〜１４ｃが省略可能となる。なお、回路パターン７１ｂ〜７１ｄの面積のばらつきが大きい場合は、各相のコンデンサの容量が不平衡となって漏洩電流が増大してしまうため、回路パターン面積は極力同一となるようにすることが望ましい。   As a result, capacitors 91a to 91c are formed between the circuit patterns 71b to 71d of the three-phase AC power supply input section and the conductor patterns on the back surface facing each other with the insulating ceramic substrate 16 interposed therebetween, as shown in FIG. 1a. It will be. The conductor pattern on the back surface will be described later. Moreover, these capacitors correspond to the capacitors 14a to 14c shown in FIG. 4a because one electrode is connected to each other by the conductor pattern on the back surface of the insulating ceramic substrate 16. Therefore, the capacitors 14a to 14c of FIG. 4a that have been installed in the module as expensive capacitor parts so far can be omitted. In addition, when the variation of the area of circuit patterns 71b-71d is large, since the capacity | capacitance of the capacitor | condenser of each phase will become unbalanced and a leakage current will increase, it is made to make a circuit pattern area the same as much as possible. desirable.

図３に図１または図２のパワーモジュールの断面図を示す。
図示のように、絶縁セラミックス基板１６の表面には通常半導体素子を搭載する回路パターン７１ａ，７１ｂ，７１ｅが形成され、裏面にはベタパターン（導体パターン）１９が形成され、このベタパターン１９が放熱板１５に接合されて用いられる。そして、回路パターン面１７には、ＦＷＤチップ８ａ〜８ｄなどが実装され、各回路パターン７１ａ，７１ｂ，７１ｅと各チップとはアルミニウムワイヤ１８などで接続（配線）されて、先の図１ａ，２ａのような回路が構成される。 FIG. 3 shows a cross-sectional view of the power module of FIG. 1 or FIG.
As shown in the figure, circuit patterns 71a, 71b, 71e for mounting semiconductor elements are usually formed on the surface of the insulating ceramic substrate 16, and a solid pattern (conductor pattern) 19 is formed on the back surface. Used by being joined to the plate 15. Then, FWD chips 8a to 8d and the like are mounted on the circuit pattern surface 17, and each circuit pattern 71a, 71b, 71e and each chip are connected (wired) by an aluminum wire 18 or the like, and the previous FIGS. A circuit like this is configured.

また、セラミック製絶縁基板１６の裏面は、ベタパターン１９を介して銅合金などからなる放熱板１５に半田などにより、ろう付けされる。この放熱板１５を図３のように冷却フィン２０へ取り付けることにより、ＩＧＢＴやＦＷＤで生じる通電時の損失（＝熱）を外気に放散させるようにしている。また、冷却フィン２０は通常、アースラインＥにより大地に接地されており、冷却フィン２０または装置筺体への接触などによる感電を防止するようにしている。なお、裏面のベタパターンを厚くすることにより、放熱板を省略する場合もある。   Further, the back surface of the ceramic insulating substrate 16 is brazed to the heat radiating plate 15 made of a copper alloy or the like via a solid pattern 19 with solder or the like. By attaching the heat radiating plate 15 to the cooling fin 20 as shown in FIG. 3, a loss (= heat) at the time of energization caused by the IGBT or FWD is diffused to the outside air. Further, the cooling fin 20 is normally grounded to the ground by the earth line E so as to prevent an electric shock due to contact with the cooling fin 20 or the apparatus housing. Note that the heat sink may be omitted by increasing the thickness of the solid pattern on the back surface.

また、使用する絶縁セラミックス基板１６のセラミックス材料としては、必要な容量を確保できるよう、比誘電率εrが大きな材料を用いることが望ましい。なお、絶縁基板１６の浮遊容量Ｃは、次の（２）式で与えられる。
Ｃ＝ε0×εr×Ｓ／ｄ…（２）
ここで、ε0：８．８５４×１０-12 εr：セラミックス材料固有の比誘電率
Ｓ：各回路パターンの面積 ｄ：絶縁基板の厚さ
したがって、必要なＣ値が決まれば、上記（２）式に基づき必要材料特性・基板厚さ・回路パターン面積が決定される。因みに、Ｃｉｎ＝４７００ｐＦとするためには、一般的なセラミックス材のεr≒１０、基板厚さ０．２ｍｍとすると、面積Ｓ＝０．０２ｍ2＝１００ｃｍ2となる。 In addition, as the ceramic material of the insulating ceramic substrate 16 to be used, it is desirable to use a material having a large relative dielectric constant ε r so as to ensure a necessary capacity. The stray capacitance C of the insulating substrate 16 is given by the following equation (2).
C = ε 0 × ε r × S / d (2)
Here, ε 0 : 8.854 × 10 −12 ε r : Specific dielectric constant specific to ceramic material
S: Area of each circuit pattern d: Thickness of insulating substrate Accordingly, if a necessary C value is determined, necessary material characteristics, substrate thickness, and circuit pattern area are determined based on the above equation (2). Incidentally, in order to set Cin = 4700 pF, if ε r ≈10 of a general ceramic material and the substrate thickness is 0.2 mm, the area S = 0.02 m 2 = 100 cm 2 .

図２はこの発明の他の実施の形態を示す構成図、図２ａはこの発明による３相インバータを示す回路図である。
図２は、直流回路部としてのフィルタコンデンサ機能を、インバータ用モジュールの正極，負極側に対する回路パターンに持たせたもので、特に正極および負極側の各回路パターン７２ａと７２ｅの面積をほぼ同じとなるようにしたものである。こうすることで、正極および負極側の各回路パターン７２ａ，７２ｅと絶縁セラミックス基板１６を挟んで対向する裏面の導体パターンとの間で、図２ａに示すように、コンデンサ９２ａ，９２ｂが形成される。しかも、これらのコンデンサは、一方の電極が絶縁セラミックス基板１６の裏面の導体パターンによって相互に接続された構成となるので、図４ｂに示すコンデンサ１４ｄ，１４ｅに相当する。したがって、直流側に設けた直流リアクトル１２とともにコモンモードフィルタを構成し、モータ側からの高周波漏洩電流を低減するようにしている。この場合の絶縁基板に必要な容量は、図１と同じく上記（２）式により導出することができる。これにより、これまで高価なコンデンサ部品としてモジュール内に設置していた図４ｂに示すコンデンサ１４ｄ，１４ｅを省略することが可能となる。 FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 2a is a circuit diagram showing a three-phase inverter according to the present invention.
FIG. 2 shows that the filter capacitor function as a DC circuit portion is provided in the circuit pattern for the positive and negative sides of the inverter module. In particular, the areas of the circuit patterns 72a and 72e on the positive and negative sides are almost the same. It was made to become. In this way, capacitors 92a and 92b are formed between the circuit patterns 72a and 72e on the positive electrode and negative electrode sides and the conductor pattern on the back surface facing each other with the insulating ceramic substrate 16 interposed therebetween, as shown in FIG. 2a. . Moreover, these capacitors correspond to the capacitors 14d and 14e shown in FIG. 4B because one of the electrodes is connected to each other by the conductor pattern on the back surface of the insulating ceramic substrate 16. Accordingly, a common mode filter is configured together with the DC reactor 12 provided on the DC side so as to reduce the high-frequency leakage current from the motor side. The capacity necessary for the insulating substrate in this case can be derived from the above equation (2) as in FIG. As a result, it is possible to omit the capacitors 14d and 14e shown in FIG.

なお、図１と図２を別々に説明したが、これらをまとめて１つにしても別々に構成する場合と同様の効果を期待することができる。なお、図２は出力側回路パターン７２ａ〜７２ｅだけでなく、入力側回路パターン７１ａ〜７１ｅにも特徴を持たせた例と言える。また、図１，図２では一枚の絶縁基板１６上に整流回路部およびインバータ回路部を構成したが、回路パターン面積が等しければ、整流回路部，インバータ回路部ごとに絶縁基板を設けるようにしても良く、さらには各相ごとに設けるようにしても良いものである。   Although FIG. 1 and FIG. 2 have been described separately, even if they are combined into one, the same effect can be expected as when they are configured separately. 2 can be said to be an example in which not only the output side circuit patterns 72a to 72e but also the input side circuit patterns 71a to 71e are characterized. 1 and 2, the rectifier circuit unit and the inverter circuit unit are configured on a single insulating substrate 16. However, if the circuit pattern area is equal, an insulating substrate is provided for each rectifier circuit unit and inverter circuit unit. Alternatively, it may be provided for each phase.

この発明の実施の形態を示す構成図Configuration diagram showing an embodiment of the present invention 図１に対応する３相インバータ回路図3-phase inverter circuit diagram corresponding to FIG. この発明の他の実施の形態を示す構成図Configuration diagram showing another embodiment of the present invention 図２に対応する３相インバータ回路図3-phase inverter circuit diagram corresponding to FIG. パワー半導体モジュールを示す断面図Cross-sectional view showing a power semiconductor module 一般的な３相インバータと、その入力側ノイズ電流の説明図Illustration of general three-phase inverter and its input side noise current 一般的な３相インバータと、その高周波電流の説明図Illustration of general three-phase inverter and its high-frequency current 図４ａまたは４ｂの３相インバータの回路パターン図4a or 4b circuit pattern diagram of the three-phase inverter

符号の説明Explanation of symbols

１…平滑コンデンサ、２…モジュール容器、２ａ〜２ｄ…端子、３…モータ、４…駆動回路、５ａ…基準正弦波、５ｂ…出力電圧指令、５ｃ…比較演算部、６…３相交流電源、８ａ〜８ｄ，１１ａ〜１１ｄ…ダイオードチップ、１０ａ〜１０ｄ…ＩＧＢＴ、１２…フィルタリアクトル、１４ａ〜１４ｅ…コンデンサ、１５…放熱板、１６，１６ａ，１６ｂ…絶縁基板、７１ａ〜７１ｅ，７２ａ〜７２ｅ…回路パターン、１８…配線、２０…冷却フィン。   DESCRIPTION OF SYMBOLS 1 ... Smooth capacitor, 2 ... Module container, 2a-2d ... Terminal, 3 ... Motor, 4 ... Drive circuit, 5a ... Reference sine wave, 5b ... Output voltage command, 5c ... Comparison operation part, 6 ... Three-phase alternating current power supply, 8a to 8d, 11a to 11d ... Diode chip, 10a to 10d ... IGBT, 12 ... Filter reactor, 14a to 14e ... Capacitor, 15 ... Heat sink, 16, 16a, 16b ... Insulating substrate, 71a-71e, 72a-72e ... Circuit pattern, 18 ... wiring, 20 ... cooling fin.

Claims (3)

単相または多相交流電源に接続され、樹脂ケース内部に半導体素子を内蔵したパワー半導体モジュールであって、放熱用金属ベースと前記半導体素子とを一枚または複数枚の絶縁基板により絶縁する構造を備え、この絶縁基板上に配置される交流入力側回路パターンの交流各相の電極面積の大きさの差が互いに±１０％以内に収まるようにするとともに、前記絶縁基板を、その表面と裏面にそれぞれ導電パターンを有するセラミックス基板とし、その表面と裏面の導電パターンで各相ごとにコンデンサを形成し、裏面の導電パターンにより各相コンデンサの一方の電極を共通に接続して接地し、コモンモードノイズ吸収用フィルタを形成することを特徴とするパワー半導体モジュール。 A power semiconductor module connected to a single-phase or multi-phase AC power source and incorporating a semiconductor element inside a resin case, wherein the heat dissipation metal base and the semiconductor element are insulated by one or more insulating substrates. Provided that the difference in the electrode area size of each AC phase of the AC input side circuit pattern disposed on the insulating substrate is within ± 10% of each other , and the insulating substrate is disposed on the front surface and the back surface thereof. Each ceramic substrate has a conductive pattern, and a capacitor is formed for each phase with the conductive pattern on the front and back surfaces, and one electrode of each phase capacitor is connected in common with the conductive pattern on the back surface and grounded. A power semiconductor module, wherein an absorption filter is formed . 直流電源に接続され、樹脂ケース内部に半導体素子を内蔵したパワー半導体モジュールであって、放熱用金属ベースと前記半導体素子とを一枚または複数枚の絶縁基板により絶縁する構造を備え、この絶縁基板上に配置された回路パターンの直流入力の正極側電極および負極側電極面積の大きさの差が互いに±１０％以内に収まるようにするとともに、前記絶縁基板を、その表面と裏面にそれぞれ導電パターンを有するセラミックス基板とし、その表面と裏面の導電パターンで各相ごとにコンデンサを形成し、裏面の導電パターンにより各相コンデンサの一方の電極を共通に接続して接地し、コモンモードノイズ吸収用フィルタを形成することを特徴とするパワー半導体モジュール。 A power semiconductor module connected to a DC power source and incorporating a semiconductor element inside a resin case, comprising a structure in which the metal base for heat dissipation and the semiconductor element are insulated by one or a plurality of insulating substrates. The difference in size of the positive electrode side electrode and the negative electrode side electrode area of the DC input of the circuit pattern arranged above is within ± 10% of each other, and the insulating substrate is provided with conductive patterns on the front surface and the back surface, respectively. A common mode noise absorbing filter is formed by forming a capacitor for each phase with a conductive pattern on the front surface and back surface, and grounding by connecting one electrode of each phase capacitor in common with the conductive pattern on the back surface. Forming a power semiconductor module. 前記請求項１または請求項２に記載のパワー半導体モジュールを、共通の樹脂ケース内に収納することを特徴とするパワー半導体モジュール。   The power semiconductor module according to claim 1 or 2 is housed in a common resin case.
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