JP2005251839A - Insulating substrate of power semiconductor module - Google Patents

Insulating substrate of power semiconductor module Download PDF

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JP2005251839A
JP2005251839A JP2004057300A JP2004057300A JP2005251839A JP 2005251839 A JP2005251839 A JP 2005251839A JP 2004057300 A JP2004057300 A JP 2004057300A JP 2004057300 A JP2004057300 A JP 2004057300A JP 2005251839 A JP2005251839 A JP 2005251839A
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insulating substrate
capacitor
module
copper foil
potential
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Akitake Takizawa
聡毅 滝沢
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Fuji Electric Co Ltd
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Fuji Electric Holdings Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the peak value of a radiation noise spectrum without causing an increase in the size or cost of a power converter. <P>SOLUTION: In the inverter circuit (for one phase) shown in the drawing, the switching of an IGBT or an FWD cause a current to flow into a stray capacity (refer to dot line) by charge/discharge and its current passage is shown by a sign 43 (refer to dot and dash line). That current becomes a high frequency noise source, but since the peak value of its noise spectrum is proportional to the area S of the current passage, the peak value can be reduced by contriving the internal structure of a module so that the area S is minimized. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

この発明は、電力変換装置から発生する放射ノイズの低減を図る半導体モジュール内部の絶縁基板構造に関する。   The present invention relates to an insulating substrate structure inside a semiconductor module for reducing radiation noise generated from a power converter.

図６に電力変換装置の代表的な装置であるインバータ主回路の例を示す。
１１は商用の交流電源、１２は交流から直流に変換するダイオード整流器モジュール、１３は大容量の電解コンデンサ、１４はモータなどの負荷、１５は電力用スイッチングデバイスからなり、直流から交流に変換するインバータ用モジュール、１６はスイッチングデバイスのスイッチング時に発生するサージ電圧を抑制するスナバコンデンサで、通常はインバータ用モジュール１５の直近に設置される。１７はダイオード整流器モジュール１２とインバータモジュール１５を冷却する放熱器である。また、インバータ用モジュール１５はＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）１８と、逆並列に接続されているＦＷＤ（フリーホイールダイオード）ダイオード１９の６回路で構成されており、通常はインバータを構成するために、２回路入りのモジュールを３台使用することが多い。 FIG. 6 shows an example of an inverter main circuit which is a typical device of the power conversion device.
11 is a commercial AC power source, 12 is a diode rectifier module that converts AC to DC, 13 is a large-capacity electrolytic capacitor, 14 is a load such as a motor, and 15 is a power switching device, and an inverter that converts DC to AC The module 16 is a snubber capacitor that suppresses a surge voltage generated during switching of the switching device, and is usually installed in the immediate vicinity of the inverter module 15. Reference numeral 17 denotes a radiator that cools the diode rectifier module 12 and the inverter module 15. The inverter module 15 is composed of six circuits of an IGBT (insulated gate bipolar transistor) 18 and an FWD (freewheel diode) diode 19 connected in antiparallel. Often three modules with two circuits are used.

２回路入りのモジュールの外観を図７に、図８にモジュール内部の絶縁基板の構成例を示す。図８（ａ）は上面図、同（ｂ）は側面図である。
図７の符号２０は直流の正側出力電極（Ｐ）、２１は負側出力電極（Ｎ）、２２は負荷側に接続される出力電極（Ｕ）、２３，２４，２５，２６は上アーム側および下アーム側ＩＧＢＴのゲート端子およびエミッタ端子である。また、モジュールの下部２７（ヒートシンクとの接続面）は銅の基板（銅ベース）で構成している。そのため、ヒートシンクと銅ベースは電気的には同電位（アース電位）となる。 FIG. 7 shows an external appearance of a module including two circuits, and FIG. 8 shows a configuration example of an insulating substrate inside the module. FIG. 8A is a top view and FIG. 8B is a side view.
Reference numeral 20 in FIG. 7 is a DC positive output electrode (P), 21 is a negative output electrode (N), 22 is an output electrode (U) connected to the load side, and 23, 24, 25 and 26 are upper arms. These are the gate terminal and emitter terminal of the side and lower arm IGBTs. Further, the lower part 27 (the connection surface with the heat sink) of the module is constituted by a copper substrate (copper base). Therefore, the heat sink and the copper base are electrically at the same potential (ground potential).

図８（ｂ）の符号２８は銅ベース２７上に形成されている絶縁基板で、セラミックなどの絶縁材２９と各電位（Ｐ，Ｕ，Ｎ）の銅パターン１，２，３より構成される。また、Ｐ電位銅はくパターン１の上には、上アーム側ＩＧＢＴチップ３３とＦＷＤチップ３４がマウントされており、Ｕ電位銅はくパターン２の上には、下アーム側ＩＧＢＴチップ３５とＦＷＤチップ３６がマウントされている。   Reference numeral 28 in FIG. 8B denotes an insulating substrate formed on the copper base 27, which is composed of an insulating material 29 such as ceramic and copper patterns 1, 2, and 3 of each potential (P, U, N). . Further, the upper arm side IGBT chip 33 and the FWD chip 34 are mounted on the P potential copper foil pattern 1, and the lower arm side IGBT chip 35 and the FWD are mounted on the U potential copper foil pattern 2. Chip 36 is mounted.

さらに図８（ａ）のように、上アーム側ＩＧＢＴチップ３３およびＦＷＤチップ３４と、Ｕ電位銅はくパターン２との間はワイヤボンディング３７，３８で接続されており、下アーム側ＩＧＢＴチップ３５とＦＷＤチップ３６と、Ｎ電位銅はくパターン３との間はワイヤボンディング３９，４０で接続されている。
また、図９にインバータモジュール（１相分）内で、放射ノイズに影響を及ぼす浮遊容量４１，４２を示す。 Further, as shown in FIG. 8A, the upper arm side IGBT chip 33 and the FWD chip 34 and the U-potential copper foil pattern 2 are connected by wire bonding 37 and 38, and the lower arm side IGBT chip 35 is connected. The FWD chip 36 and the N potential copper foil pattern 3 are connected by wire bonding 39 and 40.
FIG. 9 shows stray capacitances 41 and 42 that affect radiation noise in the inverter module (for one phase).

以上のようなインバータ用モジュール（ＩＧＢＴモジュール）の内部構造は、例えば特許文献１，非特許文献１に、また、インバータ用モジュールと平滑コンデンサを一体化する技術は例えば特許文献２，３などに開示されている。
特開平０６−０６１４０９号公報 ＩＧＢＴ一般展開資料「富士第３世代ＩＧＢＴモジュールＮシリー ズ，アプリケーションマニュアル １９９５−２／２０ 特開２００２−１９７７５３号公報 特開２００３−０９２８４７号公報 The internal structure of the inverter module (IGBT module) as described above is disclosed in, for example, Patent Document 1 and Non-Patent Document 1, and the technology for integrating the inverter module and the smoothing capacitor is disclosed in, for example, Patent Documents 2 and 3. Has been.
Japanese Patent Laid-Open No. 06-061409 IGBT General Deployment Document “Fuji 3rd Generation IGBT Module N Series, Application Manual 1995-2 / 20 JP 2002-197753 A JP 2003-092847 A

通常、電力変換装置を製品化する場合、ＣＩＳＰＲ（国際無線障害特別委員会）規約などで規定されている雑音電界強度（放射ノイズ）を、或る規格値３０ＭＨｚ〜１ＧＨｚ以内に抑える必要がある。
一般に、図６のＩＧＢＴ１８やＦＷＤ１９は、高ｄｖ／ｄｔ（電圧変化率）によるスイッチングが行なわれる。その際、図９に示すＩＧＢＴやＦＷＤの浮遊容量４１，４２は、Ｕ電位が変動するため充放電現象が起こり、それにより電流が流れる。その電流経路は多々存在するが、代表的な電流経路を図１０に符号４３（一点鎖線）で示す。 Usually, when a power converter is commercialized, it is necessary to suppress the noise electric field intensity (radiated noise) defined by CISPR (International Radio Interference Special Committee) regulations or the like within a certain standard value of 30 MHz to 1 GHz.
In general, the IGBT 18 and the FWD 19 in FIG. 6 are switched at a high dv / dt (voltage change rate). At that time, in the floating capacitances 41 and 42 of the IGBT and FWD shown in FIG. 9, the U potential fluctuates, so that a charging / discharging phenomenon occurs, whereby a current flows. There are many current paths, but a typical current path is indicated by reference numeral 43 (a chain line) in FIG.

上記電流経路４３は、モジュール内の各電極，配線を介するＩＧＢＴチップ（またはＦＷＤチップ）とスナバコンデンサ１６との間となる。この経路４３に流れる電流の波形は、その経路の配線抵抗値（図示していない）と各配線インダクタンス値の和（Ｌ＝Ｌ１＋Ｌ２＋Ｌ３＋Ｌ４＋Ｌ５）、および浮遊容量４１，４２によって決まり、その電流スペクトルはその４１または４２の容量値（Ｃ）と電極および各配線インダクタンス値の和（Ｌ）とで決まる共振周波数（ｆｒ＝１／√（Ｌ・Ｃ））でピークとなる。この電流が放射ノイズ源となり、空間に電磁波が放射される。   The current path 43 is between the IGBT chip (or FWD chip) and the snubber capacitor 16 via each electrode and wiring in the module. The waveform of the current flowing through the path 43 is determined by the wiring resistance value (not shown) of the path and the sum of the wiring inductance values (L = L1 + L2 + L3 + L4 + L5) and the stray capacitances 41 and 42, and the current spectrum thereof is 41. Alternatively, a peak occurs at the resonance frequency (fr = 1 / √ (L · C)) determined by the capacitance value (C) of 42 and the sum (L) of the electrode and wiring inductance values. This current becomes a radiation noise source, and electromagnetic waves are radiated into the space.

このような電磁波による或る空間距離地点での電界の最大値は、次の（１）式により求められる。
Ｅｐｅａｋ＝１．３２×１０-14・Ｓ・Ｅｄ／（π2・Ｔ・ｔr・Ｒ） …（１）
Ｅｐｅａｋ：電界のピーク値 Ｓ：電流経路（図１０では４３）の空間的な面積
Ｅｄ：電解コンデンサの電圧 Ｔ：ＩＧＢＴのスイッチング周期
ｔr：ＩＧＢＴまたはＦＷＤのスイッチング時の立ち上がり時間
Ｒ：電流経路（図１０では４３）の抵抗分 The maximum value of the electric field at a certain spatial distance point due to such electromagnetic waves is obtained by the following equation (1).
Epeak = 1.32 × 10 -14 · S · Ed / (π 2 · T · t r · R) ... (1)
Epeak: An electric field peak value S: spatial area Ed current path (in FIG. 10 43): the voltage of the electrolytic capacitor T: switching period of the IGBT t r: Rise time during switching of the IGBT or FWD R: current path ( In FIG. 10, the resistance component 43)

一般に、インバータに適用するモジュールの場合、電流経路４３の共振周波数ｆｒは３０ＭＨｚ付近になることが多く、そのため上記のような規格値をオーバするケースが多い。また、その周波数での電界強度も一般機器に比べて高いため、インバータの周辺機器が誤動作するなどの問題が発生する場合がある。その場合、上記（１）式のｔrを大きくする、すなわちＩＧＢＴやＦＷＤのスイッチング時のｄｖ／ｄｔを緩やかにする対策が講じられているが、トレードオフとしてスイッチング損失が増加するため放熱器の大型化や、素子定格をアップさせるなどの対策が必要となり、装置の大型化やコストアップを招くという問題がある。
したがって、この発明の課題は装置の大型化やコストアップを招くことなく、放射ノイズスペクトルのピーク値を低減することにある。 In general, in the case of a module applied to an inverter, the resonance frequency fr of the current path 43 is often around 30 MHz, and thus there are many cases where the above standard value is exceeded. In addition, since the electric field strength at that frequency is higher than that of general equipment, problems such as malfunction of peripheral equipment of the inverter may occur. In that case, increasing the t r of the equation (1), that is, measures to slow the dv / dt at the time of switching the IGBT and FWD have been followed, the radiator for switching loss increases as a trade-off Measures such as increasing the size and increasing the element rating are required, and there is a problem that the size and cost of the apparatus are increased.
Therefore, an object of the present invention is to reduce the peak value of the radiation noise spectrum without increasing the size of the apparatus and increasing the cost.

このような課題を解決するため、請求項１の発明では、電源からの電力を所定の電力に変換して負荷に供給する電力変換回路を構成する電力用半導体モジュール内部の絶縁基板において、
直流の正側電位となる銅はくパターンと直流の負側電位となる銅はくパターンとの間に、コンデンサまたはコンデンサと抵抗との直列回路を直接接続することを特徴とする。
この請求項１の発明においては、前記コンデンサおよび抵抗をチップタイプのものとすることができる（請求項２の発明）。 In order to solve such a problem, in the invention of claim 1, in the insulating substrate inside the power semiconductor module constituting the power conversion circuit that converts the power from the power source into the predetermined power and supplies it to the load,
A capacitor or a series circuit of a capacitor and a resistor is directly connected between a copper foil pattern that is a positive DC potential and a copper foil pattern that is a negative DC potential.
In the first aspect of the present invention, the capacitor and the resistor can be of a chip type (the second aspect of the present invention).

すなわち、上記（１）式からも明らかなように、電流経路の空間的な面積Ｓが小さければ、放射ノイズスペクトルのピーク値Ｅｐｅａｋを小さくできること、また、抵抗を直列に接続すれば、この抵抗で放射ノイズのエネルギを消費できることに着目している。具体的には、絶縁基板上にコンデンサおよび抵抗を配置することで、ＩＧＢＴチップ，ＦＷＤチップおよびコンデンサで囲まれる面積Ｓを極小にしている。   That is, as is clear from the above equation (1), if the spatial area S of the current path is small, the peak value Epeak of the radiation noise spectrum can be reduced, and if a resistor is connected in series, this resistance We focus on the fact that the energy of radiation noise can be consumed. Specifically, by disposing a capacitor and a resistor on an insulating substrate, the area S surrounded by the IGBT chip, the FWD chip and the capacitor is minimized.

この発明によれば、放射ノイズ源となる高周波電流が流れる経路上の面積を減少させ、さらには抵抗を接続しその抵抗でノイズ放射エネルギを消費させることで、放射ノイズスペクトルのピーク値を低減することができる。その結果、外部機器への動作障害が減るとともに、雑音電界強度規格に容易に適合し、ノイズ対策費用を軽減することが可能になるという利点が得られる。   According to the present invention, the peak value of the radiation noise spectrum is reduced by reducing the area on the path through which the high-frequency current serving as the radiation noise source flows, and further connecting the resistor and consuming the noise radiation energy by the resistor. be able to. As a result, it is possible to obtain an advantage that operation troubles to external devices are reduced, noise electric field strength standards are easily adapted, and noise countermeasure costs can be reduced.

図１はこの発明の第１の実施の形態を示す構成図である。
これは、図８で説明した従来の絶縁基板において、Ｐ電位用銅はくパターン１と、Ｎ電位用銅はくパターン３との間にコンデンサ４を接続した例である。ここに、コンデンサ４としてはチップタイプのものを用い、各銅はくパターンと半田接合することで、放射ノイズ源と高周波電流経路との面積Ｓの低減効果を、より大きくすることができる。 FIG. 1 is a block diagram showing a first embodiment of the present invention.
This is an example in which a capacitor 4 is connected between a P-potential copper foil pattern 1 and an N-potential copper foil pattern 3 in the conventional insulating substrate described in FIG. Here, a chip type capacitor is used as the capacitor 4, and the effect of reducing the area S between the radiation noise source and the high-frequency current path can be further increased by soldering with each copper foil pattern.

図２はこの発明の第２の実施の形態を示す構成図である。
これは、図１に示すものに対し、Ｎ電位用銅はくパターン３とＵ電位用銅はくパターン２の形状を変更し、コンデンサを４ａ，４ｂ，４ｃと複数（ここでは３個）に増やした例である。
図１，２はコンデンサのみを利用する例で、回路的には図４のように表わすことができる。 FIG. 2 is a block diagram showing a second embodiment of the present invention.
This is different from that shown in FIG. 1 in that the shapes of the N-potential copper foil pattern 3 and the U-potential copper foil pattern 2 are changed so that the number of capacitors is 4a, 4b, 4c (three in this case). This is an example.
1 and 2 are examples using only capacitors, and can be expressed as shown in FIG.

図３はこの発明の第２の実施の形態を示す構成図である。
これは、図１，２がコンデンサのみを利用するのに対し、抵抗５を併用（直列接続）する例で、回路図は図５のようになる。このコンデンサや抵抗もチップタイプのものを用いれば、上記と同様の効果を得ることが可能となる。ここでは、コンデンサ４と抵抗５を接続するために新たな銅はくパターン６を用いたが、空間上で接続したり、または抵抗とコンデンサの直列回路が１チップになったものを用いても良い。 FIG. 3 is a block diagram showing a second embodiment of the present invention.
This is an example in which the resistors 5 are used together (in series connection), whereas FIGS. 1 and 2 use only capacitors, and the circuit diagram is as shown in FIG. If these capacitors and resistors are chip type, the same effects as described above can be obtained. In this case, a new copper foil pattern 6 is used to connect the capacitor 4 and the resistor 5, but it is also possible to use a connection in space or a series of resistors and capacitors on a single chip. good.

この発明の第１の実施の形態を示す構成図The block diagram which shows 1st Embodiment of this invention この発明の第２の実施の形態を示す構成図The block diagram which shows 2nd Embodiment of this invention この発明の第３の実施の形態を示す構成図The block diagram which shows 3rd Embodiment of this invention コンデンサのみを用いる場合の回路図Circuit diagram when using only capacitors コンデンサと抵抗との直列接続回路を用いる場合の回路図Circuit diagram when using a series connection circuit of a capacitor and a resistor インバータ主回路の従来例を示す回路図Circuit diagram showing conventional example of inverter main circuit 従来のＩＧＢＴモジュールの外観図External view of conventional IGBT module ＩＧＢＴモジュールの内部構成例図Example of internal configuration of IGBT module インバータモジュール内部の浮遊容量を示す回路図Circuit diagram showing stray capacitance inside inverter module 放射ノイズ源となる電流経路の説明図Explanatory diagram of current path that is a source of radiation noise

符号の説明Explanation of symbols

１…Ｐ電位用銅はくパターン、２…Ｕ電位用銅はくパターン、３…Ｎ電位用銅はくパターン、４，４ａ，４ｂ，４ｃ…コンデンサ、５…抵抗、６…銅はくパターン。

1 ... P-potential copper foil pattern, 2 ... U-potential copper foil pattern, 3 ... N-potential copper foil pattern, 4, 4a, 4b, 4c ... capacitor, 5 ... resistance, 6 ... copper foil pattern .

Claims (2)

電源からの電力を所定の電力に変換して負荷に供給する電力変換回路を構成する電力用半導体モジュール内部の絶縁基板において、
直流の正側電位となる銅はくパターンと直流の負側電位となる銅はくパターンとの間に、コンデンサまたはコンデンサと抵抗との直列回路を直接接続することを特徴とする電力用半導体モジュールの絶縁基板。 In an insulating substrate inside a power semiconductor module that constitutes a power conversion circuit that converts power from a power source into predetermined power and supplies it to a load,
A power semiconductor module characterized in that a capacitor or a series circuit of a capacitor and a resistor is directly connected between a copper foil pattern that is a positive DC potential and a copper foil pattern that is a negative DC potential. Insulating substrate. 前記コンデンサおよび抵抗をチップタイプのものとすることを特徴とする請求項１に記載の電力用半導体モジュールの絶縁基板。

The insulating substrate of the power semiconductor module according to claim 1, wherein the capacitor and the resistor are of a chip type.

JP2004057300A 2004-03-02 2004-03-02 Insulating substrate of power semiconductor module Pending JP2005251839A (en)

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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008042124A (en) * 2006-08-10 2008-02-21 Fuji Electric Holdings Co Ltd Semiconductor power module
JP2010074903A (en) * 2008-09-17 2010-04-02 Fuji Electric Systems Co Ltd Inverter device
JP2011018740A (en) * 2009-07-08 2011-01-27 Nippon Inter Electronics Corp Power semiconductor module
JP2015506102A (en) * 2011-12-07 2015-02-26 トランスフォーム インコーポレーテッド Semiconductor module and manufacturing method thereof
WO2017159029A1 (en) * 2016-03-15 2017-09-21 住友電気工業株式会社 Semiconductor module
JP2018050084A (en) * 2009-05-14 2018-03-29 ローム株式会社 Semiconductor module
JP2018125943A (en) * 2017-01-31 2018-08-09 パナソニックＩｐマネジメント株式会社 Switching power supply
CN110235244A (en) * 2017-02-06 2019-09-13 三菱电机株式会社 Power semiconductor modular and power inverter
JP2020014377A (en) * 2019-09-04 2020-01-23 住友電気工業株式会社 Semiconductor module
WO2020218298A1 (en) * 2019-04-24 2020-10-29 ローム株式会社 Semiconductor device
US11669662B2 (en) 2020-10-29 2023-06-06 Fujitsu Limited Machine learning method and computing system
JP7365405B2 (en) 2019-04-24 2023-10-19 ローム株式会社 semiconductor equipment

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11145376A (en) * 1997-11-04 1999-05-28 Hitachi Ltd Semiconductor device
JP2001144248A (en) * 1999-11-12 2001-05-25 Fuji Electric Co Ltd Semiconductor module
JP2002076256A (en) * 2000-08-30 2002-03-15 Mitsubishi Electric Corp Power semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11145376A (en) * 1997-11-04 1999-05-28 Hitachi Ltd Semiconductor device
JP2001144248A (en) * 1999-11-12 2001-05-25 Fuji Electric Co Ltd Semiconductor module
JP2002076256A (en) * 2000-08-30 2002-03-15 Mitsubishi Electric Corp Power semiconductor device

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008042124A (en) * 2006-08-10 2008-02-21 Fuji Electric Holdings Co Ltd Semiconductor power module
JP2010074903A (en) * 2008-09-17 2010-04-02 Fuji Electric Systems Co Ltd Inverter device
JP2018050084A (en) * 2009-05-14 2018-03-29 ローム株式会社 Semiconductor module
JP2011018740A (en) * 2009-07-08 2011-01-27 Nippon Inter Electronics Corp Power semiconductor module
JP2015506102A (en) * 2011-12-07 2015-02-26 トランスフォーム インコーポレーテッド Semiconductor module and manufacturing method thereof
US9818686B2 (en) 2011-12-07 2017-11-14 Transphorm Inc. Semiconductor modules and methods of forming the same
JPWO2017159029A1 (en) * 2016-03-15 2019-01-17 住友電気工業株式会社 Semiconductor module
WO2017159029A1 (en) * 2016-03-15 2017-09-21 住友電気工業株式会社 Semiconductor module
US10355619B2 (en) 2016-03-15 2019-07-16 Sumitomo Electric Industries, Ltd. Semiconductor module
JP2018125943A (en) * 2017-01-31 2018-08-09 パナソニックＩｐマネジメント株式会社 Switching power supply
CN110235244A (en) * 2017-02-06 2019-09-13 三菱电机株式会社 Power semiconductor modular and power inverter
CN110235244B (en) * 2017-02-06 2023-06-27 三菱电机株式会社 Power semiconductor module and power conversion device
WO2020218298A1 (en) * 2019-04-24 2020-10-29 ローム株式会社 Semiconductor device
JP7365405B2 (en) 2019-04-24 2023-10-19 ローム株式会社 semiconductor equipment
JP2020014377A (en) * 2019-09-04 2020-01-23 住友電気工業株式会社 Semiconductor module
US11669662B2 (en) 2020-10-29 2023-06-06 Fujitsu Limited Machine learning method and computing system

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