JPH11145376A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH11145376A JPH11145376A JP9301575A JP30157597A JPH11145376A JP H11145376 A JPH11145376 A JP H11145376A JP 9301575 A JP9301575 A JP 9301575A JP 30157597 A JP30157597 A JP 30157597A JP H11145376 A JPH11145376 A JP H11145376A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- signal input
- layer
- conductive layer
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Power Conversion In General (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は内部絶縁型の半導体
モジュールに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal insulation type semiconductor module.
【０００２】[0002]
【従来の技術】従来のこの種の半導体装置の構造を図２
に示す。2. Description of the Related Art The structure of a conventional semiconductor device of this type is shown in FIG.
Shown in
【０００３】この図において、１０１は半導体素子、１
０４ａ，１０４ｂ，１０４ｃはソルダー、１０２は絶縁
基板、１０３ａ，１０３ｃは金属層、１０７はヒートシ
ンク、１１０は配線端子１０８，１０９を有する樹脂ケ
ース、１０５は金属ワイヤ、１０６はゲル充填物であ
る。In this figure, reference numeral 101 denotes a semiconductor element, 1
04a, 104b and 104c are solders, 102 is an insulating substrate, 103a and 103c are metal layers, 107 is a heat sink, 110 is a resin case having wiring terminals 108 and 109, 105 is a metal wire, and 106 is a gel filling.
【０００４】絶縁基板１０２は、酸化アルミ，窒化アル
ミなどのセラミックスからなる絶縁材で作られ、その一
方の面には、配線パターンが形成された金属層１０３ａ
が、他方の面には、半田などのろう材による接合を可能
とする為の金属層１０３ｃがそれぞれ設けられている。The insulating substrate 102 is made of an insulating material made of ceramics such as aluminum oxide and aluminum nitride, and has a metal layer 103a on which a wiring pattern is formed on one surface.
However, the other surface is provided with a metal layer 103c for enabling joining with a brazing material such as solder.
【０００５】そして、半導体素子１は、絶縁基板１０２
の一方の面に形成されている金属層１０３ａの所定の部
分にソルダー１０４ａにより接着され、さらに絶縁基板
102のもう一方の面に形成されている金属層１０３ｃ
が、ヒートシンク１０７にソルダー１０４ｂにより積層
される。そして、半導体素子１０１は、金属ワイヤ105
により、金属層１０３ａの所定の部分に対して配線が施
されている。The semiconductor element 1 is provided on an insulating substrate 102.
Is bonded to a predetermined portion of the metal layer 103a formed on one surface of the substrate by a solder 104a,
Metal layer 103c formed on the other surface of 102
Are stacked on the heat sink 107 by the solder 104b. The semiconductor element 101 is connected to the metal wire 105
Thus, a wiring is provided to a predetermined portion of the metal layer 103a.
【０００６】電流入出力用の配線端子１０８および電流
制御信号入力用の配線端子１０９は、金属層１０３ａに
形成されている配線パターンの所定の部分と外部配線を
接続するものである。The current input / output wiring terminal 108 and the current control signal input wiring terminal 109 connect a predetermined portion of a wiring pattern formed on the metal layer 103a to an external wiring.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、前記の
方法では電流入出力用の配線端子および電流制御信号入
力用の配線端子の形状が複雑となるために、部材コスト
が上がる、配線端子の体積分の装置の小型化が出来な
い、端子形状に精度が出ない等の問題がある。形状が複
雑な配線は自己インダクタンスが大きく、半導体装置の
オフ時に電流の跳ね上りを生じ損失の増大，素子の破壊
の原因となる。However, in the above-described method, the shapes of the wiring terminals for inputting and outputting the current and the wiring terminals for inputting the current control signal are complicated, so that the member cost is increased and the volume of the wiring terminal is increased. However, there are problems such as the inability to reduce the size of the device and the inaccuracy of the terminal shape. A wiring having a complicated shape has a large self-inductance, causing a current to jump when the semiconductor device is turned off, causing an increase in loss and destruction of elements.
【０００８】また、電流入出力用の配線に大電流が導通
すると電磁誘導により起電力が電流制御信号入力端子に
重畳され、入出力電流にノイズが発生したり、誤動作を
生じることがある。Further, when a large current is conducted through the current input / output wiring, electromotive force is superimposed on the current control signal input terminal by electromagnetic induction, which may cause noise or malfunction in the input / output current.
【０００９】本発明は、従来のこのような問題点を解決
するためのものであり、その目的は半導体装置の特性の
安定性を得る事である。An object of the present invention is to solve such a conventional problem, and an object of the present invention is to obtain stability of characteristics of a semiconductor device.
【００１０】[0010]
【課題を解決するための手段】本発明による半導体層
は、絶縁層と複数の導電層が交互に積層される支持体
と、複数の導電層の内の１導電層の１領域に搭載され、
１導電層の他の領域と導体によって接続される半導体素
子と、支持体上に搭載される外部端子と、を備えてい
る。さらに、１導電層の他の領域と外部端子とが、複数
の導電層の内、１導電層の下層に位置する他の導電層に
よって電気的に接続される。A semiconductor layer according to the present invention is mounted on a support in which insulating layers and a plurality of conductive layers are alternately stacked, and on one region of one of the plurality of conductive layers.
The semiconductor device includes a semiconductor element connected to another region of the one conductive layer by a conductor, and an external terminal mounted on the support. Further, the other region of the one conductive layer and the external terminal are electrically connected by another conductive layer located below the one conductive layer among the plurality of conductive layers.
【００１１】本発明によれば、１導電層の他の領域と外
部端子とが、この１導電層の下層に位置する他の導電層
によって電気的に接続されるので、支持体上における外
部端子の位置設定の自由度が高くなる。このため、外部
端子の形状を複雑にすることなく、半導体素子と外部端
子とを電気的に接続することができる。従って、外部端
子の配線長が短縮され、配線インダクタンスが低減され
る。According to the present invention, the other region of the one conductive layer and the external terminal are electrically connected to each other by the other conductive layer located below the one conductive layer. Has a higher degree of freedom in position setting. Therefore, the semiconductor element and the external terminal can be electrically connected without complicating the shape of the external terminal. Therefore, the wiring length of the external terminal is reduced, and the wiring inductance is reduced.
【００１２】[0012]
【発明の実施の形態】以下、この発明の実施例を図１，
図３により説明する。BRIEF DESCRIPTION OF THE DRAWINGS FIG.
This will be described with reference to FIG.
【００１３】ただし、本発明は下記の実施例に限られる
ものではない。However, the present invention is not limited to the following embodiments.
【００１４】（実施例１）図１に本発明による、絶縁層
を介して絶縁された２層以上の導電層を持つ支持体の最
上部の導電層に半導体素子を固着した半導体装置の模式
図を示す。Embodiment 1 FIG. 1 is a schematic view of a semiconductor device according to the present invention in which a semiconductor element is fixed to the uppermost conductive layer of a support having two or more conductive layers insulated with an insulating layer interposed therebetween. Is shown.
【００１５】図１において、１０１は半導体素子、１０
４ａ，１０４ｂ，１０４ｃはソルダー、１０２は絶縁樹
脂層、１０３ａ，１０３ｂ，１０３ｃは金属層、１０７
はヒートシンクとなる金属板、１１０は配線端子１０
８，１０９を有する樹脂ケース、１０５は金属ワイヤ、
１０６はゲル充填物である。In FIG. 1, reference numeral 101 denotes a semiconductor element;
4a, 104b and 104c are solders, 102 is an insulating resin layer, 103a, 103b and 103c are metal layers, 107
Is a metal plate serving as a heat sink, 110 is the wiring terminal 10
A resin case having 8,109; 105, a metal wire;
106 is a gel filling.
【００１６】半導体素子１０１のゲートは、金属ワイヤ
１０５により、支持体の最上部における金属層１０３ａ
の所定の部分に対して配線が施されている。The gate of the semiconductor element 101 is connected to the metal layer 103a on the top of the support by a metal wire 105.
The wiring is provided to a predetermined portion.
【００１７】図２に示す従来技術と異なり、絶縁樹脂層
１０２は、エポキシなどの樹脂材で作られ、金属層１０
３ａ，１０３ｂ，１０３ｃと交互に積層されている。最
上層の金属層１０３ａにはソルダー１０４ａにより半導
体素子２０１が接着積層されている。他方の面には、半
田などのろう材による接合を可能とする為の金属層１０
３ｃがそれぞれ設けられソルダー１０４ｂによりヒート
シンクとなる金属板１０７に接合されている。絶縁樹脂
層１０２に挟まれた中間金属層１０３ｂはワイヤ１０５
が接続された金属層１０３ａ及び外部信号入力用端子１
０９と部分的に電気的に接続している。Unlike the prior art shown in FIG. 2, the insulating resin layer 102 is made of a resin material such as epoxy and the like.
3a, 103b and 103c are alternately stacked. The semiconductor element 201 is adhesively laminated on the uppermost metal layer 103a by the solder 104a. On the other surface, a metal layer 10 for enabling joining with a brazing material such as solder is used.
3c are provided, and are joined to the metal plate 107 serving as a heat sink by the solder 104b. The intermediate metal layer 103b sandwiched between the insulating resin layers 102
Connected to the metal layer 103a and the external signal input terminal 1
09 is partially electrically connected.
【００１８】絶縁層を介した金属層は、図３ａに示すよ
うに複数の金属層にまたがる穴部に図３ｂに示す様にク
リーム半田３０４ａを充填し、加熱することにより図３
ｃに示すように各金属層は電気的に接続される。As shown in FIG. 3A, the metal layer via the insulating layer is filled with cream solder 304a as shown in FIG. 3B in a hole extending over a plurality of metal layers, and is heated.
Each metal layer is electrically connected as shown in FIG.
【００１９】本実施例によれば、金属層１０３ｃの任意
の個所と外部信号入力用端子１０９とを接続すれば、ワ
イヤ１０５と、従って半導体素子１０１のゲートと外部
信号入力用端子１０９とを電気的に接続することができ
る。このため、支持体における外部信号入力用端子１０
９の取り出し個所を、金属層１０３ａにおけるワイヤ１
０５の接続部とは別の任意の個所に設けることができ
る。従って、従来のような複雑な形状の外部信号入力用
端子を必要とせず、外部信号入力用端子の配線長を低減
することができる。すなわち、外部信号入力用端子のイ
ンダクタンスを低減することができる。According to this embodiment, if any part of the metal layer 103c is connected to the external signal input terminal 109, the wire 105, and hence the gate of the semiconductor element 101 and the external signal input terminal 109 are electrically connected. Can be connected. For this reason, the external signal input terminal 10
9 is connected to the wire 1 in the metal layer 103a.
05 can be provided at any other location. Therefore, the external signal input terminal having a complicated shape as in the related art is not required, and the wiring length of the external signal input terminal can be reduced. That is, the inductance of the external signal input terminal can be reduced.
【００２０】（実施例２）図４に、本発明をＩＧＢＴ
（絶縁ゲート型バイポーラートランジスター）モジュー
ルに適用した実施例を示す。(Embodiment 2) FIG. 4 shows an IGBT according to the present invention.
An embodiment applied to an (insulated gate bipolar transistor) module will be described.
【００２１】図４ａにモジュールの等価回路を示す。本
ＩＧＢＴモジュールにおいては、２個のＩＧＢＴのそれ
ぞれにフリーホイールダイオード（ＦＷＤ）が接続され
ている。ＩＧＢＴは高速にて動作するために、主配線の
自己インダクタンスが大きいと半導体装置のオフ時に大
きな電流の跳ね上りを生じ損失の増大，素子の破壊の原
因となる。FIG. 4a shows an equivalent circuit of the module. In the present IGBT module, a freewheel diode (FWD) is connected to each of the two IGBTs. Since the IGBT operates at high speed, if the self-inductance of the main wiring is large, a large current jumps up when the semiconductor device is turned off, causing an increase in loss and destruction of elements.
【００２２】また、電流入出力用の配線に大電流が導通
すると電磁誘導により起電力が電流制御信号入力端子に
重畳され、入出力電流にノイズが発生したり、誤動作を
生じることができる。Further, when a large current flows through the current input / output wiring, the electromotive force is superimposed on the current control signal input terminal by electromagnetic induction, so that noise or malfunction may occur in the input / output current.
【００２３】図４ｂに示すように、絶縁樹脂層１０２と
金属層１０３ａ,１０３ｂ,１０３ｃを交互に積層した支
持体の最上部にソルダー１０４ａによりＩＧＢＴ１０１
ａ，ＦＷＤ１０１ｂを積層し、下部にヒートシンクとな
る金属板１０７をソルダー１０４ｂにより接合した。１
１０は電力入出力用端子１０８，信号入力用端子１０９
と一体成形された樹脂ケースであり、内部は全部若しく
は一部をゲル充填物１０６により充填されている。As shown in FIG. 4B, the IGBT 101 is soldered on the uppermost portion of the support having the insulating resin layer 102 and the metal layers 103a, 103b, 103c alternately laminated.
a, the FWD 101b was laminated, and a metal plate 107 serving as a heat sink was joined to the lower portion by a solder 104b. 1
Reference numeral 10 denotes a power input / output terminal 108 and a signal input terminal 109
The resin case is formed integrally with the resin case, and the inside is entirely or partially filled with a gel filler 106.
【００２４】電力入出力用端子１０８、および信号入力
用端子１０９はソルダー１０４ｃにより支持基板最上部
の金属層１０３ａの所定の部分に接合される。The power input / output terminal 108 and the signal input terminal 109 are joined to a predetermined portion of the uppermost metal layer 103a by a solder 104c.
【００２５】金属層１０３ａ上の信号入力用端子１０９
の接合箇所には中間金属層１０３ｂに至る穴が設けてあ
りソルダー１０４ｃを穴部に充填，加熱することにより
中間金属層１０３ｂと信号入力用信号端子１０９が電気
的に接合できる。Signal input terminal 109 on metal layer 103a
A hole reaching the intermediate metal layer 103b is provided in the joint portion of, and the intermediate metal layer 103b and the signal input signal terminal 109 can be electrically connected by filling and heating the hole with the solder 104c.
【００２６】図４ｃに最上部金属層１０３ａに積載され
たＩＧＢＴ，ＦＷＤおよび金属ワイヤ１０５の上面図を
示す。４１１は前述したソルダー１０４ｃによる上部の
金属層１０３ａ，中間の金属層１０４ｂの接続箇所を示
す。FIG. 4c shows a top view of the IGBT, FWD and metal wire 105 stacked on the uppermost metal layer 103a. Reference numeral 411 denotes a connection point between the upper metal layer 103a and the middle metal layer 104b by the above-described solder 104c.
【００２７】また、図４ｄに中間金属層１０３ｂの上面
図を示す。絶縁樹脂層は材質，厚さを適当に選択する
と、絶縁耐電圧かつ高熱伝導を達成できる。また、図４
ｄに示す様に、チップ下位置に中間金属層１０３ｂを配
置し、かつその下部にヒートシンクとなる金属板１０７
が有るので高熱伝導を得ることが出来る。４１２は前述
したソルダー１０４ｃによる上部の金属層１０３ａ，中
間の金属層１０４ｂの接続箇所を示す。FIG. 4D shows a top view of the intermediate metal layer 103b. By appropriately selecting the material and thickness of the insulating resin layer, it is possible to achieve an insulation withstand voltage and high heat conduction. FIG.
As shown in FIG. 4D, an intermediate metal layer 103b is disposed at a position below the chip, and a metal plate 107 serving as a heat sink is provided below the intermediate metal layer 103b.
, High heat conduction can be obtained. Reference numeral 412 denotes a connection point between the upper metal layer 103a and the middle metal layer 104b by the above-described solder 104c.
【００２８】金属層１０３ｂは、絶縁樹脂層１０２のほ
ぼ全面に箔状あるいは板状に広がるように設けられ、互
いに分離された複数の領域に分けられている。複数の領
域は、図４ｃに示す最上層の金属層１０３ａにおける、
ゲート端子Ｇ１，Ｇ２、補助エミッタ端子Ｅ１，Ｅ２、
ＩＧＢＴの主エミッタ電極（ＦＷＤのアノード電極）に
ボンディングされたワイヤとの接続領域、ＩＧＢＴのゲ
ート電極にボンディングされたワイヤとの接続領域のい
ずれかとソルダーにより電気的に接続されている。ゲー
ト端子Ｇ１，Ｇ２、補助エミッタ端子Ｅ１，Ｅ２には、
それぞれ外部信号入力用端子１０９が接続される。ここ
で、金属層１０３ａにおける補助エミッタ端子Ｅ１，Ｅ
２と、金属層１０３ａにおけるＩＧＢＴの主エミッタ電
極（FWDのアノード電極）にボンディングされたワイヤ
との接続領域とは、中間金属層１０３ｂに接続される。The metal layer 103b is provided on almost the entire surface of the insulating resin layer 102 so as to spread like a foil or a plate, and is divided into a plurality of regions separated from each other. The plurality of regions correspond to the uppermost metal layer 103a shown in FIG.
Gate terminals G1, G2, auxiliary emitter terminals E1, E2,
It is electrically connected to one of a connection region with a wire bonded to a main emitter electrode (anode electrode of FWD) of the IGBT and a connection region with a wire bonded to a gate electrode of the IGBT by a solder. The gate terminals G1 and G2 and the auxiliary emitter terminals E1 and E2
An external signal input terminal 109 is connected to each. Here, the auxiliary emitter terminals E1, E in the metal layer 103a
2 and the connection region between the metal layer 103a and the wire bonded to the main emitter electrode of the IGBT (the anode electrode of the FWD) are connected to the intermediate metal layer 103b.
【００２９】本実施例によれば、支持体上の外部信号入
力用端子１０９の位置がＩＧＢＴやＦＷＤの位置に制約
されず、位置の設定に自由度が有る。この点は、ゲート
端子Ｇ１，Ｇ２についても同様である。従って、実施例
１と同様に、外部信号入力用端子１０９の配線長を低減
して、そのインダクタンスを低減することができる。さ
らに、本実施例によれば、金属層１０３ａとＩＧＢＴ，
ＦＷＤを接続するワイヤの配線長を極小化できると共
に、外部信号入力用端子１０９とＩＧＢＴやFWDとの電
気的接続が、面積が広くワイヤなどに比べて低インダク
タンスの中間金属層１０３ｂによってなされる。従っ
て、半導体素子から外部信号入力用端子までの総インダ
クタンスを低減することができる。According to this embodiment, the position of the external signal input terminal 109 on the support is not restricted by the position of the IGBT or FWD, and the position can be set freely. This is the same for the gate terminals G1 and G2. Therefore, similarly to the first embodiment, the wiring length of the external signal input terminal 109 can be reduced, and the inductance thereof can be reduced. Further, according to the present embodiment, the metal layer 103a and the IGBT,
The wiring length of the wire connecting the FWD can be minimized, and the electrical connection between the external signal input terminal 109 and the IGBT or the FWD is made by the intermediate metal layer 103b having a large area and a lower inductance than the wire or the like. Therefore, the total inductance from the semiconductor element to the external signal input terminal can be reduced.
【００３０】以上のような特徴から、本実施例は、ＩＧ
ＢＴモジュールのように、複数個の半導体素子を内蔵
し、従来ならば外部信号入力用端子の形状や金属層１０
３ａのパターン形状が複雑化し配線インダクタンスの増
加を招くような場合に、低インダクタンス化するために
好適である。From the above characteristics, the present embodiment has the
As in the case of a BT module, a plurality of semiconductor elements are built-in.
It is suitable for reducing the inductance when the pattern shape of 3a is complicated and the wiring inductance is increased.
【００３１】本実施例においては、従来方法と比較し信
号入出力配線の自己インダクタンスが減少したことによ
り、電力入出力配線に通電オン／オフした時の電磁誘導
による影響が小さくなりノイズが減少する。In this embodiment, since the self-inductance of the signal input / output wiring is reduced as compared with the conventional method, the influence of electromagnetic induction when the power input / output wiring is turned on / off is reduced and the noise is reduced. .
【００３２】[0032]
【発明の効果】以上のように本発明によれば、電流入出
力用の配線および電流制御信号入力用の配線に絶縁層を
介して絶縁された２層以上の導電層を持つ支持体を用い
ることにより、半導体装置の特性の安定性を得る事がで
きる。As described above, according to the present invention, a support having two or more conductive layers insulated via an insulating layer is used for the current input / output wiring and the current control signal input wiring. Thus, the stability of the characteristics of the semiconductor device can be obtained.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明による半導体装置の一実施例を示す説明
図である。FIG. 1 is an explanatory view showing one embodiment of a semiconductor device according to the present invention.
【図２】本発明による半導体装置の従来例を示す説明図
である。FIG. 2 is an explanatory view showing a conventional example of a semiconductor device according to the present invention.
【図３】本発明による半導体装置の一実施例を示す説明
図である。FIG. 3 is an explanatory view showing one embodiment of a semiconductor device according to the present invention.
【図４】本発明による半導体装置の他の実施例を示す説
明図である。FIG. 4 is an explanatory view showing another embodiment of the semiconductor device according to the present invention.
１０１…半導体素子、１０１ａ…絶縁ゲート型バイポー
ラートランジスター、１０１ｂ…フリーホイールダイオ
ード、１０２…絶縁樹脂層、１０３ａ，103b，１０３ｃ
…金属層、１０４ａ，１０４ｂ，１０４ｃ…ソルダー、
１０５…金属ワイヤ、１０６…ゲル充填物、１０７…金
属板、１０８…電力入出力用端子、109…信号入出力用
端子、１１０…樹脂ケース、３０４ａ，３０４ｂ…クリ
ーム半田。101: semiconductor element, 101a: insulated gate bipolar transistor, 101b: freewheel diode, 102: insulating resin layer, 103a, 103b, 103c
... metal layer, 104a, 104b, 104c ... solder,
105: metal wire, 106: gel filling, 107: metal plate, 108: power input / output terminal, 109: signal input / output terminal, 110: resin case, 304a, 304b: cream solder.
Claims (4)
支持体と、 前記複数の導電層の内の１導電層の１領域に搭載され、
前記１導電層の他の領域と導体によって接続される半導
体素子と、 前記支持体上に搭載される外部端子と、を備え、 前記１導電層の前記他の領域と前記外部端子とが、前記
複数の導電層の内、前記１導電層の下層に位置する他の
導電層によって電気的に接続されることを特徴とする半
導体装置。1. A support in which an insulating layer and a plurality of conductive layers are alternately stacked, and mounted on one region of one conductive layer of the plurality of conductive layers,
A semiconductor element connected to the other region of the one conductive layer by a conductor, and an external terminal mounted on the support, wherein the other region of the one conductive layer and the external terminal are A semiconductor device which is electrically connected to another conductive layer located below the one conductive layer among the plurality of conductive layers.
持体の最上層に位置し、前記１導電層及び前記外部端子
が、前記他の導電層に接合されることを特徴とする半導
体装置。2. The semiconductor according to claim 1, wherein said one conductive layer is located on an uppermost layer of said support, and said one conductive layer and said external terminal are joined to said another conductive layer. apparatus.
持体の最上層に位置し、前記１導電層が前記他の導電層
に接合され、前記外部端子が前記１導電層の前記１領域
及び他の領域とは別の領域に接合されることを特徴とす
る半導体装置。3. The device according to claim 1, wherein said one conductive layer is located on an uppermost layer of said support, said one conductive layer is joined to said another conductive layer, and said external terminal is one of said one conductive layer. A semiconductor device which is bonded to a region different from the region and another region.
内、最下層の導電層にヒートシンクとなる金属板が接合
されることを特徴とする半導体装置。4. The semiconductor device according to claim 1, wherein a metal plate serving as a heat sink is joined to a lowermost one of the plurality of conductive layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9301575A JPH11145376A (en) | 1997-11-04 | 1997-11-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9301575A JPH11145376A (en) | 1997-11-04 | 1997-11-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11145376A true JPH11145376A (en) | 1999-05-28 |
Family
ID=17898603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9301575A Pending JPH11145376A (en) | 1997-11-04 | 1997-11-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11145376A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002082543A1 (en) | 2001-03-30 | 2002-10-17 | Hitachi, Ltd. | Semiconductor device |
| JP2005251839A (en) * | 2004-03-02 | 2005-09-15 | Fuji Electric Holdings Co Ltd | Insulating substrate of power semiconductor module |
| JPWO2014014012A1 (en) * | 2012-07-19 | 2016-07-07 | 三菱電機株式会社 | Power semiconductor module |
-
1997
- 1997-11-04 JP JP9301575A patent/JPH11145376A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002082543A1 (en) | 2001-03-30 | 2002-10-17 | Hitachi, Ltd. | Semiconductor device |
| EP1376696A1 (en) * | 2001-03-30 | 2004-01-02 | Hitachi, Ltd. | Semiconductor device |
| US6943445B2 (en) | 2001-03-30 | 2005-09-13 | Hitachi, Ltd. | Semiconductor device having bridge-connected wiring structure |
| EP1376696A4 (en) * | 2001-03-30 | 2009-08-26 | Hitachi Ltd | Semiconductor device |
| JP2005251839A (en) * | 2004-03-02 | 2005-09-15 | Fuji Electric Holdings Co Ltd | Insulating substrate of power semiconductor module |
| JPWO2014014012A1 (en) * | 2012-07-19 | 2016-07-07 | 三菱電機株式会社 | Power semiconductor module |
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