JP4675973B2 - 微小電子機械装置およびその製造方法ならびに配線基板 - Google Patents
微小電子機械装置およびその製造方法ならびに配線基板 Download PDFInfo
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Description
図1は、本発明の第1実施形態に係る微小電子機械装置Xを示す図であり、図1Aは微小電子機械装置Xの断面図であり、図1Bは微小電子機械機構用配線基板20に実装される微小電子機械部品10の平面図であり、図1Cは微小電子機械機構用配線基板20の平面図である。なお図1Aは、図CのIa−Ia線に沿った断面図である。微小電子機械装置Xは、微小電子機械部品10と、微小電子機械機構用配線基板(以下、単に「配線基板」という。)20と、封止材30と、導電性接続材40とを含んで構成される。
Claims (13)
- 半導体基板、該半導体基板の一方主面に構成される微小電子機械機構、及び該微小電子機械機構に電気的に接続される電極を有する微小電子機械部品と、
前記半導体基板の一方主面に対向する第1主面を有する絶縁基板と、
前記絶縁基板の内部に設けられるとともに、一端が前記第1主面に導出され前記電極に電気的に接続される第1配線導体と、
前記半導体基板の一方主面と前記第1主面との間で前記微小電子機械機構を取り囲むように配置され、前記微小電子機械機構を気密封止するガラスから成る封止材と、
前記封止材から離間した位置で、前記電極と前記第1配線導体の前記一端とを電気的に接続する導電性接続材と、
前記絶縁基板の内部に設けられるとともに、一端が前記第1主面に導出され前記封止材に電気的に接続される少なくとも1つの第2配線導体と、
前記第2配線導体の前記一端と前記封止材との間に設けられた導体パターンと、を備え、
前記微小電子機械部品は、前記半導体基板の内部に設けられ、前記半導体基板の側面に導出される電極層を備える微小電子機械装置。 - 前記封止材は、陽極接合により前記半導体基板に接合可能であることを特徴とする請求項1に記載の微小電子機械装置。
- 前記導電性接続材は、前記封止材の外側で、前記電極と前記第1配線導体の前記一端とを接続することを特徴とする請求項1または2に記載の微小電子機械装置。
- 前記絶縁基板は、前記第1主面側に第1凹部を有し、
前記微小電子機械機構の少なくとも一部は、前記第1凹部内に収容されることを特徴とする請求項1〜3のいずれか1つに記載の微小電子機械装置。 - 前記絶縁基板は、前記第1主面側に第2凹部を有し、
前記封止材の少なくとも一部は、前記第2凹部内に収容されることを特徴とする請求項1〜4のいずれか1つに記載の微小電子機械装置。 - 前記第2凹部は、環状であることを特徴とする請求項5に記載の微小電子機械装置。
- 前記第2配線導体は複数存在し、
前記絶縁基板の内部に設けられるとともに、複数の前記第2配線導体を電気的に接続する第3配線導体を備えることを特徴とする請求項1〜6のいずれか1つに記載の微小電子機械装置。 - 平面視したとき、前記封止材の形状と前記導体パターンの形状は重なることを特徴とする請求項1〜7のいずれか1つに記載の微小電子機械装置。
- 前記微小電子機械部品は、前記半導体基板の内部に設けられ、一端が前記電極層に接続され、他端が前記半導体基板の該一方主面に対向する他方主面または側面に導出される第4配線導体を備えることを特徴とする請求項1〜8のいずれか1つに記載の微小電子機械装置。
- 請求項1〜9のいずれか1つに記載の微小電子機械装置の製造方法であって、
前記絶縁基板における前記導体パターン上に前記封止材を形成する形成工程と、
前記半導体基板の前記一方主面と前記絶縁基板の前記第1主面とを対向させるとともに、前記電極層と前記封止材、及び前記電極と前記導電性接続材をそれぞれ位置合わせする位置合わせ工程と、
前記半導体基板と前記封止材とを陽極接合する接合工程と、
前記導電性接続材を加熱して前記電極と前記第1配線導体の前記一端とを接続する接続工程と、を含み、
前記接合工程は、
前記封止材を加熱する工程と、
前記半導体基板及び前記絶縁基板を介して前記封止材を加圧する工程と、
前記半導体基板内の前記電極層及び前記絶縁基板内の前記第2配線導体を介して前記封止材に電圧を印加する工程と、を含むことを特徴とする微小電子機械装置の製造方法。 - 前記接合工程と前記接続工程とを同時に行うことを特徴とする請求項10に記載の微小電子機械装置の製造方法。
- 請求項1〜9のいずれか1つに記載の微小電子機械装置の製造方法であって、
前記微小電子機械部品を構成要素として含む微小電子機械部品領域を複数有する半導体母基板と、前記絶縁基板を構成要素として含む絶縁基板領域を複数有し、前記各絶縁基板に前記封止材をそれぞれ形成してなる配線母基板との位置合わせを行う位置合わせ工程と、
前記半導体母基板における前記各半導体基板と前記各封止材とを陽極接合する接合工程と、
前記各導電性接続材を加熱して前記電極と前記第1配線導体の前記一端とを接続する接続工程と、
前記各封止材による前記半導体母基板と前記配線母基板との接合体を切断する工程と、を含み、
前記接合工程は、
前記封止材を加熱する工程と、
前記半導体基板及び前記絶縁基板を介して前記封止材を加圧する工程と、
前記半導体基板内の前記電極層及び前記絶縁基板内の前記第2配線導体を介して前記封止材に電圧を印加する工程と、を含むことを特徴とする微小電子機械装置の製造方法。 - 半導体基板、該半導体基板の一方主面に構成される微小電子機械機構、及び該微小電子機械機構に電気的に接続される電極を有する微小電子機械部品のための配線基板であって、
前記半導体基板の一方主面に対向する第1主面を有する絶縁基板と、
前記絶縁基板の内部に設けられるとともに、一端が前記第1主面に導出された第1配線導体と、
前記絶縁基板の前記第1主面に設けられた環状の導体パターンと、
前記導体パターン上に設けられた、前記微小電子機械機構を気密封止するガラスから成る封止材と、を備え、
前記絶縁基板は、前記第1主面側に凹部を有し、
前記封止材の少なくとも一部は、前記凹部内に収容されることを特徴とする配線基板。
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PCT/JP2006/325979 WO2007074846A1 (ja) | 2005-12-26 | 2006-12-26 | 微小電子機械装置およびその製造方法 |
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Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
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US8204352B2 (en) * | 2007-11-29 | 2012-06-19 | Kyocera Corporation | Optical apparatus, sealing substrate, and method of manufacturing optical apparatus |
US8023269B2 (en) * | 2008-08-15 | 2011-09-20 | Siemens Energy, Inc. | Wireless telemetry electronic circuit board for high temperature environments |
US7981765B2 (en) * | 2008-09-10 | 2011-07-19 | Analog Devices, Inc. | Substrate bonding with bonding material having rare earth metal |
US8125042B2 (en) * | 2008-11-13 | 2012-02-28 | Samsung Electronics Co., Ltd. | Semiconductor package and method of manufacturing the same |
JP5468242B2 (ja) * | 2008-11-21 | 2014-04-09 | 株式会社東芝 | Memsパッケージおよびmemsパッケージの製造方法 |
US8304274B2 (en) * | 2009-02-13 | 2012-11-06 | Texas Instruments Incorporated | Micro-electro-mechanical system having movable element integrated into substrate-based package |
TW201103626A (en) * | 2009-04-28 | 2011-02-01 | Corning Inc | Microreactors with connectors sealed thereon; their manufacture |
US9090456B2 (en) | 2009-11-16 | 2015-07-28 | Qualcomm Mems Technologies, Inc. | System and method of manufacturing an electromechanical device by printing raised conductive contours |
TWI397157B (zh) * | 2009-12-28 | 2013-05-21 | 矽品精密工業股份有限公司 | 具微機電元件之封裝結構及其製法 |
FR2968647A1 (fr) * | 2010-12-08 | 2012-06-15 | Kfm Technology | Circuit comportant un composant recouvert d'un capot, procede pour realiser un tel circuit et dispositif pour la mise en oeuvre dudit procede |
US9278849B2 (en) * | 2012-06-15 | 2016-03-08 | The Boeing Company | Micro-sensor package and associated method of assembling the same |
US9791470B2 (en) * | 2013-12-27 | 2017-10-17 | Intel Corporation | Magnet placement for integrated sensor packages |
US10008473B2 (en) | 2014-06-02 | 2018-06-26 | Qorvo Us, Inc. | Power package lid |
US10199313B2 (en) | 2014-06-02 | 2019-02-05 | Qorvo Us, Inc. | Ring-frame power package |
US9666498B2 (en) * | 2014-06-02 | 2017-05-30 | Qorvo Us, Inc. | Ring-frame power package |
JP6981884B2 (ja) * | 2018-01-22 | 2021-12-17 | 京セラ株式会社 | 配線基板、パッケージおよび電子装置 |
JP2019133987A (ja) * | 2018-01-29 | 2019-08-08 | 京セラ株式会社 | 電子部品収納用基板およびこれを用いたパッケージ |
EP3738922A1 (en) * | 2019-05-13 | 2020-11-18 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Hermetic optical component package having organic portion and inorganic portion |
JP7476708B2 (ja) | 2020-07-30 | 2024-05-01 | 日本電気株式会社 | 気密封止パッケージ、赤外線検知器及び気密封止パッケージの製造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003179085A (ja) * | 1996-08-27 | 2003-06-27 | Omron Corp | 電子部品 |
JP2005072420A (ja) * | 2003-08-27 | 2005-03-17 | Kyocera Corp | 電子部品封止用基板およびそれを用いた電子装置の製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0810170B2 (ja) * | 1987-03-06 | 1996-01-31 | 株式会社日立製作所 | 半導体絶対圧力センサの製造方法 |
US5668057A (en) * | 1991-03-13 | 1997-09-16 | Matsushita Electric Industrial Co., Ltd. | Methods of manufacture for electronic components having high-frequency elements |
WO1998009312A1 (fr) * | 1996-08-27 | 1998-03-05 | Omron Corporation | Micro-relais et son procede de fabrication |
FR2780200B1 (fr) * | 1998-06-22 | 2003-09-05 | Commissariat Energie Atomique | Dispositif et procede de formation d'un dispositif presentant une cavite a atmosphere controlee |
JP2001057436A (ja) | 1999-08-18 | 2001-02-27 | Matsushita Electric Ind Co Ltd | 気密封止パッケージおよびその製造方法 |
JP4268480B2 (ja) * | 2003-08-27 | 2009-05-27 | 京セラ株式会社 | 電子部品封止用基板およびそれを用いた電子装置 |
JP2005093645A (ja) * | 2003-09-17 | 2005-04-07 | Sony Corp | 電子デバイス装置及び電子デバイス装置の製造方法 |
JP4312631B2 (ja) | 2004-03-03 | 2009-08-12 | 三菱電機株式会社 | ウエハレベルパッケージ構造体とその製造方法、及びそのウエハレベルパッケージ構造体から分割された素子 |
-
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- 2006-12-26 EP EP06843363.0A patent/EP1978555B1/en not_active Not-in-force
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- 2006-12-26 WO PCT/JP2006/325979 patent/WO2007074846A1/ja active Application Filing
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003179085A (ja) * | 1996-08-27 | 2003-06-27 | Omron Corp | 電子部品 |
JP2005072420A (ja) * | 2003-08-27 | 2005-03-17 | Kyocera Corp | 電子部品封止用基板およびそれを用いた電子装置の製造方法 |
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WO2007074846A1 (ja) | 2007-07-05 |
CN101346815B (zh) | 2012-03-28 |
US8008739B2 (en) | 2011-08-30 |
CN101346815A (zh) | 2009-01-14 |
JPWO2007074846A1 (ja) | 2009-06-04 |
EP1978555A4 (en) | 2012-08-08 |
KR20080080413A (ko) | 2008-09-03 |
KR100995301B1 (ko) | 2010-11-19 |
EP1978555B1 (en) | 2016-12-28 |
US20100176468A1 (en) | 2010-07-15 |
EP1978555A1 (en) | 2008-10-08 |
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