JP4675294B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The invention disclosed in this specification relates to a technique for obtaining a crystalline silicon film (referred to as a crystalline silicon film). For example, the present invention relates to a technique for forming a crystalline silicon film on a glass substrate. The present invention also relates to a technique for obtaining a semiconductor device (for example, a thin film transistor) using the crystalline silicon film.

  A technique for manufacturing a thin film transistor using a silicon film formed on a glass substrate is known. In particular, a technique using an amorphous silicon film formed on a glass substrate has been put into practical use. However, the amorphous silicon film is unsatisfactory in its electrical characteristics, and it has been studied to obtain a crystalline silicon film that can be expected to have higher characteristics.

  As a method for obtaining a crystalline silicon film, a method is known in which an amorphous silicon film is formed on a glass substrate by a plasma CVD method, and further, laser light irradiation or heat treatment is applied to obtain a crystalline silicon film. ing.

  In addition, a technique for obtaining a crystalline silicon film using a metal element that promotes crystallization of silicon in order to lower the heating temperature at the time of crystallization by heat treatment is known. (JP-A-6-232059, JP-A-6-2441039)

  These techniques basically have an amorphous silicon film as a starting film and crystallize the amorphous silicon film. Specifically, the amorphous silicon film is transformed into a crystalline silicon film by introducing a metal element that promotes crystallization of silicon, such as Ni, and further applying heat treatment.

  The above-described method using a metal element that promotes crystallization of silicon is significant in that a crystalline silicon film can be obtained at a temperature that a glass substrate can withstand. However, since the starting film is an amorphous silicon film, uneven growth occurs during the crystal growth, the crystallinity of the obtained crystalline silicon film is not uniform, or the metal element is partially segregated. There's a problem.

  An object of the invention disclosed in this specification is to obtain a crystalline silicon film having high uniformity without causing the above problems.

The invention disclosed in this specification is
Forming a microcrystalline silicon film over a substrate having an insulating surface;
A step of contacting and holding a metal element for promoting crystallization of silicon on the surface of the silicon film;
Applying energy to promote crystallization of the silicon film;
It is characterized by having.

  In the above structure, as a method for forming a microcrystalline silicon film, a low pressure CVD method using trisilane or trisilane may be used. Further, a plasma CVD method may be used.

  In the above configuration, as a method of applying energy, a means by heating can be used. When a glass substrate is used, the heating temperature is preferably 450 ° C. or higher and below the strain point.

  In order to obtain higher crystallinity, it is preferable to use a quartz substrate as the substrate and perform heating at a temperature of 800 ° C. to 1100 ° C.

  In the above configuration, as a method for applying energy, a method using laser light or strong light irradiation can be used. This laser beam or intense light irradiation may be performed alone, but it is more effective to perform it simultaneously with heating or after heating.

Other aspects of the invention are:
Forming a microcrystalline silicon film over a substrate having an insulating surface;
A step of contacting and holding a metal element for promoting crystallization of silicon on the surface of the silicon film;
A step of promoting crystallization of the silicon film by heating and / or irradiation with a laser beam;
It is characterized by having.

  In the above configuration, when a glass substrate is used as the substrate, the heating temperature is preferably 450 ° C. to a temperature below the strain point of the glass substrate. This is to prevent deformation of the glass substrate.

  When a quartz substrate that can withstand high-temperature heating is used, it is preferable that the heating temperature be equal to or higher than the crystallization temperature of the amorphous silicon film. When heating is performed under such conditions, the crystallinity can be extremely increased.

  The crystallization temperature of the amorphous silicon film is 580 ° C. to 620 ° C. although it depends on the deposition method and deposition conditions.

  In particular, in order to increase the crystallinity, the heating temperature is preferably set to 800 ° C. or higher.

Other aspects of the invention are:
Forming a microcrystalline silicon film over a substrate having an insulating surface;
Selectively contacting and holding a metal element that promotes crystallization of silicon on the surface of the silicon film;
Applying energy and allowing the crystallization of the silicon film to proceed in a direction parallel to the substrate;
It is characterized by having.

As the metal element that promotes crystallization of silicon, one or more kinds of elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au can be used. These elements have a concentration remaining in the film of 1 × 10 ¹⁵ atoms cm ^{−3 to} 5 × 10 ¹⁹ atoms cm ⁻³ , preferably 1 × 10 ¹⁵ atoms cm ^{−3 to} 5 × 10 ¹⁸ atoms cm ⁻³ . It is good to be. The concentrations of these metal elements are determined based on the minimum value measured by SIMS (secondary ion analysis method). Further, when viewed at a minute level of about several tens of kilometers, the metal element may be biased. In such a case, the average value may be considered.

  As a method for introducing these metal elements, a method using a solution, a sputtering method or a vapor deposition method, or a plasma treatment or a plasma CVD method can be used. However, the sputtering method, the vapor deposition method, and further the plasma treatment and the plasma CVD method have a drawback that it is difficult to adjust the concentration and that the metal element cannot be uniformly distributed on the surface of the silicon film. In particular, when the metal element is unevenly distributed on the surface of the silicon film, crystallization is uneven and the metal element element is segregated, which is a serious problem.

  On the other hand, a method using a solution is very preferable because the concentration of the metal element to be introduced can be easily adjusted, and the metal element can be uniformly dispersed and held on the surface of the silicon film.

  In the case of using a solution, a solution of the metal element compound or a solution in which the metal element is dissolved in an acid such as hydrofluoric acid can be used.

  For example, when nickel is used as a metal element for promoting crystallization of silicon, nickel compounds such as nickel bromide, nickel acetate, nickel oxalate, nickel carbonate, nickel chloride, nickel iodide, nickel nitrate, nickel sulfate, formic acid At least one selected from nickel, nickel acetylacetonate, nickel 4-cyclohexylbutyrate, nickel oxide, nickel hydroxide, and nickel 2-ethylhexanoate can be used.

  Moreover, what contained Ni in at least one selected from benzene, toluene, xylene, carbon tetrachloride, chloroform, ether, trichloroethylene, and Freon, which are nonpolar solvents, can be used.

  Further, nickel dissolved in hydrofluoric acid, buffer hydrofluoric acid, or an acid such as sulfuric acid can be used. Of course, these solutions may be diluted with an appropriate solvent.

When Fe (iron) is used as the metal element, materials known as iron salts, for example, ferrous bromide (FeBr ₂ 6H ₂ O), ferric bromide (FeBr ₃ 6H ₂ O), ferric acetate 2 iron (Fe (C ₂ H ₃ O ₂ ) ₃ xH ₂ O), ferrous chloride (FeCl ₂ 4H ₂ O), ferric chloride (FeCl ₃ 6H ₂ O), ferric fluoride (FeF ₃ 3H ₂ O), ferric nitrate (Fe (NO ₃ ) ₃ 9H ₂ O), ferrous phosphate (Fe ₃ (PO ₄ ) ₂ 8H ₂ O), ferric phosphate (FePO ₄ 2H ₂ O) ) Can be used. A solution in which iron is dissolved in an acid can also be used.

When Co (cobalt) is used as the metal element, materials known as cobalt salts, such as cobalt bromide (CoBr6H ₂ O), cobalt acetate (Co (C ₂ H ₃ O ₂ ) ₂ 4H ₂ O), cobalt chloride A material selected from (CoCl ₂ 6H ₂ O), cobalt fluoride (CoF ₂ xH ₂ O), and cobalt nitrate (Co (No ₃ ) ₂ 6H ₂ O) can be used. Alternatively, a solution in which iron is dissolved in cobalt can be used.

When Ru (ruthenium) is used as the metal element, a material known as a ruthenium salt, for example, ruthenium chloride (RuCl ₃ H ₂ O) can be used.

When Rh (rhodium) is used as the metal element, a material known as a rhodium salt, for example, rhodium chloride (RhCl ₃ 3H ₂ O) can be used.

When Pd (palladium) is used as the metal element, a material known as a palladium salt, for example, palladium chloride (PdCl ₂ 2H ₂ O) can be used as the compound. A solution in which palladium is dissolved in an acid may be used.

  Palladium is a useful element for obtaining an effect of promoting crystallization after nickel.

When Os (osnium) is used as the metal element, a material known as an osnium salt, for example, osmium chloride (OsCl ₃ ) can be used.

When Ir (iridium) is used as the metal element, a material known as an iridium salt, for example, a material selected from iridium trichloride (IrCl ₃ 3H ₂ O) and iridium tetrachloride (IrCl ₄ ) can be used.

When Pt (platinum) is used as the metal element, a material known as a platinum salt, for example, platinum chloride (PtCl ₄ 5H ₂ O) can be used. Moreover, what dissolved platinum in the acid can be used. Platinum is also an element with high reproducibility.

When Cu (copper) is used as the metal element, cupric acetate (Cu (CH ₃ COO) ₂ ), cupric chloride (CuCl ₂ 2H ₂ O), cupric nitrate (Cu (NO ₃ ) ₂ 3H ₂ Materials selected from O) can be used.

When gold is used as the metal element, a material selected from gold trichloride (AuCl ₃ xH ₂ O) and gold chloride (AuHCl ₄ 4H ₂ O) can be used.

  By using a silicon film having crystallinity as a starting film, crystallization by the action of a metal element that promotes crystallization of silicon proceeds uniformly. A crystalline silicon film having a uniform crystallinity over a wide area can be obtained. In this way, there is no growth unevenness in the course of crystal growth, the crystallinity of the obtained crystalline silicon film is not uniform, and metal elements that promote crystallization of silicon are not segregated. A crystalline silicon film having high crystallinity can be obtained.

(Function)
A crystalline silicon film is formed by heat treatment using a promoting action of a metal element that promotes crystallization of silicon, using a silicon film having microcrystalline properties as a starting film for obtaining a crystalline silicon film. obtain. At this time, since the starting film has microcrystalline properties, crystal growth (or promotion of crystallization) proceeds uniformly. In addition, since crystal growth proceeds while maintaining a uniform film quality, it is possible to suppress a phenomenon in which the metal element is partially concentrated.

  This embodiment shows a process for forming a crystalline silicon film on a glass substrate. First, a silicon oxide film is formed as a base film 102 on the glass substrate 101 to a thickness of 3000 mm by plasma CVD or sputtering.

  In this embodiment, a Corning 1737 glass substrate or a Corning 7059 glass substrate is used as the glass substrate.

Thereafter, a microcrystalline silicon film 104 is directly formed on the base film 102 to a thickness of 1000 mm. Here, a low pressure thermal CVD method is used. The film formation conditions are as follows: a film formation temperature is 580 ° C., a film formation pressure is 5 × 10 ⁻⁴ Torr, and a microcrystalline silicon film is formed using disilane as a source gas. (Fig. 1 (A))

  Here, it is necessary to obtain a microcrystalline silicon film having a dense and uniform grain size. As a method other than the low pressure thermal CVD method, a plasma CVD method can be used.

  Next, the substrate is placed on the spinner 106, and a nickel acetate solution adjusted to a concentration of 10 ppm (weight% of Ni element) is dropped. In this state, a water film 105 of a nickel acetate solution is formed on the microcrystalline silicon film 104 as shown in FIG. (Fig. 1 (B))

  Then, an unnecessary solution is removed using a spinner 106, whereby a film 107 containing nickel element is formed on the microcrystalline silicon film 104. (Figure 1 (C))

When the method using the above solution is adopted as a method for introducing a metal element that promotes crystallization of silicon, the following utility can be obtained.
(1) The concentration of nickel element remaining in the silicon film can be strictly adjusted.
(2) The nickel element can be uniformly distributed on the surface of the silicon film. This is because the film 107 containing nickel element exists as a continuous film on the silicon film 104.

  Heat treatment is performed in the state of FIG. This heat treatment needs to be performed at as high a temperature as possible below the strain point of the glass substrate (preferably 450 ° C. or higher). Here, this heat treatment is performed in a nitrogen atmosphere at 550 ° C. for 4 hours.

  As a result of this heat treatment, the crystallinity of the silicon film 104 having microcrystalline properties is promoted, so that the crystalline silicon film 108 with higher crystallinity is obtained. This crystallization proceeds uniformly evenly since the starting film 104 already has microcrystalline properties. Therefore, a crystalline silicon film with good uniformity can be obtained.

  In this state, nickel element is segregated on the surface of the crystalline silicon film 106. Therefore, the surface is etched over a depth of 500 mm.

  In this embodiment, the laser beam is further irradiated here. When laser light irradiation is performed in this way, higher crystallinity can be obtained.

  Further, heat treatment may be applied after the laser light irradiation. The heat treatment after the laser light irradiation has an effect of reducing defects in the film.

  This embodiment is a method for obtaining a crystalline silicon film by a method different from that shown in FIG. First, as shown in FIG. 2A, a silicon oxide film is formed as a base film 202 to a thickness of 3000 mm on a glass substrate 201. Here, a plasma CVD method is used as a method for forming the silicon oxide film 202. (Fig. 2 (A))

  In this embodiment, a Corning 1737 glass substrate (or Corning 7059 glass substrate) is used as the glass substrate 201.

  When the base film 202 is formed as shown in FIG. 2A, the substrate is placed on the spinner 203 and a nickel acetate salt solution adjusted to a concentration of 10 ppm is dropped. A water film 204 is thus formed. (Fig. 2 (B))

  Then, by removing the excess solution with a spinner, a film 205 containing nickel element is formed in contact with the base film 202. After this, it is effective to perform baking for about 30 minutes at a temperature of about 200 ° C to 300 ° C. (Fig. 2 (C))

  Next, a microcrystalline silicon film 206 is formed to a thickness of 500 mm by low pressure CVD. The film forming conditions are the same as those shown in Example 1. (Fig. 2 (D))

  Next, heat treatment is performed in a nitrogen atmosphere at 550 ° C. for 4 hours to promote crystallinity of the microcrystalline silicon film 206. The upper limit of the heating temperature in this step is determined by the strain point of the glass substrate to be used. For example, when a Corning 1737 glass substrate is used, the upper limit of the heating temperature is 667 ° C. because the strain point is 667 ° C. The heating temperature is preferably as high as possible. Thus, a crystalline silicon film 207 having high crystallinity can be obtained on the glass substrate. (Figure 2 (E))

  This embodiment relates to a process for manufacturing a thin film transistor using the crystalline silicon film obtained in Embodiment 1 or Embodiment 2. FIG. 3 shows a manufacturing process of this example. First, in accordance with the steps shown in Embodiment 1 or Embodiment 2, a base film 302 is formed on a glass substrate 301, and a crystalline silicon film 303 is further formed thereon. Here, the crystalline silicon film 303 has its crystallinity promoted by the action of Ni. (Fig. 3 (A))

  Next, the crystalline silicon film 303 is patterned to form an active layer 304 of the thin film transistor. In this active layer, a source region, a drain region, a channel formation region, and a low concentration impurity region (LDD region) are formed later.

  When the active layer 304 is formed, a silicon oxide film 305 functioning as a gate insulating film is formed to a thickness of 1000 mm by plasma CVD. Further, an aluminum film (not shown) for forming the gate electrode is formed by sputtering to a thickness of 5000 mm. In this aluminum film, 0.2% by weight of scandium is contained in order to suppress abnormal growth of aluminum in a later step.

  In addition to scandium, yttrium, lanthanoid, and actinoid elements can be used.

  Further, anodic oxidation using the aluminum film as an anode is performed to form a dense anodic oxide film (corresponding to 307 in FIG. 3C) on the surface. This anodic oxide film is formed to a thickness of about 100 mm. This anodic oxidation is performed using an ethylene glycol solution whose pH is adjusted to neutral with ammonia as an electrolytic solution. The film thickness can be controlled by the applied voltage.

  Next, this aluminum film is patterned by using a resist mask 309 to form an island-shaped region that becomes a base of the gate electrode 306.

  Further, anodic oxidation is performed using this island-shaped region as an anode. This anodic oxidation is performed using an acidic solution containing citric acid as an electrolytic solution. In this anodic oxidation, a porous anodic oxide 308 is formed. The anodic oxide formed in this anodic oxidation process selectively proceeds only on the side surface of the gate electrode 306 because the resist mask 309 exists. As a result, a porous anodic oxide is formed in the region indicated by 308. (Figure 3 (C))

  Next, the exposed gate insulating film 305 is removed by dry etching means having vertical anisotropy. In this step, the gate insulating film remains just below the gate electrode 306 and the porous anodic oxide as indicated by 310. (Refer to FIG. 3 (D))

  Further, the resist mask 309, the dense anodic oxide film 307, and the porous anodic oxide 308 are removed. The resist mask 309 is removed using a special stripping solution, the dense anodic oxide film is removed using buffer hydrofluoric acid, and the porous anodic oxide 308 is removed using a mixed acid of phosphoric acid, acetic acid and nitric acid. .

  Thereafter, a silicon nitride film 311 is formed to a thickness of 300 mm by plasma CVD. The silicon nitride film 311 covers the surface of the gate electrode 306 made of aluminum, and functions to suppress generation of hillocks and whiskers on the surface of the gate electrode 306. Hillocks and whiskers are protrusions generated by abnormal growth of aluminum during heating or laser light irradiation. In this way, the state shown in FIG.

  Impurity ions are implanted in the state shown in FIG. Here, P (phosphorus) ions are implanted in order to manufacture an N-channel thin film transistor. In this ion implantation, the presence of the silicon nitride film 311 can be ignored since its thickness is small.

  Therefore, by appropriately setting the ion implantation conditions, impurity ions are implanted at a high concentration in the regions 312 and 316, impurity ions are implanted at a low concentration in the regions 313 and 315, and further, the region 314 is implanted in the region 314. Can be in a state where no impurity ions are implanted.

  The reason why the impurity ions are implanted at a low concentration in the regions 313 and 315 is that the gate insulating film 310 exists and the implanted ions are shielded to some extent by the thickness. Of course, since not all of them are shielded, impurity ions are implanted into the regions 313 and 315 at a lower concentration than the regions 312 and 316.

  In this manner, the source region 321, the low concentration impurity regions 313 and 315, the channel formation region 314, and the drain region 316 are formed in a self-aligned manner. Here, the low-concentration impurity region of the region 315 between the channel formation region 314 and the drain region 316 indicated by 315 is a region generally called an LDD (lightly doped drain) region.

  When impurity ions are implanted in the state shown in FIG. 3D, laser light irradiation is further performed in this state to activate the region into which the impurity ions are implanted.

  Next, a silicon oxide film is formed as an interlayer insulating film 318 to a thickness of 6000 mm by plasma CVD. Further, an ITO electrode is formed as the pixel electrode 319. Further, contact holes are formed, and a source electrode 320 and a drain electrode 321 are formed. The source electrode 320 and the drain electrode 321 are formed of a laminated film of a titanium film, an aluminum film, and a titanium film.

  Thus, a thin film transistor constituted by using the crystalline silicon film formed on the glass substrate is completed. Such a thin film transistor is arranged in a pixel region of a liquid crystal electro-optical device having an active matrix type.

  This embodiment is characterized in that a quartz substrate is used as a substrate, and heat treatment for promoting crystallization is performed at a high temperature of 800 ° C. or higher. First, a silicon oxide film is formed as a base film 402 on a quartz substrate 401 to a thickness of 5000 mm. This base film functions to relieve stress acting between the glass substrate and a silicon film to be formed later. Since the thermal expansion coefficients of the quartz substrate and the silicon film are greatly different, it is very effective to form the base film 402 thickly.

  Next, a microcrystalline silicon film 403 is formed to a thickness of 2000 mm by a low pressure thermal CVD method similar to that shown in the first embodiment. (Fig. 1 (A))

  Next, a nickel-containing film (not shown) is formed on the surface of the silicon film 403 using a nickel acetate solution in the same manner as in the first embodiment. By performing heat treatment, the crystallinity of the silicon film 403 is promoted, and a crystalline silicon film having high crystallinity is obtained. Here, this heat treatment is performed under conditions of 800 ° C. and 4 hours. It is effective to perform this heat treatment in the range of 800 ° C. to 1100 ° C.

  Such a high temperature is higher than the crystallization temperature of the amorphous silicon film, and is an effective heating condition for obtaining high crystallinity.

  Next, a silicon oxide film 404 is formed on the surface of the silicon film 403 by using a thermal oxidation method. Here, a silicon oxide film is formed to a thickness of 1000 mm. This step is performed in an oxidizing atmosphere at a temperature of 900 ° C. In this step, the thickness of the silicon oxide film is reduced to about 1500 mm. At this time, nickel element which promoted crystallization of the silicon film in the previous heat treatment is segregated in the silicon oxide film. (Fig. 4 (B))

  Then, the thermal oxide film 404 is removed using buffer hydrofluoric acid. At this time, the high concentration nickel element existing in the film is removed at the same time.

  Thus, a crystalline silicon film 405 is formed over the quartz substrate 401 as shown in FIG. This crystalline silicon film 405 can be made highly crystalline by the action of nickel and the synergistic action of high heat treatment. (Fig. 4 (C))

  After obtaining the state shown in FIG. 4C, patterning is performed to form an active layer 406 of the thin film transistor. Further, a silicon oxide film functioning as the gate insulating film 407 is formed by a thermal oxidation method. The thickness of the gate insulating film is 500 mm. In this process, the thickness of the active layer is about 1000 mm.

  Further, the gate electrode 408 is made of molybdenum silicide or tungsten silicide. As a material constituting the gate electrode 408, various metal materials and semiconductor materials having one conductivity type can be used. (Fig. 4 (D))

  Next, a silicon oxide film 409 is formed as an interlayer insulating film to a thickness of 5000 mm by plasma CVD. Further, contact holes are formed, and a source electrode 410 and a drain electrode 411 are formed.

  Thus, a thin film transistor can be formed using a crystalline silicon film having high crystallinity on a quartz substrate. In the structure shown in this embodiment, an expensive quartz substrate must be used, but since a crystalline silicon film having very high crystallinity can be used, a thin film transistor having very high characteristics can be obtained. it can.

  In this embodiment, a metal element for selectively promoting crystallization of silicon is selectively introduced into a specific region of a microcrystalline silicon film used as a starting film, and crystal growth is performed in parallel with a direction parallel to the substrate from the heat treatment ( An example is shown in which a thin film transistor is manufactured using a region in which crystal growth is performed in a direction parallel to the substrate.

  First, a silicon oxide film 502 is formed as a base film on a glass substrate 501 (for example, Corning 1737 glass substrate or Corning 7059 glass substrate). Further, a microcrystalline silicon film 503 is formed by a method similar to that shown in Embodiment 1. The thickness of the silicon oxide film may be 3000 mm, and the thickness of the microcrystalline silicon film may be 500 mm.

  Further, a mask 504 is formed with a silicon oxide film. The silicon oxide film constituting the mask 504 has a thickness of 2000 mm and is formed by plasma CVD. This mask 504 has a structure in which the microcrystalline silicon film 503 is exposed at the opening indicated by 505. The opening indicated by 505 has a slit shape having a longitudinal direction in the depth direction of the drawing or the front side of the drawing.

  Next, a nickel acetate solution adjusted to a predetermined concentration is applied to form a water film 506. (Fig. 5 (A))

  Then, by removing an excess solution using a spinner (not shown), a state in which the nickel element is in contact with and held in contact with the microcrystalline silicon film 503 in the opening 505 is realized. (Fig. 5 (B))

The nickel concentration in the nickel acetate solution is such that the concentration of nickel element is 1 × 10 ¹⁵ atom cm ^{−3 to} 5 × 10 ¹⁹ atom cm ⁻³ , preferably 1 × 10 ¹⁵ atom cm, in a region to be used as an active layer later. ^{−3 to} 5 × 10 ¹⁸ atoms cm ⁻³ . The concentration of this nickel element is determined based on the minimum value measured by SIMS (secondary ion analysis method).

In order to determine a low concentration of 1 × 10 ¹⁵ atoms cm ⁻³ , the relationship between the nickel element concentration in the nickel acetate solution and the actually measured concentration value in the film may be used.

  Next, the microcrystalline silicon film is crystallized by heat treatment at 550 ° C. for 4 hours. In this heat treatment step, nickel element diffuses from the region of the opening 505, and crystal growth proceeds in a direction parallel to the substrate as indicated by an arrow 507. This crystal growth can be performed up to about 100 μm. (Fig. 5 (B))

  Next, the silicon oxide film 504 functioning as a mask is removed, and patterning is further performed, so that an island-shaped region 508 serving as an active layer of the thin film transistor is formed. Here, it is preferable that the start point and the end point of the previous crystal growth do not exist inside the island-shaped region 508. This is because nickel is contained at a high concentration at the start and end points of crystal growth.

  In the structure shown in this embodiment, since the crystal growth or crystallization promotion proceeds in a direction parallel to the substrate, it can be made less susceptible to the influence of crystal grain boundaries when the carrier moves in that direction. Therefore, a thin film transistor having high mobility can be manufactured.

  Next, an aluminum film (not shown) for forming a gate electrode is formed by sputtering to a thickness of 5000 mm. This aluminum film contains 0.2% by weight of scandium. This is to prevent generation of cracks and hillocks due to abnormal aluminum growth in the subsequent process.

  As an impurity element used for preventing the occurrence of cracks and hillocks due to the abnormal growth of aluminum, lanthanoids such as yttrium, gadolinium, and actinoid elements can be used.

  Next, an aluminum film (not shown) is patterned to form an island-shaped region that becomes the base of the gate electrode. A dense anodic oxide film (shown later by 510) is formed to a thickness of 100 mm on the surface. Then, a resist mask is disposed and patterning is performed to form a gate electrode. Further, a porous anodic oxide 512 is grown to a thickness of 4000 mm.

  In this way, the state shown in FIG. In the state shown in FIG. 5C, a porous anodic oxide 512 is formed on the side surface of the gate electrode 511, and a dense anodic oxide film 510 is formed on the upper surface thereof.

  Thereafter, the exposed silicon oxide film 509 is removed. Further, the dense anodic oxide film 510 and the porous anodic oxide film 512 are removed. Further, a silicon nitride film 500 is formed. This silicon nitride film is provided in order to prevent cracks and hillocks from being generated in the gate electrode due to abnormal growth of aluminum.

  In this way, the state shown in FIG. Here, impurity ions are implanted to form the source region 513, the low-concentration impurity region 514, the channel formation region 515, and the drain region 516 in a self-aligning manner. Further, laser light irradiation is performed to activate the region into which the impurity ions are implanted.

  Since the silicon nitride film 500 is formed at the time of the laser light irradiation, it is possible to prevent the gate electrode 511 made of aluminum from being cracked or hillocked.

  Thereafter, a silicon oxide film 517 functioning as an interlayer insulating film is formed to a thickness of 6000 mm by plasma CVD. Finally, contact holes are formed, and a source electrode 518 and a drain electrode 519 are formed.

  This example is an example in which Pd (palladium) is used as a metal element for promoting crystallization of silicon in Example 1 or another example. Here, a solution in which palladium is dissolved in buffer hydrofluoric acid is used. The concentration of palladium to be introduced may be the same as that of nickel.

This embodiment shows an example in which the thin film transistor manufactured in Embodiment 4 shown in FIG. 4 is used as a phototransistor. The thin film transistor illustrated in FIG. 4 has high crystallinity next to a single crystal, and its mobility is an N-channel type and high characteristics of 250 (cm ² / Vs) can be obtained.

  A quartz substrate is used as the substrate, and incident light (mainly light having a wavelength of 200 nm or more) from the substrate reaches the active layer. Therefore, the structure shown in this embodiment is characterized in that the thin film transistor functions as a thin film transistor having a function of detecting or amplifying incident light from the substrate side as shown in FIG.

  With the configuration shown in this embodiment, a photosensor or an optical amplifying device can be obtained. Further, by controlling the crystallinity of the active layer, it is possible to obtain characteristics having appropriate sensitivity in a required wavelength region.

  In order to adjust the crystallinity of the active layer, there are a method of adjusting the amount of metal element used in the crystallization promotion step, a method of changing the heating temperature in the crystallization promotion step, and a method of combining these methods. be able to.

  FIG. 7 shows a manufacturing process of this example. FIG. 7 shows an example of a thin film transistor configured in a complementary manner. First, a crystalline silicon film 703 is formed over a glass substrate 701 by the method described in Example 1 or Example 2. Here, in the case where a quartz substrate is used as the substrate 701, a crystalline silicon film may be formed according to the steps shown in Embodiment 4. Reference numeral 702 denotes an underlying silicon oxide film. (Fig. 7 (A))

  Next, the crystalline silicon film is patterned to form active layers 704 and 705. Then, a silicon oxide film 706 functioning as a gate insulating film is formed. Further, gate electrodes 709 and 710 made of aluminum and porous anodic oxides 711 and 712 around the gate electrodes are formed by the method shown in the third embodiment. Reference numerals 707 and 708 are dense anodic oxide films. (Fig. 7 (B))

  Next, the exposed gate insulating film 706 is removed. Thus, the gate insulating film remains in the regions indicated by 713 and 714. (Fig. 7 (C))

  Next, impurity ions of phosphorus and boron are implanted into each thin film transistor. Here, impurity ions are implanted in a state where each region is masked with a resist (not shown).

Thus, a source region 715 having N ⁺ type, a drain region 718, a low concentration impurity region 716 having N ⁻ type, and a channel formation region 717 are formed in a self-aligned manner. The reason why the regions are formed in a self-aligning manner is that the gate insulating film 713 remains.

Furthermore, a source region 719 having a P ⁺ type, a drain region 722, a low concentration impurity region 720 having a P ⁻ type, and a channel formation region 721 are formed in a self-aligned manner. (Fig. 7 (D))

Next, a silicon oxide film is formed as an interlayer insulating film 723 by a plasma CVD method. Then, contact holes are formed to form a source electrode 724, a common drain region 725, and a P-channel source region 726 of an N-channel thin film transistor. In this way, a thin film transistor having a complementary structure is completed.

10A and 10B illustrate a manufacturing process of a crystalline silicon film. 10A and 10B illustrate a manufacturing process of a crystalline silicon film. 10A and 10B illustrate a manufacturing process of a thin film transistor. 10A and 10B illustrate a manufacturing process of a thin film transistor. 10A and 10B illustrate a manufacturing process of a thin film transistor. An example in which a thin film transistor is used as an optical transistor will be described. 10A and 10B illustrate a manufacturing process of a thin film transistor.

Explanation of symbols

101 glass substrate 102 base film (silicon oxide film)
104 Microcrystalline silicon film 105 Water film of nickel acetate solution 106 Spinner 107 Film containing nickel element 108 Crystalline silicon film 201 Glass substrate 202 Base film (silicon oxide film)
203 Spinner 204 Water Film of Nickel Acetate Solution 205 Film Containing Nickel Element 206 Microcrystalline Silicon Film 207 Crystalline Silicon Film 301 Glass Substrate 302 Base Film (Silicon Oxide Film)
303 Crystalline silicon film 304 Active layer 305 Gate insulating film (silicon oxide film)
306 Gate electrode 307 Dense anodic oxide film 308 Porous anodic oxide film 309 Resist mask 310 Remaining gate insulating film (silicon oxide film)
311 Silicon nitride film 312 Source region 313, 315 Low concentration impurity region 314 Channel forming region 316 Drain region 318 Interlayer insulating film 319 Pixel electrode (ITO electrode)
320 Source electrode 321 Drain electrode 401 Quartz substrate 402 Base film (silicon oxide film)
403 Microcrystalline silicon film 404 Thermal oxide film 405 Crystalline silicon film 406 Active layer 407 Gate insulating film (thermal oxide film)
408 Gate electrode (metal silicide electrode)
409 Interlayer insulating film 410 Source electrode 411 Drain electrode 501 Glass substrate 502 Base film (silicon oxide film)
503 Microcrystalline silicon film 504 Mask made of silicon oxide film 505 Opening 506 Water film made of nickel acetic acid solution 507 Direction of crystal growth 508 Active layer 509 Gate insulating film 510 Dense anodic oxide film 511 Gate electrode 512 Porous anode Oxide film 513 Source region 514 Low concentration impurity region 515 Channel formation region 516 Drain region 517 Interlayer insulating film 518 Source electrode 519 Drain electrode

Claims (4)

Forming a microcrystalline silicon film over a substrate having an insulating surface;
Ni is held in contact with the surface of the microcrystalline silicon film,
A method for manufacturing a semiconductor device, wherein heat treatment is performed to form a crystalline silicon film having higher crystallinity than the microcrystalline silicon film. Form a base film on the glass substrate,
Forming a microcrystalline silicon film on the base film;
Ni is held in contact with the surface of the microcrystalline silicon film,
A method for manufacturing a semiconductor device, wherein heat treatment is performed to form a crystalline silicon film having higher crystallinity than the microcrystalline silicon film. Form a base film on the glass substrate,
Forming a microcrystalline silicon film on the entire surface of the base film;
Ni is held in contact with the surface of the microcrystalline silicon film,
A method for manufacturing a semiconductor device, comprising performing heat treatment to form a crystalline silicon film having higher crystallinity than the microcrystalline silicon film, and then patterning the crystalline silicon film.   4. The method for manufacturing a semiconductor device according to claim 1, wherein the microcrystalline silicon film is formed by a low pressure thermal CVD method or a plasma CVD method.

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