JP3901903B2 - Method for manufacturing thin film transistor - Google Patents

Description

[0001]
[Industrial application fields]
The invention disclosed in this specification relates to a technique for forming a crystalline silicon film over a substrate having an insulating surface.
[0002]
[Prior art]
In recent years, a technique for forming a thin film transistor using a silicon thin film formed on a glass substrate has attracted attention. This thin film transistor is mainly used in an active matrix type liquid crystal electro-optical device. The thin film transistor is used in various thin film integrated circuits.
[0003]
In the liquid crystal electro-optical device, liquid crystal is sealed between a pair of glass substrates, and an electric field is applied to the liquid crystal to change the optical characteristics of the liquid crystal and display an image.
[0004]
An active matrix liquid crystal display device using a thin film transistor is characterized in that a thin film transistor is disposed in each pixel and charges held in the pixel electrode are controlled using the thin film transistor as a switch. Active matrix liquid crystal display devices can display fine images at high speed, and are therefore used for displays of various electronic devices (for example, portable word processors, portable computers, and portable video cameras).
[0005]
As a thin film transistor used for an active matrix type liquid crystal display device, a thin film transistor using an amorphous silicon thin film (amorphous silicon thin film) is generally used. However, in a thin film transistor using an amorphous silicon thin film,
(1) The characteristics are low, and higher quality image display cannot be performed.
(2) A peripheral circuit for driving a thin film transistor arranged in a pixel cannot be configured.
There is a problem.
[0006]
The above problem (2) is that a thin film transistor using an amorphous silicon thin film cannot make a P-channel type thin film transistor practical, so that a CMOS circuit cannot be constructed, and a thin film transistor using an amorphous silicon thin film operates at high speed. In addition, since a large current cannot flow, it can be considered that the peripheral drive circuit cannot be assembled.
[0007]
As a method for solving the above problems, a technique of forming a thin film transistor using a crystalline silicon thin film can be mentioned. Examples of a method for obtaining a crystalline silicon thin film include a method in which heat treatment is performed on an amorphous silicon film and a method in which laser light is irradiated on an amorphous silicon film.
[0008]
However, at present, a crystalline thin film having excellent crystallinity has not been obtained.
[0009]
As a method for solving this problem, a configuration described in Japanese Patent Laid-Open No. 6-232069 is known. In this method, a crystalline silicon film is obtained under a heat treatment condition of 550 ° C. for 4 hours by utilizing a metal element that promotes crystallization of silicon, such as nickel.
[0010]
However, the technique described in the above publication is unsatisfactory in the crystallinity of the obtained crystalline silicon film. That is, the obtained crystalline silicon film has low crystallinity and a large amount of amorphous component remains. In addition, a phenomenon is observed in which the metal elements used are concentrated locally. Such a phenomenon causes a malfunction when a device is configured. This also reduces the production yield.
[0011]
[Problems to be solved by the invention]
An object of the invention disclosed in this specification is to provide a technique for obtaining a crystalline silicon film having high crystallinity over a substrate having an insulating surface.
[0012]
[Means for solving the problems]
One of the inventions disclosed in this specification is:
A step of contacting and holding a metal element that promotes crystallization of silicon on a silicon film formed on a quartz substrate;
Performing a heat treatment at a temperature of 800 ° C. to 1100 ° C. to transform the silicon film into a crystalline silicon film or promoting the crystallinity of the silicon film;
It is characterized by having.
[0013]
Other aspects of the invention are:
Applying a solution containing a metal element that promotes crystallization of silicon onto a silicon film formed on a quartz substrate;
Performing a heat treatment at a temperature of 800 ° C. to 1100 ° C. to transform the silicon film into a crystalline silicon film or promoting the crystallinity of the silicon film;
It is characterized by having.
[0014]
Other aspects of the invention are:
A step of contacting and holding a metal element that promotes crystallization of silicon on an amorphous silicon film formed on a quartz substrate;
Performing a heat treatment at a temperature higher than the crystallization temperature of the amorphous silicon film by 200 ° C. or more to transform the amorphous silicon film into a crystalline silicon film;
It is characterized by having.
[0015]
Other aspects of the invention are:
Patterning an amorphous silicon film formed on a quartz substrate to form an island-shaped region having a diameter of 200 μm or less;
A step of contacting and holding a metal element that promotes crystallization of silicon on the surface of the island-shaped region;
Performing a heat treatment at a temperature of 800 ° C. to 1100 ° C. to crystallize the island-shaped region;
It is characterized by having.
[0016]
As the substrate, a semiconductor substrate typified by a single crystal silicon wafer can be used instead of the quartz substrate. However, when a semiconductor substrate is used, there are a problem that light transmittance cannot be secured and an insulating film needs to be formed on the surface of the semiconductor substrate.
[0017]
In the invention disclosed in this specification, a substrate in which a single layer film selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film or a multilayer film thereof is formed over a quartz substrate is also referred to as a substrate. In general, it is preferable to form a base film such as a silicon oxide film in order to relieve stress acting between the quartz substrate and the semiconductor film.
[0018]
The invention disclosed in this specification is a technique in which an insulating film is formed on an integrated circuit (generally referred to as an IC circuit) using a silicon wafer, and a thin film transistor is formed thereon using the insulating film as a base film. It can be applied to. That is, a silicon wafer (or a single crystal silicon silicon substrate) on which an integrated circuit required as a substrate is formed can be used as the substrate.
[0019]
As the silicon film, an amorphous silicon film or a microcrystalline silicon film can be used. In particular, it is effective to use an amorphous silicon film in which the hydrogen content is reduced as much as possible. Further, in order to artificially reduce hydrogen in the amorphous silicon film, the amorphous silicon film is subjected to a heat treatment at a temperature of 300 to 500 ° C. for about 30 minutes to 2 hours, so that the hydrogen from the film is removed. It is very effective to promote the withdrawal. The heat treatment for crystallization may be performed after the heat treatment for removing hydrogen.
[0020]
As the metal element for promoting the crystallization of silicon, one or more kinds of elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au can be used.
[0021]
Among the above metal elements, Ni (nickel) is particularly preferable because of its large effect and high reproducibility.
[0022]
In the invention disclosed in this specification, a temperature of 800 ° C. to 1100 ° C. is preferably used as the temperature of the heat treatment for crystallizing the silicon film or promoting its crystallinity. In the case where an amorphous silicon film is used as the starting film, the temperature of this heat treatment is preferably set to 200 ° C. or more of the crystallization temperature of the amorphous silicon film that is the starting film.
[0023]
The crystallization temperature of the amorphous silicon film varies depending on the silicon film formation method and conditions. Note that since the crystallization occurs at a low temperature if the heating time is extended, there is no clear boundary between the temperatures at which the crystallization starts. For example, an amorphous silicon film that is finally crystallized by heating at 600 ° C. for 24 hours can be transformed into a completely crystalline silicon film by performing a heat treatment at 590 ° C. for 96 hours.
[0024]
Therefore, in this specification, the temperature at which the whole crystallizes in the heat treatment for 12 hours is defined as the crystallization temperature. The term “total crystallization” as used herein means that 80% or more of the whole has been transformed into a crystal component. In addition, as a state in which the entirety is crystallized, a state in which the spectrum of the amorphous component is hardly observed and the spectrum of the crystal component becomes remarkable by measurement by Raman spectroscopy can be cited.
[0025]
In general, the crystallization temperature of the amorphous silicon film is 580 ° C. to 620 ° C., although it depends on the film forming method and the film forming conditions.
[0026]
In the invention disclosed in this specification, as a method for holding a metal element that promotes crystallization of silicon in contact with the amorphous silicon film, a solution containing the metal element is applied to the surface of the amorphous silicon film. The method to do is the best.
[0027]
When this method is used, the concentration of the metal element in the silicon film can be finally adjusted by adjusting the concentration of the metal element in the solution. The concentration of the metal element present in the silicon film is 1 × 10 ¹⁵ ~ 5x10 ¹⁹ Atom cm ^-3 , Preferably 1 × 10 ¹⁶ ~ 5x10 ¹⁷ Atom cm ^-3 It is necessary to make the concentration to the extent. For this purpose, the method using the above solution is very useful. In addition, the density | concentration of a metal element is defined as the minimum value measured by SIMS (secondary ion analysis method).
[0028]
Further, it has been found that when a method using this solution is used, a metal element can be uniformly contacted and held on the surface of the amorphous silicon film. This means that the metal element layer or the layer containing the metal element can be present in contact with the amorphous silicon film uniformly. This is very important in terms of preventing local concentration of metal elements.
[0029]
When using nickel as the metal element, nickel bromide, nickel acetate, nickel oxalate, nickel carbonate, nickel chloride, nickel iodide, nickel nitrate, nickel sulfate, nickel formate, nickel acetylacetonate, A solution mainly containing at least one selected from nickel 4-cyclohexylbutyrate, nickel oxide, nickel hydroxide, and nickel 2-ethylhexanoate can be used.
[0030]
Further, nickel containing nonpolar solvents such as benzene, toluene, xylene, carbon tetrachloride, chloroform, ether, trichloroethylene, and chlorofluorocarbon can also be used.
[0031]
When Fe (iron) is used as the metal element, a material known as an iron salt, for example, ferrous bromide (FeBr) ₂ 6H ₂ O), ferric bromide (FeBr) _Three 6H ₂ O), ferric acetate (Fe (C ₂ H _Three O ₂ ) _Three xH ₂ O), ferrous chloride (FeCl ₂ 4H ₂ O), ferric chloride (FeCl _Three 6H ₂ O), ferric fluoride (FeF) _Three 3H ₂ O), ferric nitrate (Fe (NO _Three ) _Three 9H ₂ O), ferrous phosphate (Fe _Three (PO _Four ) ₂ 8H ₂ O), ferric phosphate (FePO _Four 2H ₂ At least one selected from O) can be used as the main component.
[0032]
When Co (cobalt) is used as the metal element, a material known as a cobalt salt as the compound, such as cobalt bromide (CoBr6H) ₂ O), cobalt acetate (Co (C ₂ H _Three O ₂ ) ₂ 4H ₂ O), cobalt chloride (CoCl ₂ 6H ₂ O), cobalt fluoride (CoF) ₂ xH ₂ O), cobalt nitrate (Co (No _Three ) ₂ 6H ₂ Those selected from O) can be used as the main component.
[0033]
When Ru (ruthenium) is used as the metal element, the compound is known as a ruthenium salt, such as ruthenium chloride (RuCl). _Three H ₂ O) can be used.
[0034]
When Rh (rhodium) is used as the metal element, the compound is known as a rhodium salt, such as rhodium chloride (RhCl). _Three 3H ₂ O) can be used.
[0035]
When Pd (palladium) is used as the metal element, a material known as a palladium salt as the compound, for example, palladium chloride (PdCl ₂ 2H ₂ O) can be used.
[0036]
When Os (osnium) is used as the metal element, the compound is known as an osnium salt, such as osmium chloride (OsCl). _Three ) Can be used.
[0037]
When Ir (iridium) is used as the metal element, a material known as an iridium salt as the compound, for example, iridium trichloride (IrCl _Three 3H ₂ O), iridium tetrachloride (IrCl _Four A material mainly composed of a material selected from (1) can be used.
[0038]
When Pt (platinum) is used as the metal element, a material known as a platinum salt as the compound, such as platinous chloride (PtCl _Four 5H ₂ O) can be used.
[0039]
When Cu (copper) is used as the metal element, cupric acetate (Cu (CH _Three COO) ₂ ), Cupric chloride (CuCl ₂ 2H ₂ O), cupric nitrate (Cu (NO _Three ) ₂ 3H ₂ Materials selected from O) can be used.
[0040]
When gold is used as the metal element, the compound is gold trichloride (AuCl _Three xH ₂ O), gold chloride (AuHCl) _Four 4H ₂ Materials selected from O) can be used.
[0041]
In order to adjust the concentration of these metal elements, it is effective to dilute the above materials with an appropriate solvent. It is also effective to include a surfactant in the above solution. Use of a surfactant can enhance the effect of dispersing and presenting a metal element on the surface of the amorphous silicon film.
[0042]
[Action]
Crystalline silicon having high crystallinity in a short heat treatment by using a metal element for promoting crystallization of silicon and further performing a heat treatment for obtaining a crystalline silicon film at a high temperature of 800 ° C. to 1100 ° C. A membrane can be obtained. Further, by performing the heat treatment at such a high temperature, it is possible to prevent the metal elements from being concentrated locally in the silicon film.
[0043]
【Example】
[Example 1]
FIG. 1 shows a manufacturing process of this embodiment. In this embodiment, a crystalline silicon film is formed on a quartz substrate. First, a silicon oxide film 102 having a thickness of 3000 mm is formed on a quartz substrate 101 as a base film. This silicon oxide film 102 is formed in order to prevent impurities from diffusing from the quartz substrate into the silicon film later. Next, an amorphous silicon film 103 is formed to a thickness of 500 mm by low pressure thermal CVD. (Fig. 1 (A))
[0044]
Next, a nickel acetate solution adjusted to a predetermined concentration is applied to the surface of the amorphous silicon film. Then, a water film 105 of a nickel acetate solution is formed. (Fig. 1 (B))
[0045]
Thereafter, spin coating is performed using the spinner 104. At the same time, the excess nickel acetate solution is blown off. In this way, the nickel element is held in contact with the surface of the amorphous silicon film 103. The concentration of nickel element in the nickel acetate solution is such that the concentration of nickel element finally present in the silicon film is 1 × 10. ¹⁵ ~ 5x10 ¹⁹ Atom cm ^-3 It needs to be as follows.
[0046]
In this way, the state shown in FIG. In this state, the surface of the amorphous silicon film 103 is held in contact with the nickel element. And the heat processing for 4 hours are performed at the temperature of 950 degreeC. After completion of the heat treatment, it is gradually cooled to a temperature of 700 ° C. at a cooling rate of 0.5 ° C./min. The slow cooling is performed here in order to suppress the stress from remaining in the silicon film.
[0047]
By performing this heat treatment, the amorphous silicon film 103 can be transformed into the crystalline silicon film 106. (Figure 1 (D))
[0048]
It is important that the heat treatment temperature performed here is much higher than the crystallization temperature of the amorphous silicon film 103. By setting such a high temperature, a crystalline silicon film can be obtained in a short time of about 4 hours, and the crystallinity can be made extremely high. In addition, the nickel element that contributes to the promotion of crystallization can be dispersed in the film, and local high-density trap levels can be prevented from being formed. According to the experiment, it has been found that the crystallization temperature of the amorphous silicon film shown in this embodiment is about 590 degrees.
[0049]
By applying heat treatment at such a high temperature, a crystalline silicon film having very high crystallinity can be obtained. In general, a technique for crystallizing an amorphous silicon film formed on a quartz substrate by heating at about 900 ° C. is known. The crystalline silicon film 106 obtained in this embodiment has higher crystallinity than the crystalline silicon film obtained by the technique using the known quartz substrate. This is an effect of using a metal element that promotes crystallization of silicon.
[0050]
[Example 2]
This example is an example in the case of using a copper element instead of a nickel element in the process shown in Example 1. Here, cupric acetate (Cu (CH _Three COO) ₂ ) To keep the nickel element in contact with the surface of the amorphous silicon film. The same heat treatment as in Example 1 is performed to obtain a crystalline silicon film. In addition, what is necessary is just to make the density | concentration of the copper element in a solution the same thing as the case of the nickel element of Example 1.
[0051]
Example 3
In this embodiment, an example of manufacturing an N-channel thin film transistor using the invention disclosed in this specification will be described. First, according to the process shown in Example 1, a crystalline silicon film is formed on a glass substrate. Then, the crystalline silicon film is patterned to obtain a state as shown in FIG.
[0052]
In the state shown in FIG. 2A, a silicon oxide film having a thickness of 3000 mm is formed as a base film 202 on a quartz substrate 201, and an island made of a crystalline silicon film constituting an active layer of a thin film transistor. A semiconductor layer 203 is formed.
[0053]
When the state shown in FIG. 2A is obtained, a silicon oxide film 204 constituting a gate insulating film is formed to a thickness of 1000 mm. As a film forming method, a plasma CVD method may be used. Then, an N-type microcrystalline silicon film containing P (phosphorus) is formed by a low pressure thermal CVD method. Then, the gate electrode 205 is formed by patterning the N-type microcrystalline silicon film. In this way, the state shown in FIG.
[0054]
Here, the gate electrode 205 is formed using silicon, but a metal material having high heat resistance or a silicide thereof may be used. A multilayer structure of metal and semiconductor may be employed.
[0055]
Next, in order to form a source region and a drain region in the active layer, P (phosphorus) ions are implanted as shown in FIG. Here, P ions are implanted. However, if a P channel thin film transistor is obtained, B (boron) ions may be implanted.
[0056]
Here, P ions are implanted by a plasma doping method. In this step, P ions are implanted into the regions 206 and 208 using the gate electrode as a mask. Further, the channel formation region 207 is formed in a self-aligned manner. Thereafter, heat treatment is performed at 950 ° C. for 2 hours in order to crystallize the regions 206 and 208 that have become amorphous by the impact of the implanted ions and to activate the implanted P ions.
[0057]
Laser light irradiation may be performed instead of this heat treatment. Moreover, you may perform irradiation of a laser beam, heating at the temperature of 800-110 degreeC. Further, strong light (for example, infrared light) may be irradiated instead of laser light irradiation.
[0058]
Next, as shown in FIG. 2D, a silicon oxide film 209 is formed as an interlayer insulating film by a plasma CVD method. Then, contact holes are formed, and the source electrode 210 and the drain electrode 211 are formed. This electrode is made of titanium. Thus, an N-channel thin film transistor is completed.
[0059]
The thin film transistor manufactured in this embodiment has large mobility and small OFF current characteristics as compared with a thin film transistor using a crystalline silicon film formed on a glass substrate at a temperature of about 600 ° C.
[0060]
The reason why the mobility is large is that the carrier mobility is increased by obtaining high crystallinity. Further, the small OFF current characteristics can be obtained because the number of carriers moving through the trap level is reduced due to the decrease in the trap level density.
[0061]
The OFF current in the thin film transistor refers to a current that flows between the source / drain during the OFF operation of the thin film transistor (a state in which a reverse bias is applied to the gate electrode).
[0062]
The cause of the flow of the OFF current is that carriers move through the trap level in the vicinity of the interface between the channel formation region and the drain region, as described in Japanese Patent Publication No. 3-38755. to cause. Therefore, the OFF current value can be reduced by increasing the crystallinity of the crystalline silicon film constituting the active layer and decreasing the trap level density.
[0063]
[Comparative Example]
In the manufacturing process of the comparative example shown here, a crystalline silicon film is obtained by performing a heat treatment for crystallization at a temperature of 550 ° C. using a glass substrate as the substrate in the process shown in Example 1. In this example, a thin film transistor is manufactured using a crystalline silicon film.
[0064]
A manufacturing process of this comparative example will be described with reference to FIGS. Here, a glass substrate is used as the substrate 101. First, a silicon oxide film 102 is formed on the glass substrate 101 as a base film to a thickness of 3000 mm. Further, an amorphous silicon film 103 is formed to a thickness of 500 mm by a low pressure thermal CVD method. In this way, the state shown in FIG.
[0065]
Next, the nickel acetate salt solution is applied under the same conditions as in Example 1, and spin coating is performed using the spinner 104. (Fig. 1 (B))
[0066]
In this way, the state shown in FIG. In this state, the nickel element is held in contact with the surface of the amorphous silicon film 103.
[0067]
In the state shown in FIG. 1C, heat treatment is performed at 550 ° C. for 4 hours. In this step, the crystalline silicon film 106 can be obtained by the action of nickel element. (Figure 1 (D))
[0068]
Next, an active layer of the thin film transistor is formed by patterning the crystalline silicon film. This state is shown in FIG. In the state shown in FIG. 2A, 201 is a glass substrate, 202 is a silicon oxide film as a base film, and 203 is an active layer of a thin film transistor.
[0069]
Next, an N-type microcrystalline silicon film constituting the gate insulating film is formed and patterned to form the gate electrode 205. In this way, the state shown in FIG.
[0070]
Next, P (phosphorus) ions are implanted by a plasma doping method to form a source region 206, a drain region 208, and a channel formation region 207 in a self-aligning manner. Further, the source region and the drain region are recrystallized and activated by laser irradiation. (Fig. 2 (C))
[0071]
Further, an interlayer insulating film 209 is formed by a plasma CVD method, and after forming contact holes, a source electrode 210 and a drain electrode 211 are formed to complete a thin film transistor.
[0072]
The mobility of the thin film transistor of this comparative example is about 60 to 70% of that of the thin film transistor shown in Example 1. However, the OFF current characteristics are not so bad as to cause a problem with respect to the thin film transistor shown in the first embodiment. In order to improve this OFF current characteristic, a special structure such as an offset gate structure or an LDD structure is required.
[0073]
In addition, the thin film transistor shown in this comparative example has a problem that the variation in characteristics of each element is remarkably large. The cause is considered to be as follows. When the active layer of the thin film transistor shown in this example is observed with a TEM (transmission electron microscope), it is confirmed that nickel elements are concentrated. As is well known, if metal elements are locally concentrated in a semiconductor, a high-density trap level is formed there. The existence of such high-density trap levels causes device degradation and operational instability. For these reasons, the thin film transistor shown in this example has large variations in the characteristics between elements.
[0074]
On the other hand, the thin film transistor manufactured by the process shown in Embodiment 1 has a feature that variation among elements is very small. Further, when the active layer of the thin film transistor manufactured in the process shown in Example 1 is observed with a TEM (transmission electron microscope), there is almost no local concentration of nickel element. This confirms that the variation from element to element is small. It is considered that the local concentration of the nickel element is hardly observed because the nickel element is dispersed in the silicon film by heating as high as 950 ° C.
[0075]
Example 4
This embodiment relates to a structure in which the crystalline silicon film 106 shown in FIG. 1D is obtained by the steps shown in Embodiment 1, and further laser light irradiation is performed to increase the crystallinity. The crystalline silicon film 107 in the state shown in FIG. 1D contains an amorphous component, albeit slightly.
[0076]
This amorphous component can be eliminated by further heat treatment. That is, the crystallinity can be further improved by further heat treatment. However, this heat treatment requires several hours, and is not a preferable means in consideration of productivity.
[0077]
Therefore, in this embodiment, after obtaining the state shown in FIG. 1D in the step shown in Embodiment 1, laser light irradiation is further performed to increase the crystallinity.
[0078]
As the laser light to be irradiated, excimer laser light having a wavelength in the ultraviolet region is preferably used. Here, a KrF excimer laser with a wavelength of 248 nm is used. The irradiation energy density is 300 to 400 mJ / cm. ² And
[0079]
As shown in this embodiment, the crystallinity can be enhanced by irradiating a crystalline silicon film which is once crystallized by heating with laser light. The effect can be obtained with high reproducibility.
[0080]
Although an example using laser light is shown here, strong light such as infrared light may be irradiated.
[0081]
Example 5
This embodiment relates to an active matrix liquid crystal display device having a structure in which peripheral circuits are integrated on a single quartz substrate. Hereinafter, a manufacturing process for obtaining the active matrix circuit of this embodiment will be described with reference to FIGS.
[0082]
In the drawing, a manufacturing process of a thin film transistor (denoted as a peripheral circuit TFT) of a peripheral logic circuit is shown on the left side, and a manufacturing process of a thin film transistor (denoted as a pixel TFT) of an active matrix circuit is shown on the right side.
[0083]
First, a silicon oxide film having a thickness of 1000 to 3000 mm is formed as a base oxide film 302 on a quartz substrate 301. As a method for forming this silicon oxide film, a sputtering method or a plasma CVD method in an oxygen atmosphere may be used.
[0084]
Thereafter, an amorphous silicon film is formed to a thickness of 500 mm by plasma CVD or low pressure thermal CVD. Further, nickel, which is a metal element for promoting crystallization of silicon, is held in contact with the surface of the amorphous silicon film by a method similar to the method shown in the first embodiment.
[0085]
Next, the amorphous silicon film is transformed into a crystalline silicon film by performing a heat treatment at 900 ° C. for 4 hours. After this heat treatment, crystallinity may be further enhanced by laser light irradiation or strong light irradiation.
[0086]
Next, the obtained crystalline silicon film is etched, and active layers 303 (for P-channel TFTs) and 304 (for N-channel TFTs) of thin film transistors (indicated as peripheral circuit TFTs in the figure) of island-shaped peripheral drive circuits And an active layer 305 of a thin film transistor (denoted as a pixel TFT in the figure) of a matrix circuit.
[0087]
Further, a gate insulating film 306 made of a silicon oxide film having a thickness of 500 to 2000 mm is formed by sputtering in an oxygen atmosphere. As a method for forming the gate insulating film, a plasma CVD method may be used. In the case of forming a silicon oxide film by a plasma CVD method, dinitrogen monoxide (N ₂ O) or oxygen (O ₂ ) And Monsilane (SiH) _Four ) Is preferably used.
[0088]
Thereafter, a polycrystalline silicon film (containing P (phosphorus) for increasing conductivity) having a thickness of 2000 to 5 μm, preferably 2000 to 6000 mm, is formed on the entire surface of the substrate by a low pressure CVD method. Then, this is etched to form gate electrodes 307, 308, and 309. (Fig. 3 (A))
[0089]
Thereafter, phosphine (PH) is formed on all island-like active layers by ion doping in a self-aligning manner using the gate electrode as a mask. _Three ) Is doped as a doping gas. The dose is 1 × 10 ¹² ~ 5x10 ¹³ Atom / cm ² And As a result, weak N-type regions 310, 311 and 312 are formed. (Fig. 3 (B))
[0090]
Next, a photoresist mask 313 is formed to cover the active layer 303 of the P-channel thin film transistor. At the same time, a photoresist mask 314 is formed covering the active layer 305 of the pixel thin film transistor so as to be parallel to the gate electrode and to a portion 3 μm away from the end of the gate electrode 309.
[0091]
Then, again by ion doping, P (phosphorus) ions are implanted using phosphine as a doping gas. At this time, P (phosphorus) ions are not implanted under the resist masks 313 and 314.
[0092]
As a result, strong N-type regions (source / drain) 315 and 316 are formed. In this step, among the weak N-type region 312 of the active layer 305 of the pixel thin film transistor, the region 317 (see FIG. 3D) covered with the mask 314 is not injected with P (phosphorus) and is weak N-type. Will remain. (Figure 3 (C))
[0093]
Next, the active layers 304 and 305 of the N-channel thin film transistor are covered with a photoresist mask 318, and diborane (B ₂ H ₆ ) As a doping gas, B (boron) is implanted into the island-like region 103 by ion doping. Dose amount is 5 × 10 ¹⁴ ~ 8x10 ¹⁵ Atom / cm ² And In this doping, since the dose amount of B exceeds the dose amount of P in FIG. 3C, the weak N-type region 310 formed previously is inverted to the strong P-type region 319.
[0094]
By the above doping, strong N-type regions (source / drain) 315 and 316, strong P-type regions (source / drain) 319, and weak N-type regions (low-concentration impurity regions) 317 are formed. In this embodiment, the width x of the low concentration impurity region 317 is about 3 μm from the size of the photoresist mask 114. The drain region side of the low concentration impurity region 317 functions as an LDD region. (Fig. 3 (D))
[0095]
Then, the damage by doping is recovered by performing a heat treatment at a temperature of 900 ° C. for 2 hours. At the same time, the doping impurities are activated. Thereafter, a silicon oxide film having a thickness of 5000 mm is formed as an interlayer insulator 320 over the entire surface by plasma CVD. This may be a silicon nitride film or a multilayer film of a silicon oxide film and a silicon nitride film. Then, the interlayer insulator 320 is etched by a wet etching method to form contact holes in the source / drain.
[0096]
Then, a titanium film having a thickness of 4000 mm is formed by sputtering, and this is etched to form electrodes / wirings 321, 322, and 323 for peripheral circuits. At the same time, electrodes / wirings 324 and 325 of the pixel thin film transistor are formed. Further, a silicon nitride film 326 having a thickness of 2000 mm is formed as a passivation film by plasma CVD. Then, this is etched to form a contact hole reaching the electrode 325 of the pixel thin film transistor. Finally, an ITO (indium tin oxide) film having a thickness of 1500 mm formed by sputtering is etched to form a pixel electrode 327. In this way, the peripheral circuit and the active matrix circuit can be formed integrally. (Figure 3 (E))
[0097]
Example 6
This embodiment is characterized in that a microcrystalline silicon film is used instead of the amorphous silicon film 103 in the step shown in Embodiment 1. In order to form a microcrystalline silicon film, a low pressure thermal CVD method using disilane as a source gas may be used. In the case of this embodiment, the amorphous silicon film is not transformed into the crystalline silicon film by the heat treatment, but the crystallinity of the microcrystalline silicon film is promoted by the heat treatment, and the crystalline silicon film having higher crystallinity is further obtained. Will get.
[0098]
Example 7
The present embodiment relates to a highly practical N-channel type thin film transistor that realizes a low OFF current characteristic by providing an offset gate region. FIG. 4 shows a schematic manufacturing process of the thin film transistor of this example.
[0099]
First, a silicon oxide film 402 is formed as a base film on a quartz glass substrate 401 to a thickness of 5000 mm. This silicon oxide film has a function of relieving stress acting between the quartz substrate and the silicon film formed thereon. The thickness is preferably at least 3000 mm.
[0100]
Then, an amorphous silicon film to be a starting film of a silicon film that will later constitute an active layer of the thin film transistor is formed on the silicon oxide film 402 by a low pressure CVD method. Here, disilane is used as a film forming gas, and a film having a thickness of 1000 mm is formed. In this example, V of the obtained thin film transistor _th In order to control the value of diborane, a small amount of diborane is contained in disilane. (Fig. 4 (A))
[0101]
After the amorphous silicon film 403 is formed, a nickel acetate solution is applied by spin coating. In this step, a state in which the nickel element is held in contact with the surface of the amorphous silicon film 403 is realized.
[0102]
Then, a heat treatment is performed at 800 ° C. for 4 hours to crystallize the amorphous silicon film 403. After the heat treatment, the stress in the silicon film is relaxed at a temperature of 2 ° C./min or less.
[0103]
A method of performing this heat treatment at a higher temperature is effective, but it is preferable to perform the heat treatment at about 800 to 900 ° C. in consideration of the slow cooling time and the burden on the apparatus.
[0104]
Next, patterning is performed to form an active layer 404 of the thin film transistor. (Fig. 4 (B))
[0105]
Further, a 500-nm silicon oxide film 406 is formed by thermal oxidation. At this time, the heating temperature is 950 ° C. By forming the silicon oxide film 406 to a thickness of 500 mm by the thermal oxidation method, the thickness of the active layer 404 becomes about 750 mm. (Fig. 4 (C))
[0106]
Next, molybdenum silicide for forming the gate electrode is formed to a thickness of 5000 mm. It is preferable to use a material having a low resistance as much as possible as a material for constituting this electrode. For example, tungsten silicide can be used in addition to molybdenum silicide.
[0107]
Then, a resist mask 408 is disposed, and this 5000-thick film made of molybdenum silicide is patterned. Thus, a region 407 to be a gate electrode is formed. (Fig. 4 (D))
[0108]
Next, an etching process is performed using an isotropic etching method capable of selectively etching molybdenum silicide. In this etching process, etching as indicated by an arrow in FIG. 4E progresses, and the size of the region 407 to be a gate electrode made of molybdenum silicide is reduced. Here, the width to be etched is 5000 mm. Thus, the gate electrode 409 is formed. (Fig. 4 (E))
[0109]
In this state, as shown in FIG. 5A, P (phosphorus) ions are implanted by plasma doping. As a result of this doping, P ions are implanted into the regions 410 and 413. The regions 410 and 413 become a source region and a drain region. A region of the active layer immediately below the gate electrode 409 becomes a channel formation region 412. The region 411 where P ions are not implanted becomes the offset gate region. The width of the offset gate region 411 is 5000 mm. (Fig. 5 (A))
[0110]
After the completion of the P ion implantation shown in FIG. 5A, heat treatment is performed at 800 ° C. for 2 hours. In this step, annealing of damage caused by activation of the source / drain regions and ion implantation is performed.
[0111]
Next, a silicon oxide film 414 is formed as an interlayer insulating film to a thickness of 6000 mm by plasma CVD. Then, after the contact hole is formed, a layer composed of a titanium film and an aluminum film is formed. Then, the source electrode 415 and the gate electrode 416 are formed by patterning this. This aluminum contains 0.2 wt% of scandissum to prevent the generation of hillocks. Further, although not shown, an electrode that contacts the gate electrode 409 is formed. Further, hydrogen heat treatment is performed in a hydrogen atmosphere at 400 ° C. to neutralize dangling bonds in the active layer, thereby completing the thin film transistor. In this manner, the thin film transistor shown in FIG. 5B is completed.
[0112]
FIG. 6B shows an example of characteristics of the thin film transistor whose outline is shown in FIG. (Characteristics vary widely)
[0113]
The thin film transistor whose characteristics are shown in FIG. 6 has a mobility of 247.57 cm. ² / Vs, V _th Is 0.11 V, and the S value is 0.09 V / Dec. The variation in characteristics of the obtained thin film transistor is that the mobility is 180 to 250 cm. ² The S value is in the range of about 0.09 to 0.12 V / Dec.
[0114]
A thin film transistor having such characteristics can operate at a high speed of several tens of MHz. Therefore, if the variation is suppressed, an integrated circuit that can handle image signals can be formed on the quartz substrate.
[0115]
FIG. 7 shows a summary of a manufacturing method and characteristics that are characteristic of a thin film transistor manufactured for comparison.
[0116]
Comparative Example 1 and Comparative Example 2 shown in FIG. 7 are basically manufactured according to the manufacturing steps shown in FIGS.
[0117]
Comparative Example 1 is characterized in that a crystalline silicon film is obtained without using a metal element that promotes crystallization of silicon. The comparative example 1 corresponds to a thin film transistor called a general high-temperature polysilicon TFT. Therefore, by comparing this example with Comparative Example 1, it is possible to confirm the effect of using the metal element.
[0118]
Although Comparative Example 2 uses a metal element that promotes crystallization of silicon, heat treatment for crystallization of the amorphous silicon film 403 performed in the step shown in FIG. It is characterized by being performed under conditions. Therefore, by comparing this example with Comparative Example 2, it is possible to confirm the influence on the characteristics of the thin film transistor due to the difference in the temperature of heating for crystallization of the amorphous silicon film.
[0119]
In Comparative Example 2, the activation of the source / drain regions is performed not by heating but by laser light irradiation.
[0120]
As is apparent from FIG. 7, by employing the manufacturing process of this example, when the nickel of Comparative Example 1 is not used, the nickel shown in Comparative Example 2 is used, but heating for crystallization is performed. It can be seen that a thin film transistor having significantly significant characteristics can be obtained as compared with the case where the temperature is lowered to 550 ° C.
[0121]
Note that the thin film transistors as shown in Comparative Example 1 and Comparative Example 2 can be operated only in the range of several MHz. That is, it can be operated only at a speed about 1/10 of the thin film transistor shown in this embodiment.
[0122]
Example 8
In this embodiment, a part of the manufacturing process of the thin film transistor shown in FIG. 4 is devised. As shown in FIG. 4A, when crystallization using nickel is performed after forming an amorphous silicon film 403, crystallinity in which a large number of crystal grains having an apparent grain size of several hundred μm are formed. A silicon film is obtained.
[0123]
When this crystalline silicon film is used, a thin film transistor having remarkably high characteristics can be obtained as shown in Example 7. However, when a large number of thin film transistors are formed using a crystalline silicon film formed on a quartz substrate, a situation in which crystal grain boundaries are located in the active layer at a certain rate is realized.
[0124]
Metal elements and impurities that contribute to the promotion of crystallization are precipitated at the grain boundaries. Such existence becomes a factor that inhibits the movement of the carry. Therefore, when a crystal grain boundary exists in the channel formation region of the active layer, the characteristics of the obtained thin film transistor are low. This leads to variations in characteristics of the thin film transistor obtained.
[0125]
In order to solve such a problem, it is sufficient that no crystal grain boundary exists in the active layer. The size of the active layer is as small as about 10 μm square and as large as about 100 μm square. As described above, the size of the crystal grains obtained is several hundreds μm (according to the experiment, those having a size of about 300 μm can be obtained).
[0126]
Therefore, in the configuration shown in this embodiment, an amorphous silicon film is patterned to obtain an active layer made of an amorphous silicon film, and then crystallization using nickel element is performed. That is, after obtaining the state shown in FIG. 4B, nickel element is introduced, and then heat treatment is performed at 800 ° C. for 4 hours to crystallize the amorphous silicon film having the shape of the active layer.
[0127]
As described above, the size of the active layer is as large as about 100 μm. Therefore, the island-shaped amorphous silicon film patterned to such a size becomes almost one crystal grain.
[0128]
By adopting such a configuration, it is possible to suppress the presence of crystal grain boundaries in the active layer. And the variation in the characteristic of the thin-film transistor obtained can be suppressed. That is, the mobility as shown in Example 7 is 250 cm. ² A thin film transistor having a remarkably high characteristic that can be obtained near / Vs and has an S value of less than 0.1 V / Dec can be obtained while suppressing variation in characteristics.
[0129]
Example 9
The present embodiment relates to a configuration that suppresses the influence of a metal element that promotes crystallization of silicon in the configuration shown in the eighth embodiment. When the amorphous silicon film as a starting film is panned to the shape of the active layer as shown in Example 8 and then an active layer having a crystalline state is obtained by heat treatment using nickel, the following problems are caused: Occurs.
[0130]
That is, when crystallization is performed after forming a pattern (active layer pattern) made of an amorphous silicon film, metal elements contributing to crystallization are unevenly distributed in the periphery of the active layer pattern, that is, at the edge of the pattern. End up. This uneven distribution of the metal element causes a trap level to be formed on the side surface or edge portion of the active layer. There is a concern that such a state may adversely affect the operation of the thin film transistor.
[0131]
The present embodiment provides a technique for obtaining an active layer that does not have a region in which metal elements are unevenly distributed as described above. FIG. 8 shows a manufacturing process of the active layer shown in this embodiment.
[0132]
In FIG. 8A, reference numeral 801 denotes a specific region of the amorphous silicon film formed on the quartz substrate through the underlying silicon oxide film. First, three rectangular patterns indicated by 802 to 804 are formed in this region. That is, three island-like regions indicated by 802 to 804 made of an amorphous silicon film are formed.
[0133]
The size of this pattern is 10 μm square to 200 μm square, preferably 20 μm square to 100 μm square. That is, the area is about 70% or less of the area of the obtained crystal grain. The shape may be square, rectangular, polygonal, circular or elliptical. That is, any shape that can be easily used may be used. However, a complicated shape is not preferable because it inhibits the progress of crystallization.
[0134]
Further, the size of this pattern is preferably about 200 μm or less in terms of a circle. This is due to the fact that the size of crystal grains formed by crystallization by heating using nickel is 200 μm to 300 μm.
[0135]
After the amorphous silicon film pattern as shown in FIG. 8A is formed, a nickel acetate solution is applied by spin coating to expose the rectangular amorphous silicon film patterns 802 to 804. The nickel element is in contact with and held on the surface.
[0136]
The concentration of nickel element in the nickel acetate solution is such that the nickel concentration finally remaining in the film is 1 × 10 ¹⁵ cm ^-3 ~ 5x10 ¹⁹ cm ^-3 It is necessary to adjust so as to be within the range. This is because when the concentration is higher than this concentration, the properties as a semiconductor are hindered by the influence of nickel element. In addition, if the concentration is lower than this concentration, the promoting action in crystallization of nickel element cannot be obtained. In addition, when using a metal element other than nickel, the said density | concentration range can be used as a standard.
[0137]
After the nickel acetate solution is applied, heat treatment is performed at 800 ° C. for 4 hours to crystallize the pattern indicated by 802 to 804 in FIG. As a result, a rectangular pattern having crystallinity indicated by 805 to 807 in FIG. 8B can be obtained. This pattern is substantially composed of a single crystal grain.
[0138]
Nickel elements are unevenly distributed on the edges of the patterns indicated by 805 to 807. Therefore, patterning is further performed on the patterns indicated by 805 to 807. Then, an active layer pattern of the thin film transistor indicated by 808 to 810 is formed. (Fig. 8 (C))
[0139]
The pattern of the active layer can be substantially composed of a single crystal grain. Further, since the portion where the nickel element is unevenly distributed is removed, the active layer can be in a state where the nickel element is not unevenly distributed.
[0140]
Here, a configuration in which one active layer pattern of a thin film transistor indicated by 808 is obtained from a rectangular pattern indicated by 805 is shown. However, it is also possible to obtain a pattern of two or more active layers.
[0141]
In this way, the active layer can be obtained in a state where the influence of the crystal grain boundary and the metal element that promotes crystallization is suppressed.
[0142]
【The invention's effect】
By utilizing the invention disclosed in this specification, a crystalline silicon film with extremely excellent crystallinity can be obtained. In particular,
High crystallinity can be obtained by using a metal element that promotes crystallization of silicon.
-By using a metal element that promotes crystallization of silicon, the crystallization time can be shortened.
-By performing heat treatment at a high temperature of 800 ° C. to 1100 ° C., it is possible to prevent the metal elements from being concentrated locally.
A thin film transistor having high mobility can be formed because of high crystallinity.
A thin film transistor having a low OFF current value can be formed because it has high crystallinity and no concentration of metal elements.
[Brief description of the drawings]
FIG. 1 shows a manufacturing process of a crystalline silicon film in an example.
FIG. 2 illustrates a manufacturing process of a thin film transistor in an example.
FIG. 3 illustrates a manufacturing process of a thin film transistor in an example.
FIG. 4 illustrates a manufacturing process of a thin film transistor in an example.
FIG. 5 illustrates a manufacturing process of a thin film transistor in an example.
FIG. 6 illustrates an example of characteristics of a thin film transistor in an example.
FIG. 7 shows a list of manufacturing conditions and characteristics of examples and comparative examples.
FIG. 8 shows a manufacturing process of the example.
[Explanation of symbols]
101, 201 Quartz substrate (or glass substrate)
301 quartz substrate
102, 202, 302 Base film (silicon oxide film)
103 Amorphous silicon film
104 spinner
105 Water film of nickel acetate solution
107 crystalline silicon film
203, 303, 304, 305 Active layer
204, 306 Gate insulation film
205, 307, 308, 309 Gate electrode
206 Source area
207 Channel formation region
208 Drain region
209, 320 Interlayer insulating film
210 Source electrode
211 Drain electrode
31 Thin film transistor characteristics of the example
32 Characteristics of Thin Film Transistors as Comparative Examples
310, 315, 316 Source / drain regions
317 Low concentration impurity region
313 resist mask
314 resist mask
318 resist mask
321,322,323,324 electrodes
325 electrode
326 Passivation film
327 ITO electrode (pixel electrode)

Claims (4)

Forming an amorphous silicon film;
Patterning the amorphous silicon film to form an island-shaped amorphous silicon film;
The island-shaped amorphous silicon film is held in contact with a metal element that promotes crystallization of silicon, and heat treatment is performed at a temperature of 800 to 1100 ° C. to form an island-shaped crystalline silicon film,
A method of manufacturing a thin film transistor, comprising patterning the island-shaped crystalline silicon film to form an active layer of the thin film transistor. Forming a base film,
Forming an amorphous silicon film on the base film;
Patterning the amorphous silicon film to form an island-shaped amorphous silicon film;
The island-shaped amorphous silicon film is held in contact with a metal element that promotes crystallization of silicon, and heat treatment is performed at a temperature of 800 to 1100 ° C. to form an island-shaped crystalline silicon film,
A method of manufacturing a thin film transistor, comprising patterning the island-shaped crystalline silicon film to form an active layer of the thin film transistor. Oite to claim 1 or claim 2, wherein the island-shaped amorphous silicon film can be square, rectangular, polygonal, a method for manufacturing a thin film transistor which is characterized in that either circular or elliptical. In any one of claims 1 to 3, wherein the metal element, Fe, Co, Ni, Ru , Rh, Pd, Os, Ir, Pt, Cu, one or plural kinds selected from Au element A method for manufacturing a thin film transistor, wherein:

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