JP4616548B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine or a slot machine, and more particularly to a gaming machine equipped with a plurality of data storage media having the same or similar outer shape.

  Currently, game machines such as pachinko machines and slot machines control the progress of games by program control, and a semiconductor chip of a storage element such as a processor or ROM is mounted on a control board. If there is an error in the semiconductor chip on the control board, the game cannot proceed normally. Also, fraud can be easily performed by exchanging the semiconductor chip mounted on the control board. For this reason, confirmation of the semiconductor chip mounted on the control board is an important factor.

  As a method for confirming a semiconductor chip mounted on a control board of a gaming machine, a gaming machine having a function of checking whether or not a program stored in a program storage element has been modified has been proposed (for example, Patent Document 1). In this gaming machine, the program is confirmed, and the program storage element is substantially confirmed by detecting the instruction fetch cycle for reading the program and the address signal.

Japanese Patent Laid-Open No. 5-293241

  By the way, pachinko machines, slot machines, and other gaming machines are not limited to simply advancing the game, but are generally designed to enhance the fun of the game by providing various effects according to the progress of the game. is there. In recent gaming machines, emphasis has been placed on the performance rather than the progress of the game itself.

  If there are many types of effects, a large amount of storage capacity is required for effect data to execute effects, and many semiconductor chips of data storage media storing effect data will be mounted on the control board. become. A plurality of semiconductor chips of the data storage medium having the same shape may be mounted on the same control board. It is an important issue to efficiently confirm whether such a large number of semiconductor chips are mounted at the correct position on the control board or whether the data content of the semiconductor chips mounted on the control board is correct. It has become to.

  However, in the gaming machine described in Patent Document 1, since the confirmation is performed according to the instruction fetch cycle and the address signal, the method can be applied to the program storage medium but not the data storage medium. In order to confirm whether the data storage medium is mounted at the correct position and whether the data contents are correct, another method must be applied.

  In addition, the gaming machine is provided with notifying means for notifying information related to the game by being controlled by a control device of the gaming machine and emitting sound or light to the viewer or performing a special movement. There are many cases. For this reason, using this notification means, the result of confirmation of the data storage medium may be notified to the worker performing the confirmation work. However, when the notification means notifies the result of the confirmation, if an operation other than notifying the confirmation result by the notification means is performed under the control of the control device, the notification of the confirmation result is terminated. End up. If it does so, there was a possibility that the person who is performing confirmation work may overlook the information on the result of confirmation.

  Furthermore, in the case of gaming machines such as pachinko machines and slot machines, there is a situation that is different from other electronic devices that it is necessary to prevent fraud after shipment, and it is applied to other electronic devices. In some cases, the method cannot simply be applied. As described above, in a gaming machine such as a pachinko gaming machine or a slot machine, there has been a demand for a method for efficiently checking the mounting position and the data content of a semiconductor chip mounted on a control board.

  It is an object of the present invention to efficiently check whether or not a data storage medium is mounted at a correct position on a board in a gaming machine such as a pachinko gaming machine or a slot machine.

In order to achieve the above object, a gaming machine according to the present invention provides:
A plurality of effect data storage media having the same or similar outer shape and different stored data are mounted on the substrate, and data stored in each effect data storage medium mounted on the substrate A game machine comprising: a control means for executing processing relating to a game using a game machine; and an effecting means for producing an effect according to the progress of the game,
Test effect data for performing the test effect of the effect means is distributed and stored in the plurality of effect data storage media,
The control means includes
Data reading means for reading test effect data from the plurality of effect data storage media by inputting a confirmation command signal for instructing execution of the test effect of the effect means to the control means from outside;
Test effect execution means for performing control to combine the test effect data read by the data reading means from all of the plurality of effect data storage media and execute the test effect by the effect means; It is characterized by.

According to this gaming machine, test effect data is distributed and stored in a plurality of effect data storage media, so that the data in each effect data storage medium is incorrect or each effect data storage medium is If it is not mounted at the correct position, the test effect cannot be executed normally. Therefore, test effect data read from all of the plurality of effect data storage media are combined to test the effect means, and whether the data in each effect data storage medium is correct, each effect data storage medium It can be confirmed whether is mounted in the correct position.

According to the first aspect of the present invention, test effect data read from all of the plurality of effect data storage media are combined to test the effect means, and whether the data in each effect data storage medium is correct. It is possible to confirm whether each production data storage medium is mounted at the correct position.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

  FIG. 1 is a front view showing the overall structure of the slot machine according to this embodiment. FIG. 2 is a view showing an internal structure visually recognized with the front door of the slot machine of FIG. 1 opened. FIG. 3 is a view showing the structure of the rear side of the front door of the slot machine of FIG. The front door of the slot machine 1 can be opened by inserting a key into the locking device 19 (FIG. 1) and turning it clockwise.

  With reference to FIGS. 1 to 3, a variable display device 2 is provided on the upper front side of the slot machine 1. Inside the variable display device 2, a reel unit 3 including three reels 3L, 3C, and 3R is provided. The reels 3L, 3C, and 3R are rotated / stopped by driving the reel motors 3ML, 3MC, and 3MR, respectively.

  On the outer peripheries of the reels 3L, 3C, and 3R, symbols such as “colorless 7”, “colored 7”, “BAR”, “JAC”, “watermelon”, “cherry”, and “bell” are in a predetermined order. It is drawn in. The symbols drawn on the outer peripheries of the reels 3L, 3C, and 3R are displayed on the upper, middle, and lower three stages on the variable display device 2. The reel unit 3 is provided with reel sensors 3SL, 3SC, 3SR for detecting the reference position of each of the reels 3L, 3C, 3R, and a reel lamp 3LP for irradiating light from the back. Yes.

  Various display units are provided around the variable display device 2. Below the variable display device 2, a game number display unit 21, a credit display unit 22, and a payout display unit 23 are provided. The game number display unit 21 is constituted by a game number display 51 by a 7-segment display, and displays the value of a counter that counts the number of games and the number of winnings at the time of a big bonus or a regular bonus.

  The credit display unit 22 is constituted by a credit display 52 by a 7-segment display, and displays the number of credits accumulated as data according to the number of inserted medals and the number of paid-out coins as will be described later. The payout display unit 23 is composed of a 7-segment display payout display 53, and displays the number of medals to be paid out when winning is achieved.

  On the left side of the variable display device 2, a one-bet display unit 24, two-bet display units 25 and 26, and three-bet display units 27 and 28 are provided. The 1, 2, and 3 bet display sections 24 to 28 correspond to the activated lines according to the number of bets (hereinafter referred to as “active lines”), respectively. When 58 is turned on, an effective line in each game is shown to the player. The 1-sheet, 2-sheet, 3-sheet betting display sections 24 to 28 also indicate that the 1-sheet, 2-sheet, 3-sheet betting lamps 54-58 are in a blinking state when any winning combination is won. , Show the player the active line that won the role.

  On the right side of the variable display device 2, an insertion instruction display unit 29, a start display unit 30, a weight display unit 31, a replay display unit 32, and a game over display unit 33 are provided. The insertion instruction display unit 29 indicates that a medal can be inserted when the insertion instruction lamp 59 is turned on. The start display unit 30 indicates that the start lamp 60 is turned on, so that the start can be started, that is, the operation of the start lever 11 can be accepted. The weight display unit 31 indicates that a weight to be described later is applied when the weight lamp 61 is turned on. The replay display unit 32 indicates that a replay prize has been won when the replay lamp 62 is turned on. The game over display unit 33 indicates that the slot machine 1 has been stopped when the game over lamp 63 is turned on.

  On the upper side of the variable display device 2, a liquid crystal display 4 is provided as rendering means and image display means. The liquid crystal display 4 displays images for various effects (informing) according to the progress of the game. As will be described later, the liquid crystal display 4 also serves as a notification unit of the present invention. An image for production (notification) is composed of, for example, a series of moving images, and an announcement (internal lottery) that an internal lottery has been won or there is a possibility depending on the process and final screen of the production. Or a notice (notifying that there is a possibility of winning the internal lottery). The liquid crystal display 4 is also used for displaying and notifying a test result of a data ROM, which will be described later, as an image.

  A medal slot 13, a single BET button 14, a MAXBET button 15, and a checkout button 16 are provided on a horizontal surface of a trapezoidal portion provided below the variable display device 2. The BET button lamps 70a and 70b (see FIG. 4), which are turned on when the number of bets can be set from the credits (maximum 50) accumulated as data, are arranged inside the single BET button 14 and the MAX BET button 15. Has been.

  The medal insertion slot 13 is for a player to insert a medal from here, and when the insertion medal sensor 44 detects the insertion of a medal when the insertion instruction display unit 29 is lit, a bet number is set. Alternatively, credits are accumulated as data. The single BET button 14 and the MAX BET button 15 are buttons operated by the player when setting the number of bets (1, 3 respectively) from the credits accumulated as data. When it is detected by the sheet BET switch 45 (see FIG. 4) or the MAXBET switch 46 (see FIG. 4), the bet number from the credit is set. The settlement button 16 is a button for instructing the payout of credits. When an operation is detected by the settlement switch 47 (see FIG. 4), medals corresponding to the credits accumulated as data are paid out.

  A start lever 11 and stop buttons 12L, 12C, and 12R are provided on the vertical surface of the trapezoidal portion. Further, a panel covering the stop buttons 12L, 12C, and 12R is applied as the bonus notification unit 36. The stop buttons 12L, 12C, and 12R can be operated in any order, and the rotation of the reels 3L, 3C, and 3R is stopped according to the operation order.

  The start lever 11 is operated by the player when starting the game. When the operation is detected by the start switch 41 (see FIG. 4), the reel drive motors 3ML, 3MC, 3MR are started to be driven. 3L, 3C, and 3R start to rotate. The stop buttons 12L, 12C, and 12R are buttons that the player operates to stop the rotation of the reels 3L, 3C, and 3R at a desired timing, respectively, and the operations are stop switches 42L, 42C, and 42R (see FIG. 4). Is detected, the rotation of the reels 3L, 3C, 3R is stopped.

  It is shown to the player that the operation of the stop buttons 12L, 12C, 12R is possible by turning on the operation effective lamps 63L, 63C, 63R (see FIG. 4) provided therein. The bonus notification unit 36 notifies the player that the big bonus winning flag or the regular bonus winning flag, which will be described later, is set with a probability of 100% by turning on the bonus notification lamp 66 (see FIG. 4). To do. Further, on the right side of the stop button 12R, there is provided a medal clogging elimination button 18 that mechanically vibrates the slot machine 1 when a medal is jammed.

  On the lower front side of the slot machine 1, a medal payout port 71 and a medal storage tray 72 are provided. The medal payout port 71 discharges medals paid out by the hopper 80 to the outside. The hopper 80 includes a hopper motor 82 that performs a medal payout operation, and a payout sensor 81 that detects the medal payout. The medal storage tray 72 is for storing paid-out medals. The front panel on the medal storage tray 72 is irradiated with light emitted from the fluorescent lamp 6 (see FIG. 4) installed therein. A full tank sensor 90 is provided inside the overflow tank 95 for storing medals overflowing from the hopper 80 to detect that the stored medals are full.

  Speakers 7U, 7L, and 7R are provided as rendering means on the lower front side of the slot machine 1 and on the left and right sides of the upper front side, respectively. Speakers 7U, 7L, and 7R output sound effects at the time of winning, big bonus and regular bonus entry, and output of alarm sound at the time of abnormality, and also output sound for various effects according to the gaming state Do. The speakers 7U, 7L, and 7R are also used for outputting and notifying a test result of a data ROM described later by voice.

  Further, on the front side of the slot machine 1, a game effect display unit 5 </ b> A that produces an effect by light by light emission of the game effect lamps 75 </ b> A to 75 </ b> M as an effect means so as to surround the variable display device 2 and the liquid crystal display 4. ~ 5M are provided. The game effect display units 5A to 5M perform effects by light in various patterns according to the progress of the game. Note that the light emission colors of the game effect display units 5A to 5M may be either single colors or multiple colors. By causing the game effect lamps 75A to 75M to emit light, the game effect display units 5A to 5M can be used to notify the test result of the data ROM.

  Further, inside the slot machine 1, there are a setting switch 91 for setting a winning probability for internal lottery, a setting key switch 92 for enabling the setting switch 91 to be operated by an unlocking operation, and an internal state (RAM 112 (see FIG. 5)). There is provided a power supply unit 9 including a second reset switch 93 for resetting and a main switch 94 for switching power ON / OFF. A first reset switch 48 having the same function as the second reset switch 93 is provided at a position corresponding to the locking device 19 on the rear side of the front door.

  As a control board for controlling each of the above parts, a power supply board 100 arranged on the lower side inside the game, a game control board 101 arranged on the upper side inside, a reel relay board 103, a reel lamp relay board 104, an external output board 105, and An effect control board 102 arranged on the back side of the front door is provided. FIG. 4 is a diagram showing a configuration of a control circuit of the slot machine 1 including the control boards 100 to 105. FIG. 5 is a diagram showing circuit components and signal wirings mounted on the game control board 101 and the effect control board 102.

  The power supply board 100 transforms an external power supply voltage of AC 100V and supplies operating power to the game control board 101 and other parts of the slot machine 1. In FIG. 4, the power supply board 100 is connected only to the game control board 101 and the hopper 80, but power is also supplied to other parts. In addition, a setting switch 91, a setting key switch 92, a second reset switch 93, and a main switch 94 are connected to the power supply board 100, and detection signals from these switches are sent to the game control board 101.

  The game control board 101 is a control board that controls the overall flow of the game in the slot machine 1, and is equipped with a control unit 110 composed of a one-chip microcomputer including a CPU 111, a RAM 112, a ROM 113, and an I / O port 114. Yes. Further, a random number generation circuit 115, a sampling circuit 116, a buffer circuit 117, a switch circuit 118, a motor circuit 119 and other circuits are mounted.

  The CPU 111 has a timekeeping function and a timer interrupt function, executes a program stored in the ROM 113 to perform processing related to the progress of the game, and directly or indirectly controls each part of the control circuit in the slot machine 1. . The RAM 112 is used as a work area when the CPU 111 executes a program, and is provided with a storage area for various winning flags, various gaming state flags, or various counter values described later. The ROM 113 stores programs executed by the CPU 111 and fixed data. The I / O port 114 inputs and outputs control signals to and from each circuit connected to the game control board 101.

  The random number generation circuit 115 is configured by a counter that counts at a predetermined time interval (for example, 2 milliseconds), and the sampling circuit 116 acquires a numerical value generated by the random number generation circuit 115. The CPU 111 sends an instruction to the sampling circuit 116 according to the processing to acquire the numerical value indicated by the random number generation circuit 115 as a random number (hereinafter, this function is referred to as a hardware random number function). The CPU 111 transmits various commands to be described later to the effect control board 102 via the I / O port 114 and the buffer circuit 117. Note that information is sent from the game control board 101 to the effect control board 102 in only one direction, and no information is sent from the effect control board 102 to the game control board 101.

  Connected to the game control board 101 are a single BET switch 45, a MAXBET switch 46, a start switch 41, stop switches 42L, 42C, 42R, a settlement switch 47, a first reset switch 48, and a throw-in medal sensor 44. Detection signals from the switches / sensors are input. In addition, detection signals of the reel sensors 3SL, 3SC, and 3SR are input via the reel relay substrate 103. In accordance with the detection signals of these switches / sensors input via the I / O port 114 or the detection signals of various switches input via the power supply board 100 as described above, the CPU 111 on the game control board 101 Processing is in progress.

  The game control board 101 also includes a flow path switching solenoid 49, a game number display 51, a credit display 52, a payout display 53, a loading instruction lamp 59, a single betting lamp 54, two betting lamps 55, 56, Three betting lamps 57 and 58, a game over lamp 63, a start lamp 60, a replay lamp 62, BET button lamps 70a and 70b, and operation valid lamps 63L, 63C, and 63R are connected, and the CPU 111 follows the progress of the game. These operations are controlled. The game control board 101 is connected to reel motors 3ML, 3MC, and 3MR via a reel relay board 103, and the CPU 111 is connected to the reels 3L, 3C, and 3R via a motor circuit 119 and the reel relay board 103. Controls rotation and stop.

  The effect control board 102 is a control board that controls the execution of an effect (notification) in the slot machine 1 and includes a control unit 120 including a CPU, a sub processor, a ROM, a RAM, and the like. The effect control board 102 corresponds to the board of the present invention. The control unit 120 performs processing related to the execution (informing) in the slot machine 1 as processing related to the game in the slot machine 1, and controls each circuit in the effect control board 102 and each circuit connected thereto. . The performance (notification) is performed based on the notification command signal received from the game control board 101 via the buffer circuit 130 and the game control command as the game control command signal. The control unit 120 corresponds to the control means of the present invention. Details of the control unit 120 will be described later.

  The effect control board 102 is also equipped with a random number generation circuit 134 and a sampling circuit 135, and the control unit 120 acquires a value counted by the random number generation circuit 134 by the sampling circuit 135, whereby the game control board 101 The same hardware random number function is formed.

  The effect control board 102 is connected with game effect lamps 75A to 75M, a liquid crystal display 4, speakers 7L, 7R, and 7U, a fluorescent lamp 6, a weight lamp 61, and a bonus notification lamp 66. In order to drive these, A speaker driving circuit 131, a display driving circuit 132, a lamp driving circuit 133, and the like are provided. A reel lamp 3LP is connected via a reel lamp relay substrate 104. The control unit of the production control board 102 controls each of these units to produce production (notification).

  The reel relay board 103 relays between the game control board 101, the external output board 105 and the reel unit 3. The reel relay substrate 103 is also connected with a full sensor 90, and its detection signal is input. The reel lamp relay board 104 relays between the effect control board 102 and the reel unit 3. The external output board 105 is connected to an external device such as a hall management computer and receives a big bonus medium signal, regular bonus medium signal, reel control signal, stop signal input from the game control board 101 via the reel relay board 103. The switch signal, medal IN signal, and medal OUT signal are output to the external device.

  Next, the control unit 120 provided on the effect control board 102 will be described in detail. FIG. 6 is a diagram showing the control unit 120 in detail. As illustrated, the control unit 120 includes a CPU 121 including an internal RAM 122, a program ROM 123, three data ROMs 124-1 to 122, a VDP (video processor) 125 including an attribute RAM 125a, a VRAM (video RAM) 126, and a work RAM 127a. And an ADP (audio processor) 127.

  The CPU 121, the program ROM 123, the data ROMs 124-1 to 13-4, the VDP 125, the VRAM 126, and the ADP 127 are each constituted by individual semiconductor chips. Each of the data ROMs 124-1 to 22 is a symmetric semiconductor chip with 22 pins, and the outer shape is the same or approximate, but the data stored therein is different. The data ROMs 124-1 to 12-4 correspond to the data storage medium of the present invention. Other chips have different pin numbers and outer shapes. The semiconductor chips of the CPU 121, the program ROM 123, the data ROMs 124-1 to 3, the VDP 125, the VRAM 126, and the ADP 127 are mounted on the effect control board 102 by fitting their pins into sockets formed in advance on the effect control board 102. Is done.

  The CPU 121 executes a program stored in the program ROM 123 to perform processing related to the execution of the effect (notification), and controls each circuit in the effect control board 102 and each circuit connected thereto. The CPU 121 has an internal timer. An arbitrary specific value (an address at which an instruction to be executed is stored) can be set in the program counter of the CPU 121 according to the program being executed. However, the value of the program counter is usually incremented by one.

  Further, the CPU 121 executes a program stored in the program ROM 123 to test each circuit in the effect control board 102. Production (informing) and test execution are performed based on the control data set in the control data queue shown below. Setting of control data in the control data queue is performed based on a command received from the game control board 101 via the buffer circuit 130. The CPU 121 as display control means functions as notification execution means, data reading means, confirmation means, confirmation result notification means, notification protection means, check data generation means, release means, write instruction means, and test effect execution means of the present invention. To do.

  The RAM 122 is used as a work area when the CPU 121 executes a program. The RAM 122 is provided with a first-in first-out control data queue for setting the control data as a queue for the CPU 121 to execute processing corresponding to each command. For convenience of explanation, it is assumed that the size of the control data queue is infinite. When the control data is set, the control data is added to the tail of the control data queue. When the CPU 121 finishes the process based on the control data, the next control data is fetched and the process based on the control data continues. Done. The program ROM 123 stores a program executed by the CPU 121.

  The data ROMs 124-1 to 12-3 store fixed data for executing production (notification). The data ROMs 124-1 and 12-4 store image data, and the data ROM 124-3 stores sound data and lamp data. The image data is data of numbers, characters, symbols, graphics, and the like displayed on the liquid crystal display 4, the audio data is data of various sounds output from the speakers 7L, 7R, and 7U, and the lamp data is This is data for causing the game effect LEDs 5A to 5M to emit light. The data ROMs 124-1 to 12-3 also store test data for performing a test (data check) described later. Details of the configuration of data stored in the data ROMs 124-1 to 124-1 will be described later.

  In the attribute RAM 125a, image processing instruction information as information for specifying a processing result corresponding to each command is written. The attribute RAM 125a corresponds to a temporary storage area of the present invention. The image processing instruction information includes data designating image data to be read from the data ROMs 124-1 and 12-12 and attributes of the image data (size, moving direction, moving amount, display priority, etc.). The CPU 121 writes the image processing instruction information in the attribute RAM 125a according to each command.

  In accordance with the image processing instruction information written in the attribute RAM 125a, the VDP 125 once transmits the image data from the data ROMs 124-1 and 12-12 mounted at the mounting position of the socket corresponding to the liquid crystal display 4 on the effect control board 102. Read to. At this time, the image data is read out to an area different from the area in which the image processing instruction information is written in the attribute RAM 125a. The VDP 125 develops an image according to the image processing instruction information in the VRAM 126 using the image data read to the attribute RAM 125a. The VRAM 126 corresponds to the image development area of the present invention. The VDP 125 outputs the image developed on the VRAM 126 to the display drive circuit 132 as a video signal including a synchronization signal (horizontal synchronization signal, vertical synchronization signal). The VDP 125 corresponds to the image creation unit of the present invention.

  In accordance with an instruction from the CPU 121, the ADP 127 reads audio data from the data ROM 124-3 mounted at the socket mounting position corresponding to the speakers 7L, 7R, 7U and the game effect LEDs 5A to 5M on the effect control board 102 to the work RAM 127a. Then, an audio signal is generated based on the audio data temporarily stored in the work RAM 127a, and is output to the speaker drive circuit 131. In accordance with an instruction (command) from the CPU 121, the ADP 127 also executes lamp data from the data ROM 124-3 mounted at the mounting position of the socket corresponding to the speakers 7L, 7R, 7U and the game effect LEDs 5A to 5M on the effect control board 102. Is output to the work RAM 127a, and a signal for driving the game effect LEDs 5A to 5M is output to the lamp driving circuit 133 based on the lamp data temporarily stored in the work RAM 127a.

  The CPU 121 cannot directly read the data stored in the data ROMs 124-1 to 124-3, but can read any data temporarily stored in the attribute RAM 125a of the VDP 125 or the work RAM 127a of the ADP 127. When it is necessary to read test data in the data ROMs 124-1 to 12-3 in a test described later, the CPU 121 uses the attribute RAM 125a or the work RAM 127a as will be described in detail later.

  The speaker drive circuit 131 drives the speakers 7L, 7R, and 7U according to the audio signal output from the ADP 127, and outputs audio. The display driving circuit 132 drives the liquid crystal display 4 according to the video signal output from the VDP 125 to display an image. The lamp driving circuit 133 drives the game effect lamps 75A to 75M according to the signal output from the ADP 127, and emits them.

  Next, the test of the data ROMs 124-1 to 12 will be described. The test of the data ROMs 124-1 to 124-3 is performed to check whether or not the data ROMs 124-1 to 124-3 are inserted at the correct positions in the sockets for mounting the data ROMs 124-1 to 124-3 on the production control board 102. It is checked whether the data in the read data ROMs 124-1 to 12-3 is correct. For this data check, test data for data check is stored in advance in the data ROMs 124-1 to 12-3 together with image data or audio data and lamp data.

  FIGS. 7A to 7C are diagrams showing the structures of data stored in the data ROMs 124-1 to 12-3, respectively. As shown in these drawings, the top addresses when the data ROMs 124-1 to 12-3 are inserted into the sockets on the effect control board 102 at the correct positions are the X address, the Y address, and the Z address, respectively. In each of the data ROMs 124-1 to 124-3, test data is stored at positions after the first address, a-address, b-address, c-address, and d-address.

  That is, when the data ROM 124-1 is inserted into the socket on the production control board 102 at the correct position, the test data is stored at addresses X + a, X + b, X + c, and X + d in the data ROM 124-1. When the test data Xa, Xb, Xc, and Xd stored at each address are added, the value becomes X. When the data ROM 124-2 is inserted into the socket on the effect control board 102 at the correct position, the data ROM 124-2 stores test data at addresses Y + a, Y + b, Y + c, and Y + d. When the test data Ya, Yb, Yc, Yd stored in the address are added, the value becomes Y. When the data ROM 124-3 is inserted into the socket on the production control board 102 at the correct position, the test data is stored at addresses Z + a, Z + b, Z + c, and Z + d in the data ROM 124-3. When the test data Za, Zb, Zc, Zd stored in the address are added, the value becomes Z.

  On the other hand, when the data ROMs 124-1 to 12-3 are not inserted into the sockets on the effect control board 102 at the correct positions, the following occurs. For example, assuming that the data ROM 124-2 is inserted into the socket into which the data ROM 124-1 is to be inserted, when the data is read from the addresses X + a, X + b, X + c, and X + d, the actually read data is Ya. , Yb, Yc, Yd, and the value obtained by adding them is Y, not X, which should be the original value.

Further, when there is a defect in the data ROMs 124-1 to 12-3 inserted into the sockets on the production control board 102 and there is an error in the stored data, the following occurs. For example, if there is a data defect in the data ROM 124-1, when data is read from addresses X + a, X + b, X + c, and X + d, Xa, Xb, Xc, and Xd are not prepared in the actually read data. The result of the addition is not X. In addition, the value obtained as a result of adding the read data hardly becomes Y or Z probabilistically.
Note that image data, audio data, and lamp data are stored at addresses other than the addresses where the test data of the data ROMs 124-1 to 130-3 are stored.

  Incidentally, in order for the CPU 121 to read test data from the data ROMs 124-1 to 124-1, the attribute RAM 125 a or the work RAM 127 a is used as described above. The reading of the test data will be described in detail. FIGS. 8A to 8D are diagrams for explaining the procedure of reading test data from the data ROMs 124-1 to 12 by the CPU 121. FIG. Here, a case where data is read from the data ROM 124-1 will be described as an example.

  When reading test data from the data ROM 124-1, first, as shown in FIG. 8A, the CPU 121 sends a test data read instruction to the VDP 125 together with the address of the test data to be read. The test data read instruction is written in the attribute RAM 125a. Next, as shown in FIG. 8B, the VDP 125 accesses the address included in the instruction from the CPU 121 and reads out the instructed test data from the data ROM 124-1. Then, as shown in FIG. 8C, the read test data is temporarily stored in the attribute RAM 125a.

  Thereafter, as shown in FIG. 8D, the CPU 121 reads the test data stored in the attribute RAM 125a from the VDP 125. When reading the test data from the data ROM 124-2, the operation is performed in exactly the same procedure as described above. However, when reading the test data from the data ROM 124-3, the ADP 127 is interposed instead of the VDP 125. The operation is performed in the same procedure as shown in (a) to (d).

  For example, in the case of the data ROM 124-1, the CPU 121 reads the data from the addresses X + a, X + b, X + c, and X + d according to the procedure shown in FIGS. Ask for. The same applies to the data ROMs 124-2 and 3 as well. The result of the data check is obtained by comparing the addition result with X, Y, and Z, which are verification data.

The result of the data check by the CPU 121 is notified by an image displayed on the liquid crystal display 4 or by sound output from the speakers 7L, 7R, and 7U. Whether the notification is made by the image or the sound is determined by the data content of the data ROMs 124-1 to 12-3 subjected to the data check. FIGS. 9A to 9D are diagrams showing a mode of notifying the result of the data check of the data ROMs 124-1 to 12 by the CPU 121. FIG.

When the data check target is a data ROM 124-3 for storing audio data and lamp data (actually, a data ROM inserted in a socket at a position where the data ROM 124-3 is to be inserted). As shown in FIG. 9A or 9B, the check result is notified by displaying an image on the liquid crystal display 4.

  As a result of the data check, for example, if it is determined that the data ROM 124-2 is actually inserted into the socket at the position where the data ROM 124-3 is to be inserted, as shown in FIG. For example, the image “ROM of image B is mounted at a position where the ROM of the sound / lamp is to be mounted” is displayed. As a result of the data check, if it is determined that there is a data defect in the data ROM that has been inserted into the socket at the position where the data ROM 124-3 is to be inserted, as shown in FIG. "The ROM data is not correct."

  The data ROM 124-1 or 124-2 for storing image data is the target of the data check (actually, the data ROM inserted into the socket where the data ROM 124-1 or 124-2 is to be inserted). In such a case, as shown in FIG. 9C or 9D, the check result is notified by outputting sound from the speakers 7L, 7R, and 7U.

  As a result of the data check, if it is determined that the data ROM 124-2 is actually inserted into the socket at the position where the data ROM 124-1 is to be inserted, as shown in FIG. “The image B ROM is mounted at the position where the image A ROM is to be mounted” is output as a voice. As a result of the data check, if it is determined that there is a data defect in the data ROM inserted into the socket at the position where the data ROM 124-1 is to be inserted, for example, as shown in FIG. "ROM data is not correct." However, in the case of notification by voice output, a warning sound having a different aspect may be output for each result of data check, instead of notification by words.

  Hereinafter, the operation of the slot machine 1 according to this embodiment will be described. When the slot machine 1 is in the game progress mode, from the setting of the number of bets to the rotation / stop of the reels 3L, 3C, 3R, the winning determination based on the display mode of the variable display device 2 when stopped, to the payout of medals A game including a series of processes is repeatedly performed. More specifically, each game process is performed as follows.

  When processing of one game is started, the player sets the bet number by inserting medals from the medal insertion slot 13 or by operating the BET buttons 14 and 15. If the player has won a replay in the previous game, the bet number in the previous game is automatically set. After setting the number of bets, the player operates the start lever 11. When the start lever 11 is operated, the CPU 111 of the game control board 101 performs an internal lottery to determine in advance whether or not the winning of each combination is permitted by extracting a random number. A winning flag corresponding to the combination is set in the RAM 112.

  Further, when the start lever 11 is operated, rotation (fluctuation) of the reels 3L, 3C, and 3R is started. Thereafter, when the player operates the stop buttons 12L, 12C, and 12R, the rotation of the reels 3L, 3C, and 3R is stopped. The reels 3L, 3C, and 3R also stop rotating when a certain time has elapsed from the start of rotation. When the rotation of the reels 3L, 3C, 3R is stopped, so-called pull-in control is performed in which a symbol corresponding to the winning flag is displayed on the active line in accordance with the timing of the stopping operation and the winning flag set in the RAM 112. Will be done.

  When the rotation of the reels 3L, 3C, and 3R is stopped, it is determined whether or not the symbols are aligned on the effective line according to the display mode of the variable display device 2 at that time. When the winning symbols are prepared, the CPU 111 performs various settings (including setting of the number of medals to be paid out and setting of flags relating to the gaming state) according to the winning winning combination. Then, when the planned payout number is set in the winning determination process, only the planned number of medals are paid out (or credits are increased). This completes the process for one game, and shifts to the process for the next game.

  While the processing of each game is repeatedly performed in the game progress mode as described above, the CPU 111 of the game control board 101 performs a game control command for performing various effects (notifications) according to the progress of the game. Is transmitted to the effect control board 102.

  The slot machine 1 also has a test mode in addition to the game progress mode as described above. The test mode is when the slot machine 1 is turned on by the main switch 94 or reset by the reset switches 48 and 93, even when the slot machine 1 is installed at the amusement store after shipment from the factory. When the operation is performed, the operation is performed prior to the game progress mode.

  When the slot machine 1 is in the test mode, the CPU 111 of the game control board 101 performs processing for performing various tests regardless of the progress of the game. The test includes a data check of the data ROMs 124-1 to 12-3 inserted in each socket of the effect control board 102.

  The CPU 111 of the game control board 101 transmits a data check command as a confirmation command signal to the effect control board 102 in order to perform data check of the data ROMs 124-1 to 124-1. In addition, when another type of test is performed on the side of the effect control board 102, the CPU 111 transmits a command corresponding to the test to be performed to the effect control board 102. The command transmission mode is the same for commands related to effects (notification) and tests.

  On the other hand, the effect control board 102 is operated according to commands sent from the game control board 101 in the game progress mode and the test mode. That is, if a command related to various effects (notifications) is sent in the game progress mode, an effect (notification) corresponding to the received command is performed, and commands related to various tests are sent in the test mode. In this case, an effect (notification) corresponding to the received command is performed. However, the control unit 120 of the effect control board 102 does not perform the operation by distinguishing between the game progress mode and the test mode.

  FIG. 10 is a flowchart showing a power-on process executed by the CPU 121 of the effect control board 102 when the power of the slot machine 1 is turned on. In the power-on process, first, timing is started by an internal timer (step S101). After starting the timing, it is determined whether an initialization command or a power recovery command transmitted from the game control board 101 has been received (step S102). Note that the power recovery command is a command transmitted from the game control board 101 when a power error occurs before the power is turned on, the power is shut off, and the power-off state is backed up. The initialization command is a command transmitted from the game control board 101 when the power is turned on when the power-off state is not backed up.

  If the predetermined time has elapsed since the start of the internal timer without receiving the initialization command or the power recovery command, it is determined that the effect control board 102 and the game control board 101 are not normally connected, and the data The same data check control data set by reception of the check command is set in the control data queue. The control data queue is a queue in which control data for executing processing according to each command by the CPU 121 is arranged. Since the control data queue is empty when the power is turned on, the control data for data check is placed at the head of the control data queue (step S104).

  When an initialization command or a power recovery command is received before the elapse of a predetermined time from the start of timing of the internal timer, the internal register of the CPU 121 and the RAM 122 are initialized, and further, according to an instruction from the CPU 121, the VDP 125, the VRAM 126, and the ADP 127 Are also initialized (step S105). The reason why such initialization processing is performed even in the case of a power recovery command is to prevent inconsistency between the processing on the game control board 101 side and the processing on the effect control board 102 side.

  Following step S104 or step S105, it is confirmed whether the control state of the CPU 121 is “command execution prohibited state” (step S106). The determination of whether or not the “command execution prohibition state” is set is made by confirming the state of the command execution prohibition flag stored in the RAM 122. The command prohibition state flag is set in step S314 (FIG. 12) described later.

  If NO is determined in step S106, the power-on process is terminated. On the other hand, if “YES” is determined in the step S106, the “command execution prohibited state” is canceled (step S107). Release of the “command execution prohibition state” is performed by clearing the command execution prohibition flag. When the “command execution prohibited state” is canceled in step S107, the power-on process is terminated.

  In the present embodiment, when an initialization command or a power recovery command is received at power-on, the internal register of the CPU 121 and the RAM 122 are initialized in step S105 described above, and further, the VDP 125 is in accordance with an instruction from the CPU 121. The VRAM 126 and the ADP 127 are also initialized. Therefore, in this case, since the command execution prohibition flag in the RAM is cleared, it is always determined as NO in step S106. Therefore, when the initialization of step S105 is not performed, or when the state of the command execution prohibition flag is stored in a storage area that is not initialized when the power is turned on, YES may be determined in step S106. It will be.

  When the power-on process is completed, the CPU 121 performs a normal process. FIG. 11 is a diagram illustrating a process executed by the CPU 121 of the effect control board 102 after the end of the power-on process. The CPU 121 performs the command reception standby process shown in FIG. 11A and the control data check process shown in FIG. 11B in parallel. These processes are executed by switching at regular intervals by, for example, timer interruption.

  In the command reception waiting process of FIG. 11A, the CPU 121 determines whether or not a command sent from the game control board 101 has been received (step S201). Until the command is received, the process of step S201 is repeated and the reception of the command is awaited. Note that the initialization command and the power recovery command are not determined here because the processing based on the initialization command and the power recovery command is performed in step S102. However, the various commands transmitted following the power recovery command are subject to determination here.

  When any command is received from the game control board 101, control data corresponding to the received command is set at the end of the control data queue (step S202). Here, when the data check command is received, the control data for data check, which is the same as that set when a predetermined time has elapsed from the start of the timing of the internal timer, is received without receiving the initialization command. It will be set (step S202). Then, the process returns to step S201.

  In the control data check process of FIG. 11B, the CPU 121 checks the control data queue and determines whether any control data is set (step S251). Until the control data is set in the control data queue, the process of step S251 is repeated, and the process waits until the control data is set. If it is determined in step S251 that control data is set in the control data queue (step S251; YES), it is confirmed whether the control state of the CPU 121 is the “command execution prohibited state” (step S252). The determination of whether or not the “command execution prohibition state” is set is made by confirming the state of the command execution prohibition flag stored in the RAM 122. The command prohibition state flag is set in step S314 (FIG. 12) described later.

  If YES is determined in the step S252, the process returns to the step S251 to repeat the process. On the other hand, if NO is determined in step S252, the first control data among the set control data is extracted (step S253). Then, it is determined what kind of control data has been taken out (step S254). When the control data extracted in step S254 is control data for data check, a data check process (FIG. 12) described later in detail is performed (step S255). When the data check process ends, the process returns to step S251.

  If the extracted control data is other types of control data (step S254: other), other processing corresponding to the type of each control data is executed (step S256). That is, if the control data is related to a test other than the data check, the test indicated by the control data is executed. If the control data is related to the effect (notification), an instruction is sent to the VDP 125 and / or ADP 127 according to the control data, and the effect (notification) is executed using the data stored in the data ROMs 124-1 to 12-3. Thereafter, the process returns to step S251.

  Next, the data check process in step S255 will be described in detail. FIG. 12 is a flowchart showing details of the data check process. In the data check process, the data ROMs 124-1 to 12-3 are correctly mounted in the sockets in which the data ROMs 124-1 to 130-3 of the effect control board 102 are to be mounted, and the data in the mounted data ROMs 124-1 to 124-3 is stored. This is a process for checking whether it is correct.

  In the data check process of FIG. 12, the first loop process is performed by sequentially substituting the values of X, Y, and Z into the variable M (steps S301 to S301 '). In the first loop, first, 0 is substituted into the variable K as an initial value (step S302). When the variable K is initialized, the values of a, b, c, and d are sequentially substituted into the variable N to perform the second loop processing (steps S303 to S303 '). In the second loop, the test data stored at addresses M + N in the data ROMs 124-1 to 12-4 is read, and the value of the read test data is substituted into the variable L (step S304). Here, when the test data is read out from the data ROMs 124-1 to 124-1, it is performed with the VDP 125 or ADP 127 interposed as shown in FIG. 8. Next, the value of the variable K and the value of the variable L are added, and the addition result is substituted into the variable K (step S305). K (for example, Xa + Xb + Xc + Xd) that is the addition result corresponds to the check data of the present invention.

  For example, when the data ROMs 124-1 to 124-1 are inserted in the sockets at the correct positions, the value of the variable M is X if the data check target is the data ROM 124-1. As the value of the variable N is sequentially changed and the processing of the second loop is performed, the values of the test data Xa, Xb, Xc, and Xd at the addresses X + a, X + b, X + c, and X + d are added to the variable K. Go. The value of the variable K when exiting the second loop is Xa + Xb + Xc + Xd = X, which is equal to the value of the variable M.

  After exiting the second loop, it is determined whether or not the value of the variable K is equal to the value of the variable M (step S306). If the value of the variable K is equal to the value of the variable M, it means that the data ROMs 124-1 to 12-12 subjected to the data check are inserted into the socket at the correct position and the data contents are correct. In this case, if there is a remaining value to be substituted into the variable M in the first loop, the next value is substituted and the processing in the first loop is performed again. If there is no remaining value to be substituted into the variable M, The first loop will be exited. When the first loop is exited, all the data check processing is terminated, and the processing returns to the processing of the flowchart of FIG.

  If the value of the variable K is not equal to the value of the variable M, it means that the data ROMs 124-1 to 12-12 subject to the data check have not been inserted into the socket at the correct position, or the data contents are not correct. become. In this case, first, it is determined whether or not the value of the variable M is Z, and it is determined whether or not the data check target is the data ROM 124-3 storing the voice data / lamp data (step S307).

  If it is determined in step S307 that the value of the variable M is not Z, the data check target is the data ROM 124-1 or 2 that stores the image data. The speakers 7L, 7R, and 7U are selected. Here, it is further determined whether or not the value of the variable K (that is, the value obtained by adding the test data) is X, Y, or Z (step S308). However, it is not determined here that the value of the variable K is equal to the value (X or Y) currently assigned to the variable M.

  If it is determined in step S308 that the value of the variable K is X, Y, or Z, the data ROM 124-1 or 2 corresponding to the current value of the variable M (X or Y) is inserted into the socket at the position where the data ROM 124-1 or 2 is to be inserted. The audio data of the correctly mounted data ROM 124-3 indicates that the inserted data ROM is one of the data ROMs 124-1 to 12-3 corresponding to the current value of the variable K (X, Y or Z). As shown in FIG. 9C, a voice is output from the speakers 7L, 7R, and 7U and notified (step S309).

  If it is determined in step S308 that the value of the variable K is not X, Y, or Z, the socket at the position where the data ROM 124-1 or 2 corresponding to the current value of the variable M (X or Y) is to be inserted. As shown in FIG. 9 (d), it is confirmed from the speakers 7L, 7R, and 7U that the data content of the data ROM inserted into the data ROM is invalid by using the audio data of the correctly mounted data ROM 124-3. A sound is output and notified (step S310).

  If it is determined in step S307 that the value of the variable M is Z, the data check target is the data ROM 124-3 storing the voice data / ramp data, so that the data check result is notified. The liquid crystal display 4 is selected as the notification means. Here, it is further determined whether or not the value of the variable K (that is, the value obtained by adding the test data) is X or Y (step S311).

  If it is determined in step S311 that the value of the variable K is X or Y, the data ROM 124-3 corresponding to the current value (Z) of the variable M has been inserted into the socket at the position where the data ROM 124-3 is to be inserted. Actually, the data ROM 124-1 or 2 corresponding to the current value (X or Y) of the variable K is shown in FIG. ), An image is displayed on the liquid crystal display 4 for notification (step S312).

  If it is determined in step S311 that the value of the variable K is neither X nor Y, the data ROM 124-3 corresponding to the current value (Z) of the variable M is actually inserted into the socket at the position where it should be inserted. The fact that the data content of the data ROM is illegal is notified by displaying an image on the liquid crystal display 4 as shown in FIG. 9B using the image data of the data ROMs 124-1 and 2 mounted correctly. (Step S313).

  As described above, in this embodiment, in step S309 and step S312, the data ROM actually mounted at the mounting position (the mounting position corresponding to the value of M) targeted in the first loop is The notification is performed in a different notification mode depending on which of the data ROMs 124-1 to 122-3. Further, following step S309, step S310, step S312, and step S313, the control state of the CPU 121 is shifted to the “command execution prohibited state” (step S314). The transition to the “command execution prohibited state” is performed by setting a command execution prohibition flag in the RAM 122. The “command execution prohibited state” corresponds to the notification protection state of the present invention. After shifting to the “command execution prohibited state” in step S314, all the data check processing is ended, and the processing returns to the processing of the flowchart of FIG.

  In the present embodiment, after the transition to the “command execution prohibited state” in step S314, the data check process is completely terminated. If NO is determined in step S306, the first loop is executed. The process of steps S307 to S314 is performed. However, instead of such processing, after it is determined NO in step S306, the notifications in steps S309, S310, S312 and S313 are performed for a necessary time so that the notification is not easily overlooked, and step S314 is performed. After proceeding to step S301 ′, the process may proceed to step S301 ′. In step S301 ′, if there is a remaining value to be substituted for the variable M, the next value is substituted and the processing in the first loop is performed again. If there is no remaining value to be substituted for the variable M, the first value is set. It will be configured to exit the loop.

  As described above, in the slot machine 1 according to the present embodiment, if a data check command is sent from the game control board 101 in the test mode, the CPU 121 reads the test data in the data ROMs 124-1 to 12-3. Based on the read test data, it is confirmed whether the correct data ROMs 124-1 to 12-3 are inserted in the respective sockets. Further, the fact that the data contents of the data ROMs 124-1 to 124-1 are not correct is confirmed as an abnormality regarding the data ROMs 124-1 to 124-1 to check whether the data contents of the data ROMs 124-1 to 124-inserted into each socket are correct. It is supposed to be. And the result is alert | reported from the liquid crystal display 4 or the speakers 7L, 7R, and 7U. This makes it possible to efficiently check whether the data ROMs 124-1 to 12-3 are correctly inserted in the sockets of the effect control board 102 or whether the data contents are correct.

  The slot machine 1 enters the test mode and the data check command is transmitted when the main switch 94 or the reset switches 48 and 93 are operated. That is, it is not necessary to perform a special operation for checking the data in the data ROMs 124-1 to 130-3, and the data check of the data ROMs 124-1 to 13 can be easily started. Since the data check command is transmitted from the game control board 101 to the effect control board 102 in the same manner as the command related to the effect (notification) sent in the game progress mode, a signal input unit for causing the CPU 121 to start data check is provided. There is no need to provide it separately.

  The test data stored in the data ROMs 124-1 to 12-4 are stored only at the addresses a, b, c, and d added to the values of the respective leading addresses. In the data check, it is only necessary to read from the corresponding addresses. Therefore, the test data can be read quickly. Further, the test data is added to each of the data ROMs 124-1 to 130-3, and only the addition result is collated with the confirmation data. For this reason, the number of collations with the confirmation data is small, and the data check can be performed quickly. Even when a plurality of test data are read from the data ROMs 124-1 to ROM-12 and strict confirmation is performed, it is only necessary to prepare one piece of confirmation data for collation with the addition result of each test data. Therefore, it is possible to strictly check the data ROMs 124-1 to 12-3 without preparing a large amount of confirmation data for collation with each test data.

  Further, the confirmation data collated with the addition result of the test data is the value of the head address when the corresponding data ROMs 124-1 to 12-3 are correctly inserted. The top addresses of the data ROMs 124-1 to 12-3 are data that must be prepared for reading test data, and it is not necessary to prepare dedicated data as confirmation data. Further, based on the result of adding test data, when the correct data ROMs 124-1 to 124-3 are not inserted into the sockets at the correct positions, the data ROMs 124-1 to 124-4 inserted into the sockets are stored. It becomes possible to easily identify the socket to be originally inserted.

  For the notification of the result of the data check of the data ROMs 124-1 to 122, for the data ROMs 124-1 and 2 storing the image data, sound is output from the speakers 7L, 7R and 7U, and the sound data and lamp data are stored. The data ROM 124-3 to be notified is displayed by displaying an image on the liquid crystal display 4. For this reason, even if there is an error in the data ROM actually mounted in the socket subject to data check, there is no problem in informing the check result.

  In particular, by displaying an image on the liquid crystal display 4 to notify the result of the data check, the recognition becomes easy. Further, if it is possible to specify which of the data ROMs 124-1 to 3-3 is erroneously inserted into each socket as a result of the data check, this is also notified. It becomes easy to do.

  By the way, there are CPU 121, VDP125, ADP127, etc. in addition to the data ROMs 124-1 to 130-3, but the data originally stored in the data ROMs 124-1 to 1303 is used. Are VDP 125 and ADP 127, and the CPU 121 cannot directly read the data in the data ROMs 124-1 to 124-3. However, when performing a data check, the CPU 121 sends an instruction to the VDP 125 or ADP 127 so as to read the test data read by the attribute RAM 125a or the work RAM 127a. For this reason, the CPU 121 can read the test data stored in the data ROMs 124-1 to 124-3 even if not directly connected to the data ROMs 124-1 to 12.

  The present invention is not limited to the above-described embodiment, and various modifications and applications are possible. Hereinafter, (A) to (N) will be described as modifications of the above-described embodiment applicable to the present invention.

  (A) In the above-described embodiment, as an abnormality related to the data ROMs 124-1 to 124-1, the case where the data contents of the data ROMs 124-1 to 124-3 are incorrect is described as an example. However, the abnormality relating to the data ROMs 124-1 to 124-3 is not limited to this. For example, an abnormality in which the data ROM 124-1 to 3 is inserted into the socket in the wrong direction, each pin of the data ROM 124-1 to 3 is not properly fitted into the socket, or the pin is damaged An abnormality such that data cannot be read is also an abnormality relating to the data ROMs 124-1 to 124-3 of the present invention, and this abnormality is also subject to data check processing.

  For example, when the data ROMs 124-1 to 12-3 are inserted in the socket in the wrong direction or when test data that cannot be read is included, the total of the test data read in step S304 is X, Y in step S306. , Z so that the test data is stored in advance in the data ROMs 124-1 to 124-3. As a result, if the data ROMs 124-1 to 12-3 are inserted in the socket in the wrong direction, it is determined NO in step S306, and the data ROMs 124-1 to 3 are inserted in the socket in the wrong direction. Or an abnormality that there is test data that cannot be read from the data ROMs 124-1 to 12-3.

  Specifically, for example, if the data ROM 124-1 is inserted in the wrong direction at the mounting position where the data ROM 124-1 is to be mounted, in step S304 of the second loop in FIG. , Xc, Xd, X + a address, X + b address, X + c address, X + d address are determined so that Xa ′, Xb ′, Xc ′, Xd ′ are read out, and test data Xa ′, Xb ′, Xc ′. , Xd ′ (Xa ′ + Xb ′ + Xc ′ + Xd ′ is not X) is stored in the data ROM 124-1. Also, for example, if there is test data that cannot be read in step S304 of the second loop in FIG. 12, a value different from Xa, Xb, Xc, Xd is substituted for variable L in step S304. .

  (B) In the above embodiment, by receiving the data check command transmitted from the game control board 101 in the test mode, the CPU 121 of the effect control board 102 performs data check on the data ROMs 124-1 to 130-3. I was supposed to. On the other hand, by inputting a confirmation signal equivalent to the data check command from a dedicated tester or the like, the data check on the data ROMs 124-1 to 12-3 can be started. In this case, before the production control board 102 is assembled to the main body of the slot machine 1, the data check on the data ROMs 124-1 to 130-3 can be performed.

  (C) In the above embodiment, when it is determined that the data ROMs 124-1 to 13-3 are not inserted into the socket at the correct position as a result of the data check of the data ROMs 124-1 to 3 (the test data addition result is different from the start address X , Y, Z) and when the data content is determined to be incorrect (when the addition result of the test data does not become X, Y, Z), the liquid crystal display 4 or the speakers 7L, 7R, Notification from 7U was to be performed. However, the present invention is not limited to this.

  For example, even when the data ROMs 124-1 to 12-3 are inserted into the sockets at the correct positions and the contents of the data are determined to be correct, the fact is notified from the liquid crystal display 4 and the speakers 7L, 7R, and 7U. It may be a thing. Further, if the addition result of the test data does not coincide with the head address, it is possible to notify that all the data contents are not correct. Furthermore, after all the data ROMs 124-1 to 12-3 are checked for data, all the results may be notified.

  (D) In the above embodiment, the confirmation data is the value of the top address when the corresponding data ROMs 124-1 to 12-3 are correctly inserted, and no dedicated data is prepared as confirmation data. Then, the addition result of the test data is compared with the value of the head address (steps S301 to S306). However, dedicated comparison data may be prepared as confirmation data, and the data check process may be performed by comparing the comparison data with each test data. Further, if the data check process performed by comparing the comparison data with each test data is performed together with the data check process of the above-described embodiment, the data ROMs 124-1 to 13 are checked more accurately. be able to.

  (E) In the above embodiment, when the data ROMs 124-1 to 12-3 are correctly mounted, the start addresses of the data ROMs are X, Y, and Z, respectively, for confirmation that is collated with the calculation result of the test data. It was data. Further, since the data ROMs 124-1 and 12-4 store image data, and the data ROM 124-3 stores sound data and lamp data, the result of the data check is notified by sound and image, respectively. . On the other hand, the following can be performed by changing the structure of the data stored in the data ROMs 124-1 to 124-1.

  FIGS. 13A to 13C are diagrams showing modifications of the data stored in the data ROMs 124-1 to 124-1. The data ROMs 124-1 to 12-4 store confirmation data Xe, Ye, Ze at addresses X + e, Y + e, and Z + e, respectively, when they are inserted into sockets at the correct positions. A value obtained by adding the test data Xa, Xb, Xc, and Xd stored in the data ROM 124-1 is equal to the confirmation data Ye stored in the data ROM 124-2. A value obtained by adding the test data Ya, Yb, Yc, Yd stored in the data ROM 124-2 is equal to the confirmation data Ze stored in the data ROM 124-3. A value obtained by adding the test data Za, Zb, Zc, and Zd stored in the data ROM 124-3 is equal to the confirmation data Xe stored in the data ROM 124-1.

  For example, when performing data check on the data ROM 124-1, after obtaining the addition result of the test data Xa, Xb, Xc, Xd from the data ROM 124-1, the confirmation data Ye is read from the data ROM 124-2, The data check can be performed by checking the above. Similarly, for the data ROM 124-2, the confirmation data Ze is read from the data ROM 124-3, and for the data ROM 124-3, the confirmation data Xe is read from the data ROM 124-1.

  As a result, the data check can be performed using different confirmation data for the slot machines of different models without modifying the data check program. Since the confirmation data is different for each model, for example, even if a data ROM used for a different model is mounted at the correct position, it can be determined that the data content is incorrect. become.

  If the number of data ROMs to be mounted is smaller than the number of sockets provided on the effect control board 102, empty sockets are generated. If data is read from the address of an empty socket, both the test data and the confirmation data are 0, depending on the logic method. For example, if the position where the data ROM 124-2 is to be mounted is an empty socket, the total of the test data Xa, Xb, Xc, and Xd in the data ROM 124-1 may be set to zero.

  In FIG. 13, data ROMs 124-1 to 12-3 store NG display data from address X + f, address Y + f, and address Z + f when inserted into the socket at the correct positions. The NG display data is image data for enabling only the result of the data check to be displayed. For example, even if the data ROM 124-3 that originally stores the audio data / lamp data is inserted into the socket into which the data ROM 124-1 is to be inserted, when the address X + f is accessed, the image data for NG display is displayed. Can be read. Therefore, regardless of what kind of production (notification) the data stored in the data ROMs 124-1 to -12 is used for the image data for NG display, As shown in b), the data check result can be displayed on the liquid crystal display 4 for notification.

  (F) In the embodiment described above, all the data check processing is completed after exiting the first loop in step S301 'or after step S314. However, as indicated by a broken line in FIG. 12, the display confirmation processing in step S315 may be performed after step S301 'or step S314. FIGS. 14A to 14C are diagrams illustrating modifications of data stored in the data ROMs 124-1 to 12-3 when the display confirmation process is performed. FIG. 15 is an explanatory diagram for explaining an image displayed on the liquid crystal display 4 based on the data of FIG. FIG. 16 is a flowchart showing the display confirmation process.

  The data ROMs 124-1 to 12-3 shown in FIGS. 14A to 14C are X + g address, Y + g address, Z + g address, and X + h address, Y + h when inserted into the socket on the effect control board 102 at the correct position. From the address, Z + h address, left / right area data and middle area data are stored as test presentation data. The left / right area data is stored from the X + g address, the Y + g address, and the Z + g address when the data ROMs 124-1 to 12-3 are inserted at the correct positions. The middle area data is stored from address X + h, address Y + h and address Z + h when the data ROMs 124-1 to 12-3 are inserted at the correct positions.

  FIG. 15 is an explanatory diagram for explaining an image displayed on the liquid crystal display 4 based on the left / right region data and the middle region data. The left / right area data is data for displaying a predetermined image in the left area and the right area of the liquid crystal display 4, as shown in FIGS. 15 (a1), (a2), and (a3). . In the present embodiment, data for displaying a “red” band in the left area of the liquid crystal display 4 and a “blue” band in the right area of the liquid crystal display 4 are left and right area data. Stored from address X + g when the ROM 124-1 is inserted into the socket at the correct position, the image shown in FIG. 15A1 can be displayed by the left / right area data. The data for displaying the “green” band in the left area of the liquid crystal display 4 and the “blue” band in the right area of the liquid crystal display 4 is the left / right area data. Is stored from address Y + g when inserted at the correct position, and the image shown in FIG. 15 (a2) can be displayed by the left / right area data. The data for displaying the “blue” band in the left area of the liquid crystal display 4 and the “blue” band in the right area of the liquid crystal display 4 is the left / right area data. Is stored from address Z + g when inserted at the correct position, and the image shown in FIG. 15 (a3) can be displayed by the left and right area data.

  Further, the middle area data is data for displaying a predetermined image in the central area of the liquid crystal display 4 as shown in FIGS. 15 (b1), (b2), and (b3). In the present embodiment, data for displaying a “red” band in the central area of the liquid crystal display 4 is stored as the middle area data from address X + h when the ROM 124-1 is inserted into the socket at the correct position. Thus, the image shown in FIG. 15 (b1) can be displayed by the middle area data. Data for displaying a “green” band in the central area of the liquid crystal display 4 is stored as middle area data from address Y + h when the ROM 124-2 is inserted into the socket at the correct position. The image shown in FIG. 15B2 can be displayed by the data. Data for displaying a “blue” band in the central area of the liquid crystal display 4 is stored as middle area data from address Z + h when the ROM 124-3 is inserted into the socket at the correct position. The image shown in FIG. 15 (b3) can be displayed by the data.

  In the display confirmation process shown in FIG. 16, the CPU 121 reads test effect data from the X + g address and the Y + h address with respect to the VDP 125 (step S401), and displays the data on the liquid crystal display 4 based on the read data. A command is issued to execute a test effect (step S402). The VDP 125 causes the liquid crystal display 4 to execute a test effect based on this command. That is, the VDP 125 reads the test effect data at the address X + g (left / right area data) and the test effect data at the address Y + h (middle area data) into the attribute RAM 125a, and the read X + g address and the test effect at the address Y + h. The image data is synthesized and developed in the VRAM 126. Then, the image developed on the VRAM 126 is displayed on the liquid crystal display 4 so that the test effect is executed on the liquid crystal display 4.

  The test effect executed in this way differs depending on which of the data ROMs 124-1 to 12-3 is inserted in the socket. The mounting position of the correct socket corresponding to the liquid crystal display 4 on which the data ROM 124-1 is to be mounted is referred to as “mounting position 1”. The mounting position of the correct socket corresponding to the liquid crystal display 4 on which the data ROM 124-2 is to be mounted is referred to as “mounting position 2”. Depending on the relationship between “mounting position 1” and “mounting position 2” and the data ROMs 124-1 to 12-3 mounted therein, the images displayed on the liquid crystal display 4 in the test effect differ as follows.

  When the data ROM 124-1 and the data ROM 124-2 are mounted at correct positions, a normal image is displayed with a test effect. A normal image in the present embodiment is an image composed of bands arranged in the order of “red, green, and blue”. In other words, when the data ROM 124-1 is mounted at the “mounting position 1” and the data ROM 124-2 is mounted at the “mounting position 2”, the bands arranged in the order of “red, green and blue” as shown in FIG. 15 (a1b2). An image consisting of is displayed.

On the other hand, when the data ROMs 124-1 to 12-3 are not mounted at the correct positions, a normal image cannot be displayed as a test effect, and the images at the time of abnormality are shown in FIGS. Images shown in a2b1), (a2b2), (a2b3), (a3b1), (a3b2), (a3, b3) are displayed on the liquid crystal display 4.
When the data ROM 124-1 is mounted at "Mounting position 1" and the data ROM 124-1 is mounted at "Mounting position 2", as shown in FIG. 15 (a1b1), from the bands arranged in the order of "Red, Red and Blue" Will be displayed.
When the data ROM 124-1 is mounted at “Mounting position 1” and the data ROM 124-3 is mounted at “Mounting position 2”, as shown in FIG. 15 (a 1 b 3), it is composed of bands arranged in the order of “Red Blue Blue”. An image is displayed.

When the data ROM 124-2 is mounted at "Mounting position 1" and the data ROM 124-1 is mounted at "Mounting position 2", as shown in FIG. 15 (a2b1), from the bands arranged in the order of "green red blue" Will be displayed.
Similarly, depending on the mounting position of the data ROMs 124-1 to 124-3, as shown in FIGS. 15 (a 2 b 2), (a 2 b 3), (a 3 b 1), (a 3 b 2), (a 3, b 3), An image composed of bands arranged in the order of “green blue blue”, “blue red blue”, “blue green blue”, and “blue blue blue” is displayed.

  In the present embodiment, as described above, the band of the color displayed on the liquid crystal display 4 by the test effect depending on whether the data ROM 124-1 and the data ROM 124-2 are mounted at the correct positions or not. The order is different. Therefore, whether or not the data ROM 124-1 and the data ROM 124-2 are mounted at correct positions can be checked by looking at the display on the liquid crystal display 4. If the data ROMs 124-1 to 124-1 are not mounted at the correct positions, the color depends on which of the data ROMs 124-1 to 124-1 is mounted at “mounting position 1” or “mounting position 2”. Are displayed on the liquid crystal display 4 in a different order. For this reason, when the order of the color bands displayed on the liquid crystal display 4 in the test performance is viewed, any of the data ROMs 124-1 to 12-3 is erroneously mounted at “mounting position 1” and “mounting position 2”. Can be determined. For example, as shown in FIG. 15 (a2b1), if an image composed of bands arranged in the order of “green, red and blue” is displayed, the data ROM 124-2 is mistakenly displayed as “mounting position 2”. It can be determined that the data ROM 124-1 is erroneously installed. Furthermore, it is possible to confirm whether the color display of the liquid crystal display 4 is normally performed by giving a color to the image displayed on the liquid crystal display 4 in the test effect.

  By the way, the image displayed on the liquid crystal display 4 by the test effect is not limited to the above example. For example, a pattern image as shown in FIG. 17 can be displayed on the liquid crystal display 4 in a test effect. In the example shown in FIG. 17, the left and right region data for displaying the images shown in FIGS. 17A1, 17A2 and 17A3 in the ROMs 124-1 to ROM3, and FIGS. 17B1 and 17B2 are displayed. ), Middle region data for displaying the image shown in (b3) is stored in the same storage position as in the examples of FIGS. When the test effect is executed, when the data ROM 124-1 and the data ROM 124-2 are mounted at the correct positions, the image of the symbol shown in FIG. 17 (a1b2) in which the characters “PASS” are circled. Is displayed on the liquid crystal display 4 as a normal image. On the other hand, as in the case of FIG. 15 above, when the data ROMs 124-1 to 12-3 are not mounted at the correct positions, the images at the time of abnormality are shown in FIGS. 17 (a1b1), (a1b3), (a2b1), ( Images shown respectively in a2b2), (a2b3), (a3b1), (a3b2), (a3, b3) are displayed on the liquid crystal display 4. Also in the example of FIG. 17, if a color is given to the design or the background of the design, the same effect as in FIG. 15 can be obtained by performing the test effect.

  The above display confirmation process can be modified as follows. FIGS. 18A to 18C are diagrams illustrating modifications of data stored in the data ROMs 124-1 to 12-3 when the display confirmation process according to another embodiment is performed. In the above embodiment, two mounting positions of “mounting position 1” and “mounting position 2” are provided as mounting positions of the correct socket corresponding to the liquid crystal display 4. When three mounting positions are provided as correct socket mounting positions corresponding to the liquid crystal display 4, and three types of data ROMs 124-1 to 12-3 are mounted at the respective mounting positions, they are stored in the data ROMs 124-1 to 124-3. For example, the data may be modified as shown in FIG.

  The data ROMs 124-1 to 12-3 shown in FIGS. 18A to 18C are stored in the X + g address, the Y + g address, the Z + g address, the X + h address, and the Y + h address when inserted into the socket on the effect control board 102 at the correct positions. , Z + h address, X + i address, Y + i address, Z + i address, left area data, middle area data and right area data are stored as test effect data. The left area data is stored from address X + g, address Y + g, and address Z + g when data ROMs 124-1 to 12-3 are inserted at the correct positions. Further, the middle area data is stored from the X + h address, Y + h address, and Z + h address when the data ROMs 124-1 to 12-3 are inserted at the correct positions. The right area data is stored from address X + i, address Y + i, and address Z + i when the data ROMs 124-1 to 12-3 are inserted at the correct positions. In this case, test effect data is read from the X + g address, the Y + h address, and the Z + i address, and the test effect is displayed on the liquid crystal display 4 based on the read data.

  The display confirmation process described above is performed after step S301 'or step S314 in the data check process of FIG. 12, but may be performed before step S301. Further, only the display confirmation process can be performed in the data check process without performing the processes from step S301 to step S301 'and step S314.

  (G) In the above embodiment, the case where the data check of the data ROMs 124-1 to 12-4 for storing the image data or the sound data and the lamp data has been described, but the data check is similarly performed for the program ROM 123. be able to. This is because the program is only handled differently in the CPU 121, and the stored state is not different from image data or audio data at all. However, in order to prevent the test data from being read as a program according to the value of the program counter when the program is executed, it is only necessary to prevent the program of the same module from being stored across the address where the test data is stored.

  (H) In the above-described embodiment, the test data itself is stored at a specific address (address X + a, etc.) of the data ROMs 124-1 to 12. However, the test data is actually stored at the specific address. The stored address data may be stored. In this case, address data may be read from a specific address, and test data may be read according to the read address data. As a result, it is possible to prevent a piece of data (including a program) from being divided and stored or creating an empty area in the data ROMs 124-1 to 124-3 in order to avoid the division. Also in this case, even if the data contents of the data ROMs 124-1 to 12-3 mounted on the effect control board 102 differ depending on the model, it is necessary to change the program for performing the data check process. Absent.

  (I) In the embodiment described above, the CPU 121, the program ROM 123, the data ROMs 124-1 to 3, the VDP 125, the VRAM 126, and the ADP 127 are each configured and mounted on separate production chips on the effect control board 102. It was a thing. However, the configuration is arbitrary as long as at least the CPU 121 and the data check target ROM are mounted on separate chips. The program and data may be stored in the same ROM, or the program may be stored separately in a plurality of ROMs. Further, the VDP 125 and the ADP 127 may not be provided. In this case, the CPU 121 may be configured to read the test data directly from the ROM.

  (J) In the above embodiment, when the CPU 121 of the effect control board 102 receives the data check command from the CPU 111 of the game control board 101, the data of the data ROMs 124-1 to 12-3 is checked. On the other hand, a test board that is not used during normal operation may be connected to the effect control board 102, and a data check command may be transmitted from the test board to the effect control board 102. When the CPU 121 receives a data check command from the test board, the CPU 121 can check the data in the data ROMs 124-1 to 12-3 in the same manner. When the effect control board 102 and the test board have a slot for connecting a cable from the game control board 101, the cable from the test board is connected to the slot in a state where the game control board 101 is not connected. Thus, it may be connected.

  (K) In the above-described embodiment, the data ROMs 124-1 to 12-3 mounted on the production control board 102 are confirmed to be mounted in the respective sockets at the correct positions or whether the data contents are correct. On the other hand, the same can be done for the ROM chip mounted on the game control board 101. The present invention can also be applied to a case where a control circuit is formed on one board without dividing the game control board 101 and the effect control board 102.

  (L) In the above embodiment, the data ROMs 124-1 to 12-3 made of semiconductor chips are mounted on the effect control board 102 as data storage media. However, as long as the data storage location is managed and the test data can be stored in a specific storage location, a magnetic disk or an optical disk may be used. The specific storage location for storing the test data is specified by the address in the data ROMs 124-1 to 130-3. However, for example, in the case of a magnetic disk, it may be specified by a sector and a track.

  (M) In the above embodiment, the case where the present invention is applied has been described by taking a slot machine as an example. However, for a gaming machine such as a pachinko gaming machine, a ROM chip mounted on a substrate (or another type) In the same manner, it is possible to confirm whether or not the data storage medium is mounted in each socket at the correct position and whether the data content is correct.

  (N) In the above embodiment, the “command execution prohibited state” is configured to be canceled in step S107 or step S105 when the power is turned on. However, the timing for releasing the “test execution prohibited state” is not limited to this. A configuration in which the “command execution prohibited state” is canceled on condition that the power supply is cut off may be used. For example, when the power is shut off, the CPU 121 may clear the command execution prohibition flag to cancel the “command execution prohibition state”. Alternatively, in step S314, by setting a command execution prohibition flag to a storage area that is not backed up when the power is shut off, the situation where the command execution prohibition flag is set at the time of power shutoff is lost, and the “command execution prohibition state” is released. It may be configured.

  In addition, the “command execution prohibited state” may be canceled when it is confirmed that a specific command has been received. This specific command is, for example, a dedicated command for instructing to release the “command execution prohibited state” or a data check command. Furthermore, a predetermined time has elapsed since the “command execution prohibited state” was set in step S314, or notifications in steps S309, S310, S312 and S313 were performed, or the data check process was completed. The “command execution prohibited state” may be canceled on the condition that a predetermined time has elapsed since then. As the predetermined time in this case, a sufficiently long time is appropriately selected so that it is difficult to overlook the notification.

FIG. 3 is a front view showing the overall structure of the slot machine according to the embodiment of the present invention. FIG. 2 is a view showing an internal structure visually recognized with the front door of the slot machine of FIG. 1 opened. FIG. 2 is a view showing a structure on the back side of the front door of the slot machine of FIG. 1. FIG. 2 is a block diagram showing an overall configuration of a control circuit of the slot machine of FIG. 1. It is a figure which shows the circuit component and signal wiring which are mounted in the game control board and the production control board. It is a figure which shows the control part on an effect control board in detail. It is a figure which shows the structure of the data memorize | stored in the data ROM of FIG. It is a figure explaining reading of the test data from the data ROM of FIG. It is a figure which shows the aspect which alert | reports the data check result of the data ROM of FIG. It is a flowchart which shows the process at the time of power activation which CPU of an effect control board performs. (A) is a flowchart which shows the command reception standby process which CPU of an effect control board performs after the time of power activation, (b) is a flowchart which shows a control data check process. It is a flowchart which shows the data check process of FIG. 11 in detail. It is a figure which shows the modification of the structure of the data memorize | stored in the data ROM of FIG. It is a figure which shows the modification of the structure of the data memorize | stored in the data ROM of FIG. It is explanatory drawing explaining the image displayed on a liquid crystal display based on the data of FIG. 14 by test production. It is a flowchart which shows a display confirmation process. It is explanatory drawing explaining the modification of the image displayed on a liquid crystal display by test production. It is a figure which shows the modification of the structure of the data memorize | stored in the data ROM of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Slot machine 4 Liquid crystal display 7L, 7R, 7U Speaker 101 Game control board 102 Effect control board 121 CPU
124-1 to 124-3 Data ROM
125 VDP (video processor)
125a attribute RAM
126 VRAM
127 ADP (Audio Processor)
127a Work RAM

Claims (1)

A plurality of effect data storage media having the same or similar outer shape and different stored data are mounted on the substrate, and data stored in each effect data storage medium mounted on the substrate A game machine comprising: a control means for executing processing relating to a game using a game machine; and an effecting means for producing an effect according to the progress of the game,
Test effect data for performing the test effect of the effect means is distributed and stored in the plurality of effect data storage media,
The control means includes
A data reading means for reading test effect data from the plurality of effect data storage media by inputting a confirmation command signal for instructing execution of the test effect of the effect means to the control means from outside;
Test effect execution means for performing control for combining the test effect data read by the data reading means from all of the plurality of effect data storage media and executing the test effect by the effect means; A gaming machine characterized by

Images