JP4598955B2 - ２組の活性領域の間で共用されるゲート電極を有する半導体デバイス - Google Patents

２組の活性領域の間で共用されるゲート電極を有する半導体デバイス Download PDF

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Publication number
JP4598955B2
JP4598955B2 JP2000585933A JP2000585933A JP4598955B2 JP 4598955 B2 JP4598955 B2 JP 4598955B2 JP 2000585933 A JP2000585933 A JP 2000585933A JP 2000585933 A JP2000585933 A JP 2000585933A JP 4598955 B2 JP4598955 B2 JP 4598955B2
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Japan
Prior art keywords
substrate
gate electrode
active regions
semiconductor device
insulating layer
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Expired - Fee Related
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JP2000585933A
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English (en)
Japanese (ja)
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JP2002531949A (ja
JP2002531949A5 (enExample
Inventor
ガードナー，マーク・アイ
フルフォード，エイチ・ジム
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of JP2002531949A5 publication Critical patent/JP2002531949A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment

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  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
JP2000585933A 1998-12-01 1999-08-09 ２組の活性領域の間で共用されるゲート電極を有する半導体デバイス Expired - Fee Related JP4598955B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/201,995 US6177687B1 (en) 1998-12-01 1998-12-01 Semiconductor device having gate electrode shared between two sets of active regions and fabrication thereof
US09/201,995 1998-12-01
PCT/US1999/018038 WO2000033381A1 (en) 1998-12-01 1999-08-09 Semiconductor device having shared gate electrode and fabrication thereof

Publications (3)

Publication Number Publication Date
JP2002531949A JP2002531949A (ja) 2002-09-24
JP2002531949A5 JP2002531949A5 (enExample) 2006-08-31
JP4598955B2 true JP4598955B2 (ja) 2010-12-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000585933A Expired - Fee Related JP4598955B2 (ja) 1998-12-01 1999-08-09 ２組の活性領域の間で共用されるゲート電極を有する半導体デバイス

Country Status (6)

Country Link
US (1) US6177687B1 (enExample)
EP (1) EP1142018B1 (enExample)
JP (1) JP4598955B2 (enExample)
KR (1) KR100577447B1 (enExample)
DE (1) DE69939069D1 (enExample)
WO (1) WO2000033381A1 (enExample)

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1191970A (en) * 1982-11-09 1985-08-13 Abdalla A. Naem Stacked mos transistor
US4686758A (en) * 1984-06-27 1987-08-18 Honeywell Inc. Three-dimensional CMOS using selective epitaxial growth
JPS62155556A (ja) * 1985-12-27 1987-07-10 Nec Corp 半導体装置の製造方法
US4654121A (en) * 1986-02-27 1987-03-31 Ncr Corporation Fabrication process for aligned and stacked CMOS devices
JPH02117166A (ja) * 1988-10-27 1990-05-01 Ricoh Co Ltd 半導体装置
US5310696A (en) 1989-06-16 1994-05-10 Massachusetts Institute Of Technology Chemical method for the modification of a substrate surface to accomplish heteroepitaxial crystal growth
JPH03104158A (ja) * 1989-09-18 1991-05-01 Matsushita Electron Corp Ｃｍｏｓ型半導体装置
US5215932A (en) 1991-09-24 1993-06-01 Micron Technology, Inc. Self-aligned 3-dimensional PMOS devices without selective EPI
JPH0590517A (ja) * 1991-09-30 1993-04-09 Toshiba Corp 半導体装置及びその製造方法
WO1993009567A1 (en) * 1991-10-31 1993-05-13 Vlsi Technology, Inc. Auxiliary gate lightly doped drain (agldd) structure with dielectric sidewalls
US5324960A (en) * 1993-01-19 1994-06-28 Motorola, Inc. Dual-transistor structure and method of formation
JP2500924B2 (ja) * 1994-08-12 1996-05-29 株式会社東芝 半導体装置
JP3323381B2 (ja) * 1995-12-14 2002-09-09 三菱電機株式会社 半導体装置及びその製造方法
JP3081543B2 (ja) * 1996-03-29 2000-08-28 三洋電機株式会社 スプリットゲート型トランジスタ、スプリットゲート型トランジスタの製造方法、不揮発性半導体メモリ
US5882959A (en) * 1996-10-08 1999-03-16 Advanced Micro Devices, Inc. Multi-level transistor fabrication method having an inverted, upper level transistor which shares a gate conductor with a non-inverted, lower level transistor
US5770482A (en) * 1996-10-08 1998-06-23 Advanced Micro Devices, Inc. Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto
US5714394A (en) 1996-11-07 1998-02-03 Advanced Micro Devices, Inc. Method of making an ultra high density NAND gate using a stacked transistor arrangement
US5843816A (en) * 1997-07-28 1998-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated self-aligned butt contact process flow and structure for six transistor full complementary metal oxide semiconductor static random access memory cell
US5949092A (en) * 1997-08-01 1999-09-07 Advanced Micro Devices, Inc. Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in relation to interlayer insulator
KR100290899B1 (ko) * 1998-02-06 2001-06-01 김영환 반도체소자및이의제조방법

Also Published As

Publication number Publication date
DE69939069D1 (de) 2008-08-21
KR100577447B1 (ko) 2006-05-10
EP1142018B1 (en) 2008-07-09
KR20010081049A (ko) 2001-08-25
US6177687B1 (en) 2001-01-23
EP1142018A1 (en) 2001-10-10
JP2002531949A (ja) 2002-09-24
WO2000033381A1 (en) 2000-06-08

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