|
CA1191970A
(en)
*
|
1982-11-09 |
1985-08-13 |
Abdalla A. Naem |
Stacked mos transistor
|
|
US4686758A
(en)
*
|
1984-06-27 |
1987-08-18 |
Honeywell Inc. |
Three-dimensional CMOS using selective epitaxial growth
|
|
JPS62155556A
(ja)
*
|
1985-12-27 |
1987-07-10 |
Nec Corp |
半導体装置の製造方法
|
|
US4654121A
(en)
*
|
1986-02-27 |
1987-03-31 |
Ncr Corporation |
Fabrication process for aligned and stacked CMOS devices
|
|
JPH02117166A
(ja)
*
|
1988-10-27 |
1990-05-01 |
Ricoh Co Ltd |
半導体装置
|
|
US5310696A
(en)
|
1989-06-16 |
1994-05-10 |
Massachusetts Institute Of Technology |
Chemical method for the modification of a substrate surface to accomplish heteroepitaxial crystal growth
|
|
JPH03104158A
(ja)
*
|
1989-09-18 |
1991-05-01 |
Matsushita Electron Corp |
Ｃｍｏｓ型半導体装置
|
|
US5215932A
(en)
|
1991-09-24 |
1993-06-01 |
Micron Technology, Inc. |
Self-aligned 3-dimensional PMOS devices without selective EPI
|
|
JPH0590517A
(ja)
*
|
1991-09-30 |
1993-04-09 |
Toshiba Corp |
半導体装置及びその製造方法
|
|
WO1993009567A1
(en)
*
|
1991-10-31 |
1993-05-13 |
Vlsi Technology, Inc. |
Auxiliary gate lightly doped drain (agldd) structure with dielectric sidewalls
|
|
US5324960A
(en)
*
|
1993-01-19 |
1994-06-28 |
Motorola, Inc. |
Dual-transistor structure and method of formation
|
|
JP2500924B2
(ja)
*
|
1994-08-12 |
1996-05-29 |
株式会社東芝 |
半導体装置
|
|
JP3323381B2
(ja)
*
|
1995-12-14 |
2002-09-09 |
三菱電機株式会社 |
半導体装置及びその製造方法
|
|
JP3081543B2
(ja)
*
|
1996-03-29 |
2000-08-28 |
三洋電機株式会社 |
スプリットゲート型トランジスタ、スプリットゲート型トランジスタの製造方法、不揮発性半導体メモリ
|
|
US5882959A
(en)
*
|
1996-10-08 |
1999-03-16 |
Advanced Micro Devices, Inc. |
Multi-level transistor fabrication method having an inverted, upper level transistor which shares a gate conductor with a non-inverted, lower level transistor
|
|
US5770482A
(en)
*
|
1996-10-08 |
1998-06-23 |
Advanced Micro Devices, Inc. |
Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto
|
|
US5714394A
(en)
|
1996-11-07 |
1998-02-03 |
Advanced Micro Devices, Inc. |
Method of making an ultra high density NAND gate using a stacked transistor arrangement
|
|
US5843816A
(en)
*
|
1997-07-28 |
1998-12-01 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Integrated self-aligned butt contact process flow and structure for six transistor full complementary metal oxide semiconductor static random access memory cell
|
|
US5949092A
(en)
*
|
1997-08-01 |
1999-09-07 |
Advanced Micro Devices, Inc. |
Ultra-high-density pass gate using dual stacked transistors having a gate structure with planarized upper surface in relation to interlayer insulator
|
|
KR100290899B1
(ko)
*
|
1998-02-06 |
2001-06-01 |
김영환 |
반도체소자및이의제조방법
|