JP4587337B2 - Bullet ball machine - Google Patents

Description

  The present invention relates to a gaming machine, and more particularly, to a bullet ball gaming machine including at least a main control board that controls the progress of a game and a prize ball control board that executes payout of prize balls when a prize is awarded.

  A gaming machine, such as a pachinko gaming machine, is configured to pay out a predetermined number of gaming balls as prize balls when the launched gaming balls win a prize opening. The game balls won at each prize opening on the game board are temporarily stopped in a safe ball tank, and the stopped game balls are detected one by one by a sensor, and a predetermined number of prize balls are driven by a motor or the like. After paying out to the player by the device, the detected game ball is discharged from the safe ball tank. In this conventional pachinko machine, the winning game balls are stopped in the safe ball tank, and the prize balls are discharged out of the machine after paying out the prize balls, so that even if an unexpected situation such as a power failure occurs, the winning game balls are safe Since it was stopped in the ball tank, it had the effect of not giving a disadvantage to the player.

However, the conventional pachinko gaming machine has the following problems.
(1) The configuration is bulky and complicated because it is necessary to provide a safe ball tank.
(2) When a power outage or the like occurs, the data on the number of premium balls to be paid out disappears, so the maximum number of premium balls is paid out, and the correct premium ball is not paid out. For example, even if 5 or 10 premium balls are to be paid out for one winning ball, 15 premium balls are paid out.

  In order to solve these problems, in recent years, a prize payout control board for paying out a prize ball is provided, and data corresponding to the number of prizes to be paid out is stored in a memory of the prize payout board, and this memory is backed up by a battery. Proposals have been made. As the invention related to the proposal, the applicant of the present invention has made an invention shown in “Ball Ball Game Machine” of Japanese Patent Application No. 10-126693. This proposal has the excellent effect that the mechanism of the pachinko machine can be simplified and an accurate prize ball can be paid out.

However, in the pachinko gaming machine equipped with the prize payout board described above, the following problems can be considered.
(1) When winning a prize at each winning opening at the same time, the winning balls may not be paid out in order. For example, when winnings are made consecutively or almost at the same time as the winning holes for five award balls, the winning holes for ten award balls and the winning holes for fifteen balls, the winning balls are not paid out in the order of winning. There was a problem that there was something.
(2) Further, when winning continuously, there was a problem that the payout was not made in time and the number of memorized winnings increased, and it was unclear from which memory to pay.
(3) Due to the problem described in (1) or (2) above, there was a problem that the player may have distrust.
The bullet ball game machine of the present invention is made for the purpose of suitably solving these problems and providing a healthier game machine.

Means and effects for solving the problems

In order to solve the above-mentioned problem, the ball game machine according to claim 1,
A main control board that controls the progress of the game due to the behavior of the game balls launched on the game board surface;
A prize ball payout control board for paying out a prize ball to a player;
A power supply board for supplying power to the main control board and the prize ball payout control board;
In a ball game machine including
A game ball detecting means for detecting a winning of a game ball launched on the game board surface on the main control board, and when the game ball detecting means detects that there is a winning, the winning ball payout in the order of detection Data output means for outputting data for transmission related to the number of prize balls to the control board, and data erasure means for erasing data output by the data output means,
Upon receiving the data output by the data output means on the prize ball payout control board, unpaid data adding means for adding to the unpaid data, and paying out the prize ball according to the added unpaid data An unpaid data subtracting means for subtracting from the unpaid data when it is detected that the payout has been made,
The main control board (30) is equipped with a one-chip microcomputer (61) with a built-in RAM,
The main control board (30) is supplied with 12V power from the power board (55),
The main control board (30) generates a 5V power source for driving the one-chip microcomputer (61) from the supplied 12V power source,
The main control board (30) has a reset circuit (60) connected to a reset terminal (* RES) of the one-chip microcomputer (61),
In the reset circuit (60), the power supply obtained by dividing the 12V power supply is input to the input terminal (VSB), the 5V power supply is input to the power supply terminal (VCC), and the output terminal (RESET) is pulled by the 5V power supply. Up,
The reset circuit (60) sets the reset terminal (* RES) of the one-chip microcomputer (61) to low level when the 12V power supply rises, and then sets the reset terminal (* RES) to high level by the 5V power supply. ,
It is characterized by that.

The bullet ball game machine according to claim 1 has an effect that the winning balls can be paid out in the order of winning.
In the ball game machine according to the first aspect, the one-chip microcomputer of the main control board can be reset by the rising of the 12V power supply supplied from the power supply board.

It is an external appearance perspective view which shows the pachinko machine 10 which employ | adopted this invention. It is the back view which looked at the pachinko machine 10 from the back. 3 is a front view showing a configuration of a game board 22 of the pachinko machine 10. FIG. 2 is a block diagram showing an electrical configuration of a pachinko machine 10. FIG. 3 is a block diagram showing a configuration for supplying power from a power supply board 55. FIG. 3 is a circuit diagram showing a configuration of a voltage monitoring circuit 60 of a main control board 30. FIG. 3 is a circuit diagram showing configurations of a voltage monitoring circuit 62 and a backup voltage monitoring circuit 64 of a prize ball control board 31. FIG. It is a timing chart which shows the operation state of CPU61 of the main control board 30 at the time of power activation, and CPU of each sub control board. 4 is a timing chart showing operation states of the CPU 61 of the main control board 30 and the CPUs of the sub control boards at the time of power-on / off. It is a flowchart which shows the process of a "winning memory | storage routine". It is a memory map which shows the memory area which memorize | stores the order of winning a prize. It is a flowchart which shows the process of a "winning transmission routine". It is a flowchart which shows the process of a "reception data storage routine". It is a flowchart which shows the process of the "reception data storage routine" of the 2nd specific example. It is a flowchart which shows the process of "prize ball payout routine". It is a flowchart which shows the process in "over winning ball payout process".

  Preferred embodiments of the present invention will be described below with reference to the drawings. The embodiments of the present invention are not limited to the following specific examples, and it goes without saying that various forms can be adopted as long as they belong to the technical scope of the present invention. As shown in FIG. 1, the pachinko machine 10 of this specific example includes a rectangular outer frame 11 and a front frame 12. .) 13 is provided. The front frame 12 is rotatably attached to the outer frame 11 by hinges 14 at the upper and lower left ends. An upper plate 15 is provided below the front frame 12, and a lending button 16, a settlement button 17 and a balance display unit 18 are provided on the upper plate 15. When a prepaid card is inserted into the card slot 19 of the card reader 13, the stored balance is displayed on the balance display unit 18, and when the lending button 16 is pressed, the game balls are lent out and the game balls are drawn from the payout opening of the upper plate 15. Discharged.

  A window-shaped metal frame 20 is removably attached to the front frame 12 with respect to the front frame 12. A plate glass 21 is double fitted into the metal frame 20. A game board 22 is stored behind the plate glass 21. A lower plate 23 is provided at the lower part of the front frame 12 of the upper plate 15, and a firing handle 24 is attached to the right side of the lower plate 23. A rotation ring (not shown) is held on the outer periphery of the launch handle 24, and the game ball can be launched onto the game board 22 by rotating clockwise. The upper plate 15 and the lower plate 23 are connected to each other, and are configured to guide the game ball to the lower plate 23 when the upper plate 15 is full of game balls.

  FIG. 2 is a back view of the pachinko machine 10 viewed from the back side. As shown in the drawing, a mechanism board 26 to which the above-described game board 22 is detachably attached is housed in the above-described outer frame 11. The mechanism panel 26 is provided with a ball tank 27, a guide rod 28, and a payout device 29 from above. With this configuration, if there is a winning game ball at the winning opening on the game board 22, a predetermined number of gaming balls can be discharged from the ball tank 27 to the above-described upper plate 15 through the guide rod 28 by the payout device 29. . In addition, the main control board 30 and the prize ball control board 31 can be attached to and detached from the mechanism board 26, a special symbol display device 32 is provided on the game board 22, a launch control board 33 is provided on the lower left part of the front frame, and a special symbol display device is provided. External connection terminal boards 50 are respectively attached to the left side of 32. It should be noted that the structure related to the payout of game balls with the mechanism panel 26 as the center is the same as the conventional structure, and the detailed description thereof is omitted.

  Next, the game board 22 will be described with reference to FIG. As shown in FIG. 3, the game board 22 has an LCD panel unit (hereinafter referred to as “LCD”) 32a constituting a special symbol display device 32 at the center, and a normal electric accessory serving as a first type starting port at the lower part thereof. 36, the normal symbol display device 37 on the upper part of the LCD 32a, the normal symbol operation gates 38 and 39 on the left and right of the LCD 32a used for starting the variation of the symbol displayed on the normal symbol display device 37, and the big winning opening 40 on the lower part of the ordinary electric accessory 36. Further, an out port 41 at the bottom of the board surface, other various winning ports, a windmill, a game nail (not shown), and the like are provided. With this configuration, when the above-described launch handle 24 is rotated, the launch motor 33a driven by the launch control board 33 is driven, and the game ball on the upper plate 15 is launched onto the game board 22 via the guide rail. . If the launched game ball wins each winning hole, the game ball is taken into the back of the board as a safe ball, and if not won, it is taken into the back of the board through the out port 41 as well.

  Next, the electrical configuration of the pachinko machine 10 described above will be described with reference to the block diagram of FIG. As shown in the figure, the electric circuit of the pachinko machine 10 includes the main control board 30, the prize ball control board 31, the special symbol display device 32, the launch control board 33, the lamp control board 34, the sound control board 35, and the like. ing. In this circuit diagram, a so-called relay board for transferring signals is not described.

  The main control board 30 is configured as a logic operation circuit centered on an 8-bit one-chip microcomputer incorporating a ROM that stores a game control program and a RAM that serves as a work area for operations and the like. An external input / output circuit for inputting / outputting with various actuators is also provided. On the input side of the main control board 30, there are a first type start port switch 36a, normal symbol operation switches 38a and 39a, an accessory continuous operation switch (hereinafter simply referred to as "V switch") 40a, a count switch 40b, a full tank A switch 43, a supply switch 44, a plurality of other prize opening switches 52, and the like are connected. On the output side, a special prize opening solenoid 40c, a V solenoid 40d, a normal accessory solenoid 36b, an external connection terminal board 50, and the like are connected.

  The first type start port switch 36a is in the above-described normal electric accessory 36 on the game board 22, the normal symbol operation switches 38a and 39a are in the normal symbol operation gates 38 and 39, respectively, and the V switch 40a is in the big prize opening 40. Within a specific area, the count switch 40b is also in the big prize opening 40, the full tank switch 43 is in the lower pan 23, the replenishment switch 44 is in the ball tank 27, and the other prize opening switches 52 are the ordinary electric accessory 36 and the big prize opening. It is attached to each winning opening on the board other than 40. Here, the V switch 40a wins the prize winning opening 40 when the game ball that has won the prize winning opening 40 has passed the special device operating area (hereinafter referred to as "special area"). For all game balls, the full tank switch 43 indicates that the game ball is full in the lower plate 23, the supply switch 44 indicates that there is a game ball in the ball tank 27, and the other prize opening switch 52. Is for detecting that a game ball has won a prize on each of the winning holes on the board other than the ordinary electric accessory 36 and the big winning hole 40. Further, the large winning opening solenoid 40c connected to the output side is used for the large winning opening 40, the V solenoid 40d is used for a special area in the large winning opening 40, and the ordinary accessory solenoid 36b is used for opening and closing the ordinary electric accessory 36, respectively. Is.

  The special symbol display device 32 includes the LCD 32a described above, a symbol display device control board (hereinafter simply referred to as “design control board” (hereinafter also referred to as “image control board”)) 32b, a backlight, It is composed of an accessory unit 32c such as an inverter board. Similar to the main control board 30 described above, the symbol control board 32b is configured as a logic operation circuit centered on an 8-bit one-chip microcomputer.

  The prize ball control board 31 pays out a game ball as a prize ball to the player when a winning is obtained by driving and controlling the ball cutting motor 29b in accordance with a command command from the main control board 30, and the prepaid card unit described above. 13 and the CR adjustment display substrate 42 and the like are also controlled, and are configured as a logical operation circuit using a microcomputer. The CR adjustment display board 42 includes the lending button 16, the adjustment button 17, and the balance display portion 18 of the upper plate 15 described above. A prize ball payout switch 29 a is connected to the input side of the prize ball control board 31. The prize ball payout switch 29a is provided below the ball cutting motor 29b in the payout device 29, and detects a game ball paid out by the ball cutting motor 29b.

  The launch control board 33 drives and controls the launch motor 33a in accordance with the amount of rotation of the launch handle 24 operated by the player. When the player presses the launch stop switch 24b, the launch control board 33 stops firing or launches. This is for turning on the touch lamp 45 when the touch switch 24a built in the handle 24 is in the ON state. The touch switch 24 a is built in the firing handle 24 and detects that the player is touching the firing handle 24.

  The lamp control board 34 is mainly composed of driving elements such as transistors. Upon receiving a command from the main control board 30, the lamp control board 34 receives a normal symbol display device 37, lamps such as jackpot lamps and error lamps, and various lamps such as LEDs. It is intended to light up the display.

  The sound control board 35 includes a sound source IC, an amplifier, and the like, and is used to drive and control the speaker 46 in response to a command from the main control board 30.

  A circuit for one-way communication so that the transmission to the special symbol display device 32, the prize ball control board 31, the launch control board 33, the lamp control board 34, and the sound control board 35 can be transmitted only from the main control board 30. It is configured as. This one-way communication configuration can be implemented using an inverter circuit or a latch circuit.

  As shown in FIG. 5, various power sources are supplied to the main control board 30, the prize ball control board 31, the symbol control board 32b, the launch control board 33, the lamp control board 34, the sound control board 35, and the like. Has been. The power supply circuit 55 is configured to generate a backup power supply of DC5V from a 24V AC power supply using DC32V, DC12V, and a capacitor. Each board such as the main control board 30, the prize ball control board 31, and the symbol control board 32b generates DC 5V for driving the IC from the supplied DC 12V power source.

  Here, as shown in the figure, the DC 12 V power supplied from the power circuit 55 is connected to the reset (RES) terminal of the CPU 61 via the voltage monitoring circuit 60 of the main control board 30. Similarly, the DC12V power supplied from the power supply circuit 55 is connected to the reset (XRES) terminal of the CPU 63 via the voltage monitoring circuit 62 of the prize ball control board 31, and the XNMI terminal of the CPU 63 via the backup voltage monitoring circuit 64. It is connected to the. The 5V backup power supply of the power supply circuit is connected to the backup terminal (VBB) of the CPU 63. Similarly, DC12V power supplied from the power supply circuit 55 is connected to the reset (RES) terminal of the CPU 66 via the voltage monitoring circuit 65 of the symbol control board 32b.

  As shown in FIG. 6, the voltage monitoring circuit 60 of the main control board 30 includes a voltage monitoring IC 11, resistors R17, R18 and R19, a bypass capacitor C10, and the like. The VSB terminal that is the input terminal of the voltage monitoring IC 11 is supplied with a DC12V power source divided by the resistors R17 and R18, and the RESET terminal that is the output terminal is pulled up to DC5V by the resistor R19. It is connected to the RES terminal which is an input terminal of the CPU 61. Although not shown, the voltage monitoring circuit 65 has the same configuration as the voltage monitoring circuit 60.

  As shown in FIG. 7, the voltage monitoring circuit 62 of the prize ball control board 31 includes a voltage monitoring IC 8, resistors R38, R39 and R40, bypass capacitors C22 and C23, and the like. The VS terminal that is the input terminal of the voltage monitoring IC 8 is supplied with a DC12V power source divided by the resistors R39 and R40, and the RESET terminal that is the output terminal is pulled up to DC5V by the resistor R38. The CPU 63 is connected to an XRES terminal that is an input terminal.

  The backup voltage monitoring circuit 64 includes a comparator IC1A, resistors R41 to R45, and the like. The negative input terminal of the comparator IC1A is supplied with a DC5V power source divided by resistors R43 and R44, and the positive input terminal is supplied with a DC12V power source divided by resistors R41 and R42 for output. The terminal is pulled up to DC5V by a resistor R45 and is connected to an XNMI terminal which is an input terminal of the CPU 63.

  With the above-described configuration, the operation start state of each CPU of the main control board 30 when the power is supplied to the pachinko machine 10 and the sub-control boards other than the main control board such as the prize ball control board 31 and the symbol control board 32b Will be described according to the timing chart shown in FIG. When the pachinko machine 10 is powered on, the power board 55 generates DC 32V, DC 12V, and DC 5V, which is a battery backup power source (VBB). The generated DC 12V power is supplied to each control board as shown in FIG.

  Here, as shown in FIG. 8, when the power is turned on (point P1), the voltage of the DC12V power supply gradually rises from 0V to 12V in a parabolic manner. When the voltage of the DC12V power supply that gradually rises to the reference value LV2, the outputs of the voltage monitoring circuit 62 of the winning ball control board 31 and the voltage monitoring circuit 65 of the symbol control board 32b change from low level to high level, and the reset of the CPU 63 is released, and the CPU 63 Starts the security check operation (point P2). When the power supply voltage of DC12V is the reference value LV2, the output of the voltage monitoring circuit 60 of the main control board 30 maintains a low level state. When the power supply voltage of DC12V rises from the reference value LV2 to the reference value LV1, the output of the voltage monitoring circuit 60 changes from the low level to the high level, the reset of the CPU 61 is released, and the CPU 61 starts the security check operation (point P3).

  The security check time T1 of the CPU 61 of the main control board 30 is designed to be equal to or longer than the security check time T2 of each CPU of the sub control boards such as the CPU 63 of the prize ball control board 31 and the CPU 66 of the symbol control board 32b. Has been. As is well known, the security check is a function for checking whether or not the contents of the ROM in which the CPU 61, 63 and 66, which are one-chip microcomputers, have written the progress of the game, are legitimate.

  The security check time T1 of the main control board 30 is equal to or longer than the security check time T2 of the sub-control board, and the security check operation of the CPU 61 of the main control board 30 is executed later than the security check operation of the sub-control board. Thus, when the CPU 61 of the main control board 30 starts executing the game control according to the program written in the ROM, each CPU of the sub-control board has already executed the game control. As a result, even if the CPU 61 of the main control board 30 transmits data to each sub-control board immediately after the power is turned on, each sub-control board is executing the original control, so that the data can be reliably received. . In this specific example, the security check time T1 is about 439 ms, and the time from when the CPU 61 of the main control board 30 executes power supply to the game control is about 529 ms to 549 ms. The security check time T2 is about 200 ms, and the time from when the CPU 63 of the prize ball control board 31 which is one of the sub-control boards is turned on to control the game is about 202 ms to 203 ms.

  Next, the operation when the power supply to the pachinko machine 10 is cut off will be described according to the timing chart shown in FIG. When the power supply to the pachinko machine 10 is interrupted (point P6), the DC12V power supply voltage decreases substantially linearly after that, but then decreases substantially linearly and reaches 0V after a predetermined time. When the reference voltage LV1 is reached (point P7) in the course of gradually decreasing linearly (point P7), the output voltage of the voltage monitoring circuit 60 of the main control board 30 changes from high level to low level, and the CPU 61 is reset. Thereafter, as the time elapses, the power supply voltage of DC12V gradually decreases and reaches the reference voltage LV3 (point P8), and the output voltage of the backup voltage monitoring circuit 64 of the prize ball control board 31 changes from the high level to the low level. As a result, the XNMI terminal of the CPU 63 of the prize ball control board 31 becomes low level, and a non-maskable interrupt is applied to the CPU 63.

  When the power supply voltage of DC12V further decreases from the reference voltage LV3 and reaches the reference voltage LV2 (point P9), each sub-control board such as the voltage monitoring circuit 62 of the prize ball control board 31 and the voltage monitoring circuit 65 of the symbol control board 32b. The output voltage of the voltage monitoring circuit changes from high level to low level. As a result, the CPU of each sub control board is brought into a reset state. Here, the RAM of the winning ball control board 31 is backed up by a battery, and the data stored in the RAM is retained for a predetermined time (in this example, about 1 hour 20 minutes to about 3 hours 30 minutes) even when the power is turned off. The Incidentally, as described above, the XNMI terminal is made valid before the CPU 63 of the prize ball control board 31 is reset. As a result, the CPU 63 prohibits writing by prohibiting access to the RAM. Accordingly, the contents of the RAM in an unstable state that is in the reset state are not backed up by the battery, but the contents of the stable RAM before the reset can be backed up by the battery.

As described above, when the power is turned off, the CPU 61 of the main control board 30 is first set to the reset state, and then each CPU of the sub control board is set to the reset state. Thereby, there is an effect that each sub control board receives the data transmitted before the CPU 61 of the main control board 30 is turned off. In this specific example, the reference voltage LV1 is 9.39V to 10.21V, the reference voltage LV3 is 8.00V to 9.23V, and the reference voltage LV2 is designed to be 7.20V to 7.75V. Has been.

  The operation of this example having the above configuration will be described with reference to FIGS. When the processing executed by the CPU 61 of the main control board 30 shifts to the “winning storage routine” shown in FIG. 10, it is first determined whether or not there is a winning (step S100). In this specific example, the ordinary electric accessory 36 serving as a starting port is configured as a winning port for five winning balls, the large winning port 40 is configured as 15 winning balls, and the other winning ports are configured as ten winning balls. It is detected by the first-type start opening switch 36a that has won the ordinary electric accessory 36, the count switch 40b that has won the big winning opening 40, and the other winning opening switch 52 that has won the other winning openings. If an affirmative determination is made that there is a winning (step S100), the value of the unpaid winning number MMN is incremented (+1) (step S110), and then the winning order storing process is executed (step S120). Return to return. If a negative determination is made in step S110, the process returns.

  In the winning order storing process (step S120), as shown in the memory map of FIG. 11, the data for determining the number of winning balls using a 2-bit memory for a single winning on the 20-byte memory space is the data for winning a prize. Written in order. In this specific example, 01 (H) is awarded for a winning opening of five prize balls, 10 (H) is awarded for a winning opening of 10 prize balls, and 11 ( H) data is written. In this specific example, if 2 bits from the least significant bit are used in the order in which a winning is detected, data representing the number of winning balls for 4 winnings is written in 1 byte, and 1 byte memory is used. Are written in the memory of the next higher address. Which position in the memory space is to be written can be determined based on the incremented unpaid prize number MMN.

  When winning data is stored by the “winning storage routine”, a “winning transmission routine” shown in FIG. 12 is executed. The “winning storage routine” shown in FIG. 10 and the “winning transmission routine” shown in FIG. 12 are periodically executed by a hardware interrupt. In the “winning transmission routine” shown in FIG. 12, it is first determined whether or not the value of the unpaid winning number MMN is zero (step S150). If the value of the unpaid prize MMM is not zero, a winning transmission process is executed (step S160). In this specific example, the 1-byte data of the address A000 (H) is transmitted as it is, that is, the data of the number of prize balls for four winnings is transmitted to the symbol control board 32b at a time. For example, even if the value of the unpaid prize MMM is 3 or less and 1 or more, 1-byte data is transmitted as it is. When the winning transmission process is executed, the value 4 is subtracted from the value of the unpaid prize number MMN (step S170), and it is determined whether or not the value of the unpaid prize number MMN subjected to the subtraction process is equal to or less than zero. (Step S180). If a negative determination is made that it is not less than zero, a storage update process is executed (step S190), and the process returns to the return.

  The storage update process (step S190) is a process of repeatedly executing a process of copying 1-byte data with an address of 1 above to an address with an address of 1 up to an address where no data is written. Specifically, the data at address A001 (H) is at address A000 (H), the data at address A002 (H) is at address A001 (H), and the data at address A003 (H) is at address A002 (H). This is a process of copying one byte at a time, and repeatedly executing up to an address where data is not written. On the other hand, if an affirmative determination is made in step S180 that the value of the unpaid prize number MMN is zero or less, the value of the unpaid prize number MMN is cleared to zero (step S200), and addresses A000 (H) to A013. A process of clearing the memory up to (H) (step S210) is executed, and the process returns to return. If a negative determination is made in step S150, the process returns.

  In this specific example, the winning transmission process (step S160) is configured to transmit 1-byte data by a single process, but the first and second bits which are the least significant bits of the address A000 (H). The eye data may be transmitted by a single process. In the case of this configuration, the value of the unpaid prize MMM is decremented (−1) after the transmission process, and the storage update process shifts the data to the right by 2 bits, and the 7th bit and the most significant bit, 8 bits In the eye, the data of the first bit and the second bit which are one address higher are copied.

  When the CPU 63 of the winning ball control board 31 determines that there is a transmission of winning data from the main control board 30 (step S250 (FIG. 13 “Received Data Storage Routine”)), a process of adding the unpaid winning prize number ZMN is performed. Execute (step S260). In the addition process in step S260, if the transmitted 1-byte data is data representing the number of winnings for each of the four winnings, the number of unpaid winnings ZMN is +4, and the number of winnings for each of the three winnings is calculated. In the case of the data shown, the number of unpaid winnings ZMN is +3, and in the case of data representing the number of winnings for each of two winnings, the amount of unpaid winnings ZMN is +2, and the number of winnings for each winning is shown. In the case of data, this is a process of adding +1 to the unpaid prize number ZMN. When the unpaid prize amount ZMN is added (step S260), it is determined whether or not the unpaid prize number ZMN is memory over (step S270). In this specific example, the memory for storing the number of winnings is a 20-byte memory, like the memory for storing the winnings of the main control board 30 shown in FIG. 01 (H), 10 (H) winning ball numbers are 10 (H), and 15 winning ball number is 11 (H). Therefore, each 20-byte memory can store the number of winning balls for each of 80 gaming balls.

  If it is determined that the memory is not over, a winning order storing process is executed (step S280). This process is a process of writing the number of winning balls corresponding to the winning in the memory, similar to the process of step S120 performed on the main control board 30, and is an unpaid value obtained by adding 1 to the unpaid winning number ZMN before being added. 01 (H), 10 (H), or 11 (H) data in the memory space corresponding to the unpaid winning number ZMN obtained by adding the winning numbers 1 to 4 transmitted from the memory space corresponding to the winning number ZMN. Is written. Note that it is possible to determine whether the number of winnings is 1 to 4 based on the transmitted 1-byte data by 00 (H) from the most significant bit to which bit. If 1 to 4 winning numbers represented in the 1-byte data transmitted in step S270 correspond to memory over, the corresponding winning number is added to obtain a new over winning number OMN. The process is executed (step S290), and the process returns to return.

  When the process of step S280 and / or step S290 is executed, the addition process of the number of prize balls M5D, MAD, and MED is executed (step S300), and the process returns to return. If a negative determination is made in step S250, the process returns. This process increments (+1) the number of winning balls M5D if there is 01 (H) data in the transmitted 1-byte data, and increments the number of winning balls MAD if there is 10 (H) data. , 11 (H), there is a process for incrementing the number of prize balls MED. By executing each process of the “reception data storage routine” shown in FIG. 13, the number of winning prizes for the 15 prize balls to be paid out is the number of prize balls MED, the number of winning prizes is the number of prize balls MAD, 5 The number of winning balls is stored as the number of winning balls M5D, and the order of winning for the 80 winning balls to be paid out is stored in the memories A000 to A013 (H).

  Here, when the configuration is such that 2-bit data, that is, data for one winning is transmitted by one transmission process, each process (steps S310 to S390) of the “reception data storage routine” shown in FIG. ), The number of prizes for 15 prize balls to be paid out is memorized as the number of prize balls MED, the number of prizes for 10 prize balls is memorized as the number of prize balls MAD, and the number of prizes of 5 prize balls is memorized as the number of prize balls M5D. In addition, the winning order for the 80 winning balls to be paid out may be stored in the memory at addresses A000 (H) to A013 (H). That is, as in FIG. 13, when it is determined in step S310 that there is a transmission of winning data from the main control board 30 (step S310), a process of adding the unpaid winning number ZMN is executed (step S320). If the unpaid winning number ZMN is not over memory (step S330: YES), the winning order storing process (step S340) is performed. If the unpaid winning number ZMN is over memory (step S330: NO), the corresponding A process of adding the number of winning prizes to obtain a new over winning prize number OMN is performed (step S350). After Step S340 or S350, the number of prize balls M5D, MAD, and MED is incremented by 1 for each of 5, 10, and 15 prize balls (Steps S370 to S390), and the process returns. If a negative determination is made in step S310, the process returns.

  Next, a process in which the CPU 63 of the prize ball control board 31 drives and controls the ball cutting motor 29b to pay out the prize ball will be described according to a “prize ball payout routine” shown in FIG. If the value of the unpaid winning number ZMN added by the processing of step S260 is not zero and the over-winning number OMN is zero (steps S400 to S410), the number of winning balls for the winnings that have not been paid out is stored in the memory. It is stored in order of winning on A000 (H) to A013 (H). In this case, the CPU 63 of the prize ball control board 31 stores the data written in the first and second bits, which are the least significant bits of the address A000 (H), as 11 (H), 10 (H) or 01 (H) is determined (step S420).

  If it is determined to be 11 (H) by the determination process, the ball cutting motor 29b is driven and controlled until it is detected by the prize ball payout switch 29a that 15 game balls have been paid out (step S430). A process of decrementing (-1) the value of the prize ball number MED is executed (step S440). If it is determined as 10 (H) by the determination process, the ball cutting motor 29b is driven and controlled until it is detected by the prize ball payout switch 29a that 10 game balls have been paid out (step S450). A process of decrementing (-1) the value of the number of winning balls MAD is executed (step S460). If it is determined as 01 (H) by the determination process, the ball cutting motor 29b is driven and controlled until it is detected by the prize ball payout switch 29a that five game balls have been paid out (step S470). A process of decrementing (-1) the value of the number of winning balls M5D is executed (step S480).

  When the execution of the winning ball payout process is completed (steps S420 to S480), the winning order storage update is executed (step S490), and then the unpaid winning number ZMN is decremented (step S500), and the process returns. In the winning order storage update process (step S490), the 1-byte data at address A000 (H) is shifted to the right twice, that is, the written data is moved to the right by 2 bits. The data of the first bit and the second bit of address A001 (H) is moved to the eighth bit which is the most significant bit, and this process is repeated until an address where no data is written. On the other hand, if it is determined in step S410 that the over-winning number OMN is not zero, the number of winning ball data that has not been paid out has exceeded 80, and the winning ball for which the winning order is not stored. Is executed (step S510), the process of step S500 is executed, and the process returns. If a negative determination is made in step S400, the process returns. This over winning ball payout process will be described according to the “over winning ball payout process” shown in FIG.

  In this process, the CPU 63 of the prize ball control board 31 first determines whether the value of the prize ball number MED is zero (step S550), whether the value of the prize ball number MAD is zero (step S560), and the number of prize balls. Whether or not the value of M5D is zero (step S570) is successively determined and executed. If the value of the number of prize balls MED is not zero (step S550), the value of the number of prize balls MED is decremented after paying out 15 game balls as prize balls (steps S580 to S590). If the value of the prize ball number MED is zero and the value of the prize ball number MAD is not zero (steps S550 to S560), the value of the prize ball number MAD is decremented after paying out 10 game balls as prize balls. (Steps S600 to S610). If the value of the prize ball number MED and the value of the prize ball number MAD are both zero and the value of the prize ball number M5D is not zero (steps S550 to S570), the prize is given after paying out five game balls as prize balls. The value of the number of balls M5D is decremented (steps S620 to S630).

  After executing any one of the steps S580 and S590, the steps S600 and S610, or the steps S620 and S630, the value of the over-winning number OMN is decremented (step S640), and the process returns to “return”. If it is determined in steps S550 to S570 that the values of the number of winning balls MED, MAD, and M5D are all zero, nothing is executed and the process returns to “return”.

  As described above, according to the specific example described in detail, the main control board 30 stores the number of winning balls in the order of winning, and transmits the stored winning data to the winning ball control board 31. On the other hand, the winning ball control board 31 stores the number of winning balls in the order of winning until the 20-byte memory is over, and the winning ball cannot catch up or a lot of winnings occur at a time, resulting in a 20-byte memory. When is over, only the number of prize balls is stored. Then, the winning balls are executed in order from the largest number of winning balls with respect to the memory over. As a result, normally, the winning balls can be paid out in the order of winning, and at the time of transition where the winning balls cannot catch up, the payout is executed with priority given to the winning balls having a large number of winning balls for the memory overrun. As a result, there is an excellent effect that the memory space for storing the winning order can be configured without increasing the size. In addition, since the battery backup function is installed in this specific example, even when the system recovers from a power failure, the prize balls can be paid out according to the stored data, and the prize balls can be paid out in the order of winning. It has the effect of being able to.

  Further, in this specific example, when the memory is over, a configuration is adopted in which the amount of memory over is paid out first and then paid out in accordance with the winning order. Even if the data is transmitted, it is only necessary to execute the writing process on the data after the winning ball process is performed, and there is an excellent effect that the storing process of the winning data is not complicated. In this specific example, the winning data transmitted from the main control board 30 to the prize ball control board 31 is configured to send 1-byte data at a time. There is also an excellent effect that it is possible to shorten the time of the receiving process. In addition, in this specific example, in a state where the memory is not over, data indicating the number of winning balls is written in the winning order in the 20-byte memory space of addresses A000 (H) to A013 (H), and the number of winning balls Since the prize ball numbers M5D, MAD, and MED, which are data indicating the data, are incremented, some or all of the data written in the memory at addresses A000 (H) to A013 (H) for some reason disappears. Even so, the payout of prize balls can be effected according to the number of prize balls M5D, MAD, and MED, and there is an effect that no unexpected disadvantage is given to the player. When the memory is not over, the total number of prize balls indicated by the data written to addresses A000 (H) to A013 (H) is compared with the total number of prize balls indicated by the number of prize balls M5D, MAD, and MED. By doing so, it is possible to compare and determine whether or not there is an error in the total number of prize balls.

  Further, in this specific example, a configuration in which data is transmitted in one direction from the main control board 30 to the prize ball control board 31 is adopted, but when the power is turned on, the prize ball control board 31CPU63 is more than the CPU 61 of the main control board 30. Is configured to start up quickly, so that even if a game ball wins immediately after returning from a power failure or the like, the data relating to the winning sent from the main control board 30 to the winning ball control board 31 can be always received. It has the effect. On the other hand, when the power is cut off due to a power failure or the like, the main control board 30 is stopped operating earlier than the prize ball control board 31, so that the prize ball control board 31 receives the data relating to the winning sent from the main control board 30. This has the effect of preventing the harmful effect of not receiving. In addition, the XNMI terminal becomes valid before the XRES terminal becomes valid and the CPU 63 of the prize ball control board 31 stops its operation. At this time, data writing can be prohibited, so that the power supply is unstable. This also has an extremely excellent effect that accurate winning data can be stored and retained in the event of a power failure without writing data in the state.

  In this specific example, the payout of the prize ball when the memory is over is configured to give priority to paying out a prize ball with a large number of prize balls. There is no problem. Also, in this specific example, when returning from a power failure, it is configured to pay out the winning balls in the order of winning according to the stored data, but when returning from a power failure, priority is given to winning with a large number of winning balls, Alternatively, the payout may be made with priority given to winnings with a small number of prize balls. Further, in this specific example, until the memory is over, data indicating the number of winning balls is written in the memory in the order of winning, and the corresponding winning ball numbers M5D, MAD, and MED are incremented. There is no problem even if the value of the number of winning balls M5D, MAD, and MED is incremented only when it is over, and when the memory is not over, the data indicating the number of winning balls is simply written in the winning order in the memory.

DESCRIPTION OF SYMBOLS 10 ... Pachinko machine 22 ... Game board 24 ... Launch handle 24a ... Touch switch 30 ... Main control board 31 ... Prize ball control board 32 ... Special symbol display device 32a ... LCD panel unit (LCD)
32b ... design display control board (design control board)
33 ... Launch control board 34 ... Lamp control board 35 ... Sound control board 36 ... Normal electric accessory (starting port)
36a ... 1st type starting port switch 37 ... Normal symbol display device 40 ... Grand prize opening 40a ... Accessory continuous operation switch (VSW)
40b ... Ten-count switch (count SW)
52 ... Other prize opening switches 55 ... Power supply boards 60, 62, 65 ... Voltage monitoring circuits 61, 63, 66 ... CPU (one-chip microcomputer)
64 ... Backup voltage monitoring circuit

Claims (1)

A main control board that controls the progress of the game due to the behavior of the game balls launched on the game board surface;
A prize ball payout control board for paying out a prize ball to a player;
A power supply board for supplying power to the main control board and the prize ball payout control board;
In a ball game machine including
A game ball detecting means for detecting a winning of a game ball launched on the game board surface on the main control board, and when the game ball detecting means detects that there is a winning, the winning ball payout in the order of detection Data output means for outputting data for transmission related to the number of prize balls to the control board, and data erasure means for erasing data output by the data output means,
Upon receiving the data output by the data output means on the prize ball payout control board, unpaid data adding means for adding to the unpaid data, and paying out the prize ball according to the added unpaid data An unpaid data subtracting means for subtracting from the unpaid data when it is detected that the payout has been made,
The main control board (30) is equipped with a one-chip microcomputer (61) with a built-in RAM,
The main control board (30) is supplied with 12V power from the power board (55),
The main control board (30) generates a 5V power source for driving the one-chip microcomputer (61) from the supplied 12V power source,
The main control board (30) has a reset circuit (60) connected to a reset terminal (* RES) of the one-chip microcomputer (61),
In the reset circuit (60), the power supply obtained by dividing the 12V power supply is input to the input terminal (VSB), the 5V power supply is input to the power supply terminal (VCC), and the output terminal (RESET) is pulled by the 5V power supply. Up,
The reset circuit (60) sets the reset terminal (* RES) of the one-chip microcomputer (61) to low level when the 12V power supply rises, and then sets the reset terminal (* RES) to high level by the 5V power supply. ,
A ball game machine characterized by that.

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