JP5127027B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine, and more particularly, to a gaming machine in which a control device for controlling various operations is composed of a plurality of boards connected to each other.

  2. Description of the Related Art Conventionally, gaming machines that perform various effects synchronized with game contents using a liquid crystal display device, a speaker, an electric lamp, and the like are known. For example, in a pachinko machine that is one form of gaming machine, when a game ball wins a specific winning opening provided on the gaming board, a plurality of symbols displayed on the liquid crystal display device are changed, and By generating sound and light according to fluctuations, it attracts players' interest. If a plurality of symbols that stop after a predetermined time become a “hit” combination, the game moves to a “hit state” in which a player can acquire a large number of game balls, and the opening / closing member of the big prize opening is opened to play the game The ball is ready for winning. Also, many slot machines have been proposed that use images, sounds, and the like to entertain players.

  And the control apparatus for controlling these various operation | movement is provided in the back side or inside of the gaming machine. Here, since the operation performed by the gaming machine differs depending on the type of gaming machine, the control device has to be created individually according to the type of gaming machine. Therefore, it has been difficult to reduce the manufacturing cost of the gaming machine.

Therefore, a control board that can be used in common for multiple types of gaming machines and a memory board that is unique to each type of gaming machine are created separately, and these are connected to each other to configure the entire control device. A gaming machine has been proposed (see, for example, Patent Document 1). According to this gaming machine, when a new gaming machine is manufactured using parts of an old gaming machine, a control board that can be used in common can be used as it is, and only a unique memory board is exchanged for each type of gaming machine. do it. Specifically, regarding a liquid crystal display control device that controls display of a liquid crystal display device, an effect control board including a controller that outputs an image signal to the liquid crystal display apparatus, and the effect control board are detachably provided. A memory board storing different image data for each machine type is created separately. With this configuration, when a new type of gaming machine is manufactured, it is only necessary to replace the memory substrate, and it is not necessary to newly create the liquid crystal display control device itself. Therefore, the manufacturing cost of the gaming machine can be reduced.
JP 2005-329016 A

  However, in such a conventional gaming machine, when a memory board different from the regular memory board to be connected is connected to the control board, an appropriate operation such as error notification or stop of the rendering operation is performed. I could not. Therefore, there is a possibility that the gaming machine is installed in the amusement hall without the regular memory board being connected. In addition, if the production was not performed normally as a result of incorrect connection, the cause of the problem had to be predicted and dealt with based on experience and knowledge. There was also a problem that it could not be done. Furthermore, since the memory board can be easily replaced, there is a possibility that an unauthorized program is replaced with a memory board in which an unauthorized program is stored. However, when an unauthorized operation is performed, an appropriate operation cannot be performed. There was also.

  The present invention has been made to solve the above-described problem, and performs an appropriate operation such as error notification or stop of a rendering operation when a memory board different from a regular memory board is connected to the control board. An object of the present invention is to provide a gaming machine that can be used.

In order to achieve the above object, the gaming machine according to claim 1 includes a main board that controls the main control of the game and a connection part connected to another board, and transmits a signal transmitted from the main board. The sub-control board that receives and controls the production and the data connected to the connecting portion of the sub-control board and used by the sub-control board are stored, and ID information that identifies the type of the board is stored a memory substrate having the ID information storing means for a proper memory information storage means for previously storing information of appropriate said memory board connected to the connection portion, and the information stored in the proper memory information storage means, using said ID information stored in the ID information storage means, whether or not appropriate the memory substrate in alignment with the stored in the proper memory information storage means information is connected to the connecting portion A memory substrate alignment determining means for determining, inconsistent operation control means for controlling a predetermined operation performed when appropriate the memory substrate is determined not to be connected by the memory substrate alignment determining means, said secondary A relay board that connects the connection portion of the control board and the plurality of memory boards, and the ID information storage means stores at least ID information indicating a storage capacity of the memory board, And a decoding circuit for generating a signal for selecting one of the plurality of memory substrates using the ID information .

  In addition to the configuration of the invention described in claim 1, the gaming machine described in claim 2 of the present invention further comprises error display means for informing that the appropriate memory board is not connected to the sub control board. And the non-matching operation control means controls the error display means to display an error when the memory board matching judgment means judges that the appropriate memory board is not connected. And

  A gaming machine according to claim 3 of the present invention comprises, in addition to the configuration of the invention according to claim 1 or 2, an effect control prohibiting means for prohibiting control of the effect by the sub-control board, and the inconsistency The hour operation control means controls the effect control prohibiting means to prohibit the effect control by the sub control board when the memory substrate alignment determining means determines that the appropriate memory substrate is not connected. It is characterized by that.

Further, in the gaming machine according to claim 4 of the present invention, in addition to the configuration of the invention according to any one of claims 1 to 3 , is the memory board continuously connected to the connection portion of the sub-control board? A memory board connection detection means for detecting whether or not the memory board alignment determination means determines that the appropriate memory board is not connected when the memory board connection detection means determines that the memory board is not continuously connected. It is judged that it is not connected to the connection part.

In addition to the configuration of the invention according to any one of claims 1 to 4 , the gaming board according to claim 5 of the present invention includes ID information for displaying ID information for identifying the type of the board. A display unit is provided.

According to the gaming machine of claim 1, information on an appropriate memory board connected to the connection portion of the sub control board is stored in the appropriate memory information storage means, and the information stored in the appropriate memory information Whether or not an appropriate memory board to be matched is connected to the connection portion is determined by the memory board matching judgment means. If it is determined that an appropriate memory board is not connected, the predetermined operation is controlled by the operation control means at the time of mismatch. Therefore, if an inappropriate memory board is connected due to a connection error, failure, fraud, etc., the operator should confirm that the appropriate memory board is not connected by performing a predetermined operation. And can be notified to employees of the playground. Therefore, an operator or the like can take quick and accurate measures such as replacement or repair of parts.
Moreover, the gaming machine of the present invention can easily determine whether or not an appropriate memory board is connected by using the ID information stored in the ID information storage means of the memory board. Further, the designer can appropriately change the accuracy of judgment of the consistency of the memory board, the ease of designing the gaming machine, the manufacturing cost, and the like by appropriately changing the stored contents of the ID information.
In addition, at least ID information indicating its own storage capacity is stored in the memory board, and the decoding circuit provided in the relay board outputs a signal for selecting one of the plurality of memory boards as the ID information. Can be used. Therefore, it is possible to form a continuous memory map that does not cause an empty space. Therefore, even when the capacity of the memory board connected to the sub control board is changed, it is not necessary to change the design of the sub control board itself. In addition, although the degree of freedom of connection of the memory board to the sub control board is improved, there is a possibility that a connection error of the memory board may occur, but it is possible to determine whether or not an appropriate memory board is connected. Further, it is possible to improve the degree of freedom of connection of the memory board while preventing the gaming machine from being installed in the game arcade with incorrect connection.

  Further, in the gaming machine according to claim 2 of the present invention, in addition to the effect of the invention according to claim 1, an error display means displays an error when an inappropriate memory board is connected. Therefore, an operator or the like can easily grasp from an error that an appropriate memory board is not connected.

  In addition to the effect of the invention described in claim 1 or 2, the gaming machine according to claim 3 of the present invention is provided by the effect control prohibiting means when an inappropriate memory board is connected. Since the control of the effect of the sub control board is prohibited, the operator or the like can easily grasp that the appropriate memory board is not connected. In addition, since the performance itself is not performed, it is possible to prevent the performance from being disturbed and causing the player to feel uncomfortable. Furthermore, it is possible to prevent the game from being continued while the memory board storing the illegal program is connected.

Further, in the gaming machine according to claim 4 of the present invention, in addition to the effect of the invention according to any one of claims 1 to 3 , it is determined whether or not the memory board is continuously connected to the connection portion of the sub control board. It is detected by the memory board connection detection means, and based on the detection result, it can be determined whether or not an appropriate memory board is continuously connected to the connection portion. Therefore, if the memory board connected to the sub-control board is removed even once, it is determined that the memory boards are not aligned, so that it is possible to more surely grasp fraud or poor connection.

In addition, in the gaming machine according to claim 5 of the present invention, in addition to the configuration of the invention according to any one of claims 1 to 4 , ID information for identifying the type of board is provided in the ID information display section. Therefore, an operator or the like can reduce connection mistakes by looking at the ID information display unit and connecting the memory board to the sub-control board. In addition, by checking the ID information display unit, it is possible to check whether or not an appropriate memory substrate is connected.

  Hereinafter, the pachinko machine 1 which is 1st embodiment of this invention is demonstrated with reference to drawings. First, with reference to FIG.1 and FIG.2, the mechanical structure of the pachinko machine 1 is demonstrated. FIG. 1 is a perspective view of the state in which the front frame 14 and the middle frame 13 of the pachinko machine 1 are opened as seen obliquely from the front, and FIG. 2 is a front view of the pachinko machine 1. In the following description, the front side of the sheet of FIG. 2 is referred to as “the front side of the pachinko machine 1”, and the depth side of the sheet is referred to as “the back side of the pachinko machine 1”.

  First, a schematic configuration of the pachinko machine 1 will be described. As shown in FIG. 1, the pachinko machine 1 includes an outer frame 12 that is disposed in an island facility (not shown) of a game arcade and supports a main body of the pachinko machine 1 in a substantially rectangular shape when viewed from the front. The outer frame 12 is a frame member that supports the main body of the pachinko machine 1 and is attached to an island facility (not shown) of the game arcade. The vicinity of the left column portion of the middle frame 13 is pivotally supported in the vicinity of the outer frame left column portion 12 a of the outer frame 12.

  The middle frame 13 is made of a metal angle member having a substantially rectangular shape when viewed from the front. The left column portion of the middle frame 13 is pivotally supported in the vicinity of the outer frame left column portion 12a of the outer frame 12 via the upper hinge 22 and the lower hinge 21, so that the middle frame 13 is substantially the same as the outer frame 12. It can be rotated horizontally (openable and closable). The game board 2 is disposed in the upper half of the middle frame 13. Further, an upper plate 5 is provided below the game board 2 on the front side of the middle frame 13 to supply game balls to the launcher and receive prize balls. A lower plate 6 is provided. On the right side of the lower plate 6, a launch handle 7 for adjusting the launch of the game ball by the launcher is provided. A front frame 14 having a substantially rectangular shape in front view is provided on the front side of the game board 2.

  A center cover 27 is provided on the back side of the middle frame 13 of the pachinko machine 1, and a main board 41, a sub-integrated board 58, and an effect control board, which will be described later, for controlling each part of the pachinko machine 1 are provided. 43, a number of control devices (see FIG. 3) such as the power supply board 42 are protected. The right side surface of the center cover 27 is provided with an error display unit 38 that displays an error occurring between the effect control board 43 and the memory boards 120 and 130 (see FIG. 3) connected to the effect control board 43. It has been. This error display section 38 is composed of 7-segment LEDs, and displays numbers, alphabets, etc., when a memory board having an appropriate capacity corresponding to the pachinko machine 1 is not connected to the effect control board 43, etc. The error occurrence and its contents are notified to the user. This display method will be described later.

  Although not shown, a mode setting button 34 (see FIG. 3) for setting an identity confirmation mode for confirming the identity of the memory board connected to the effect control board 43 is provided on the back side of the center cover. A mode cancel button 35 (see FIG. 3) for canceling the identity confirmation mode is provided. A lower cover 28 is provided below the center cover 27, and various parts for operating the pachinko machine 1 are protected. Further, a game ball tank 29 for storing game balls supplied from the gaming machine installation island is provided above the center cover 27.

  Next, the table frame 14 will be described. As shown in FIG. 2, the front frame 14 has a substantially rectangular shape when viewed from the front, and has an opening at a substantially central position so that the game area 4 of the game board 2 can be viewed from the front side. A glass window 23 (see FIG. 1), which is a transparent plate, is fitted into the opening, and the gaming area 4 can be visually recognized through the glass window 23. The front frame left end portion 14a (see FIG. 1) of the front frame 14 is pivotally supported in the vicinity of the left column portion of the middle frame 13, so that the front frame 14 rotates in a substantially horizontal direction with respect to the middle frame 13. It is movable (can be opened and closed). A speaker 32 is provided at the upper left part of the front frame 14 and a speaker 33 is provided at the upper right part. The two speakers 32 and 33 are connected to the sub-integrated board 58 (see FIG. 3) by wiring. Yes. Various sounds are generated from the speakers 32 and 33 under the control of the sub-integrated board 58. A large number of lighting lamps 63 (see FIG. 3) for production are provided on the front surface of the front frame 14.

  Next, the game board 2 will be described. By operating the launch handle 7, a game ball launched from a launcher (not shown) as launching means flows down the space formed by the game board 2 and the glass window 23. The game board 2 is supported by the front side of the game board opening (not shown) of the game board fixed frame fixed to the back side of the middle frame 13 and is supported by a front frame 14 that holds the glass window 23 substantially at the center. Protected. As shown in FIG. 1, a game area 4 having a substantially circular shape in front view is provided on the front surface of the game board 2, surrounded by the outer rail 3, in which game balls launched by the launching means flow down.

  As shown in FIG. 2, a symbol display device 8 having a liquid crystal display device 36, various lamps and LEDs is provided in the approximate center of the game area 4. Further, a special symbol starting electric accessory 15 is provided on the lower side of the symbol display device 8, and normal symbol starting gates 19 and 20 are respectively arranged on the left and right sides of the special symbol starting electric accessory 15. Yes. A normal winning opening 10 is provided on the left side of the normal symbol starting gate 19, and an ordinary winning opening 11 is provided on the right side of the normal symbol starting gate 20. Further, a special winning opening 16 is provided below the special symbol starting electric accessory 15, and a gaming ball that has not won any winning opening is collected below the special winning opening 16. A mouth 30 is provided.

  Next, the symbol display device 8 will be described. As shown in FIG. 2, a special symbol memory number display LED 60 composed of four LEDs is provided in the lower part of the symbol display device 8, and a special symbol composed of two 7-segment LEDs is provided on the right side thereof. A symbol display unit 25 is provided. Further, a normal symbol storage number display LED 59 composed of four LEDs is provided at the upper part of the symbol display device 8, and a normal symbol display unit 24 is provided above it. The symbol display device 8 includes a liquid crystal display device 36 at the center. Various images such as moving images and messages are displayed on the liquid crystal display device 36. In particular, in order to notify the result of the jackpot determination, three demo symbols are displayed. The demo symbol uses a symbol larger than the special symbol displayed on the special symbol display unit 25 so as to attract the player's eyes.

  Next, the electrical configuration of the pachinko machine 1 will be described with reference to FIG. FIG. 3 is a block diagram showing an electrical configuration of the pachinko machine 1. As shown in FIG. 3, the control unit 40 mainly includes a main board 41, a power supply board 42, an effect control board 43, a payout control board 45, an electrical decoration board 46, an intermediate board 47, and a sub-integrated board 58. Yes. The production control board 43 is connected to the first memory board 120 and the second memory board 130 via the relay board 100. The control unit 40 is provided on the back side (back side) of the pachinko machine 1 and is protected by the center cover 27 (see FIG. 1).

  First, the main substrate 41 will be described. The main board 41 that performs main control of the pachinko machine 1 is provided with a main board CPU unit 50 that performs various processes according to a program. The main board CPU unit 50 includes a CPU 51 for performing various arithmetic processes, a RAM 52 for temporarily storing data values generated during the arithmetic processes, a control program, initial values of various data, and other boards. And a ROM 53 that stores commands and the like for instructing these, and these are integrally molded as one LSI. Further, an interrupt signal generation circuit 57 is connected to the CPU unit 50, and the CPU 51 executes a control program stored in the ROM 53 every time an interrupt signal is input from the interrupt signal generation circuit 57. To do.

  Further, the main board 41 is provided with an I / O interface 54, and a game ball that has won the sub-board such as the sub-integrated board 58, the payout control board 45, the intermediate board 47, and the special symbol starter electric accessory 15. A start port switch 72 is connected to detect. Further, the I / O interface 54 of the main board 41 is connected to an output port 55 for outputting information of the pachinko machine 1 to a game hall management computer (not shown).

  Next, the payout control board 45 and the intermediate board 47 will be described. The payout control board 45 incorporates a CPU 45 a, an input interface (not shown), a RAM and a ROM, and is connected to a prize ball payout device 49. Then, according to the command transmitted from the main board 41, the prize ball payout device 49 is controlled. Further, the intermediate board 47 has a large winning opening opening solenoid 70 for opening / closing the opening / closing member of the special winning opening 16, an electric accessory opening solenoid 71 for opening / closing the opening / closing member of the special symbol starting electric combination 15, The normal symbol operation switches 73 and 74 that detect the game balls that have passed the symbol start gates 19 and 20, the count switch 75 that counts the number of game balls that have won the big winning opening 16, and the normal winning ports 10 and 11 won. Winning port switches 76 and 77 for detecting a game ball, a normal symbol memory number display LED 59 and a special symbol memory number display LED 60 composed of four LEDs, and a normal symbol display unit 24 and 2 composed of one LED. A special symbol display unit 25 composed of two 7-segment LEDs is connected. The intermediate board 47 relays switches and solenoids, and relays to a display unit or the like that receives direct control from the main board 41.

  Next, the sub integrated substrate 58 and the electrical decoration substrate 46 will be described. The sub-integrated board 58 is provided with a CPU 581, a RAM 582, and a ROM 583, and is connected to the effect control board 43, the electrical decoration board 46, the speakers 32 and 33, the mode setting button 34, and the mode release button 35. And according to the command transmitted from the main board | substrate 41, comprehensive control of the effect control board 43, the electrical decoration board 46, and the speakers 32 and 33 is performed. Further, by turning on the power to the pachinko machine 1 while the mode setting button 34 is pressed, the identity confirmation mode for confirming the identity of the memory board connected to the effect control board 43 is set. When the power is turned on while the mode release button 35 is pressed, the identity confirmation mode is released. This identity confirmation mode will be described later with reference to FIG. The illumination board 46 incorporates a CPU 46a, an input interface (not shown), RAM, and ROM, and controls the illumination lamp 63.

  Next, the power supply substrate 42 will be described. The power supply board 42 supplies direct current stabilized power to the pachinko machine 1 and includes a power supply circuit 65, a backup battery 66, and a power supply monitoring circuit 67. The power supply circuit 65 is supplied with AC 24V. A rectifier composed of a silicon diode bridge (not shown), a smoothing circuit composed of an electric field capacitor, a stabilization circuit composed of a regulator IC, and the like are provided, and stabilized DC 12V and 5V are generated to each substrate. It can be supplied. Further, the backup battery 66 is composed of a capacitor. When the backup battery 66 is charged with DC 5V generated by the power supply circuit 65 and no power is supplied to the pachinko machine 1, the backup battery (main board 41, sub integrated board) is used. 58 and the RAM of the effect control board 43). Thereby, the pachinko machine 1 can store various contents at the time of power-off. When the power supply voltage supplied to the power supply circuit 65 drops to a predetermined voltage or less (12 V or less in the present embodiment) during the game, the power supply monitoring circuit 67 causes the main board 41, the sub integrated board 58, and the production. A power-off signal is output to the control board 43. Then, supply of backup power (5 V) from the backup battery 66 to the backup target is started, and the stored contents of the pachinko machine 1 are backed up. On the other hand, when the voltage rises above the predetermined voltage, the output of the power-off signal is stopped and predetermined processing is performed.

  Next, the effect control board 43 will be described. The effect control board 43 includes a CPU, a RAM, a ROM, and the like. The display control unit 48 outputs display control data according to a command received from the sub-integrated board 58, and a liquid crystal display according to a signal input from the display control unit 48. An image display processor (Video Display Processor, hereinafter referred to as “VDP”) 80 that outputs an image signal to the device 36 is provided. The effect control board 43 includes a 4 GB first memory board 120 having 1 GB ROMs 121 to 124 (see FIG. 4) and a 2 GB second memory board 130 having 1 GB ROMs 131 and 132 (see FIG. 4). Are connected via the relay substrate 100. The VDP 80 reads out necessary data from the image generation data stored in the plurality of ROMs in the two memory boards 120 and 130 according to the display control data input from the display control unit 48, and clicks on the pachinko machine. Image data (RGB data) corresponding to the gaming state of the machine 1 is generated. This image data is developed and temporarily stored in the VRAM 82 (see FIG. 4), and is output to the liquid crystal display device 36 in accordance with the display control data. An error display unit 38 and a liquid crystal display device 36 are connected to the effect control board 43, details of which will be described later with reference to FIG.

  Next, the details of the effect control board 43 and its surrounding control circuits will be described with reference to FIG. FIG. 4 is a block diagram showing details of the effect control board 43 and its surrounding control circuits.

  First, the effect control board 43 will be described. The effect control board 43 includes a display control unit 48, a VDP 80, an oscillator 81, and a VRAM 82. The display control unit 48 includes a display control CPU 91, a display control RAM 92, and a display control ROM 93. The display control ROM 93 stores a display control program for the liquid crystal display device 36, data for controlling the image display mode, and the like, and transmits signals and data to the display control CPU 91. Similarly, the display control RAM 92 is also connected to the display control CPU 91 and temporarily stores various counters, flags, data, signals, etc. In the pachinko machine 1 of the first embodiment, the same memory board is used. A memory board identity confirmation flag is stored in the display control RAM 92 indicating that 120 and 130 are continuously connected to the effect control board 43 without being removed or replaced. Details of this will be described later.

  The display control CPU 91 is a CPU that can handle a memory with a storage capacity of 8 GB. The display control CPU 91 receives a command for controlling the display mode of the liquid crystal display device 36 from the sub-integrated board 58, and displays an image based on the received control command. Select the display mode. Then, display control data for displaying the selected display mode is transmitted to the connected VDP 80. The display control CPU 91 is connected to an address bus and a data bus, and outputs an address signal and a data signal. The address signal includes a memory substrate selection signal for selecting one of the plurality of memory substrates, and a chip select signal for selecting one of the plurality of ROMs provided on the memory substrate. And is decoded by first decoding circuits 125 and 135 and a second decoding circuit 101 described later. Each ROM recognizes whether or not it is accessed by the input chip select signal, and data access is possible when it is accessed. Here, the display control CPU 91 according to the first embodiment recognizes the capacity of the memory board connected to the effect control board 43 using the ID information stored in the memory board. Further, the display control CPU 91 confirms whether or not an appropriate memory board is connected to the effect control board 43 using the ID information of the memory board, and details thereof will be described later with reference to FIG.

  The oscillator 81 oscillates at a constant dot clock frequency and is connected to the VDP 80. The VDP 80 transmits to the liquid crystal display device 36 a synchronization signal necessary for taking a video display timing based on the dot clock frequency oscillated by the oscillator 81. Further, the VDP 80 reads necessary image generation data from a ROM in the memory boards 120 and 130 described later in accordance with the display control data transmitted from the display control CPU 91, and image data (in accordance with the gaming state of the pachinko machine 1 ( RGB data) is generated. The image data is developed and temporarily stored in the VRAM 82, and the image data is read from the VRAM 82 in accordance with the display control data and transmitted to the liquid crystal display device 36 in accordance with the synchronization signal. Further, the VDP 80 incorporates an LSI for checking registers and the like. And the effect control board 43 demonstrated above is provided with the connector 88, The relay board | substrate 100 or the memory boards 120 and 130 can be connected via this connector 88. FIG.

  Next, the first memory substrate 120 will be described. The first memory board 120 is provided with ROMs 121 to 124 having a storage capacity of 1 GB and a first decoding circuit 125, and is connected to another board by a connector 118. The first decoding circuit 125 is a circuit for selecting one of the four ROMs 121 to 124 in accordance with a chip select signal transmitted through the address bus. The first decode circuit 125 and the ROMs 121 to 124 are connected by a chip select signal line, and a decode circuit input line that is a part of an address bus is connected from the connector 118 to the first decode circuit 125. Further, an address bus and a data bus are connected from the connector 118 to the ROMs 121 to 124. Here, in the block diagram shown in FIG. 4, the line extending from the connector 118 is represented by one line, but actually comprises a plurality of address buses and data buses. For the sake of simplification of description, a plurality of signal lines are expressed by a single line in the following manner. In addition, since there are four ROMs 121 to 124 mounted on the first memory board 120, the number of decoding circuit input lines connected to the first decoding circuit 125 from the connector 118 is actually two.

  In addition, the first memory board 120 is provided with an ID information storage unit 126 that stores ID information indicating its own storage capacity. The ID0 signal line 127 in the ID information storage unit 126 is connected to the power supply potential, and the ID1 signal line 128 is connected to the ground potential, which indicates that its own storage capacity is 4 GB. This will be described in detail later. . The ID0 signal line 127 and the ID1 signal line 128 are both connected to the connector 118.

  Next, the second memory substrate 130 will be described. The second memory board 130 is provided with ROMs 131 and 132 having a storage capacity of 1 GB and a first decoding circuit 135, and is connected to another board by a connector 119. Unlike the first decode circuit 125 in the first memory substrate 120, the first decode circuit 135 in the second memory substrate 130 is a circuit for selecting one of the two ROMs 131 and 132. An address bus and a data bus are connected from the connector 119 to the ROMs 131 and 132, a decoding circuit input line that is a part of the address bus is connected from the connector 119 to the first decoding circuit 135, and a decoding circuit input line from the first decoding circuit 135 to the ROMs 131 and 132. Are connected to chip select signal lines.

  Similarly to the first memory substrate 120, the second memory substrate 130 is also provided with an ID information storage unit 136 indicating its own storage capacity. The ID0 signal line 137 and the ID1 signal line 138 are connected from the connector 119 to the ID information storage unit 136, and both of these two signal lines are connected to the ground potential, so that the storage capacity thereof is 2 GB. It shows that there is. Details of this will be described later.

  The ROMs 121 to 124 provided on the first memory substrate 120 and the ROMs 131 and 132 provided on the second memory substrate 130 are both flash ROMs that can be electrically rewritten. Accordingly, when a new type of gaming machine is manufactured using parts of an old gaming machine, the contents of the ROMs 121 to 124 and the ROMs 131 and 132 can be rewritten and used to reduce costs. In addition, an ID information display unit that displays ID information indicating the type of the substrate is provided on the surfaces of the memory substrates 120 and 130. In the first embodiment, since the ID information is information indicating the storage capacity, information of “2 GB” and “4 GB” is displayed on the surfaces of the memory substrates 120 and 130. Therefore, by looking at the ID information display unit and connecting the memory boards 120 and 130 to the effect control board 43, connection errors can be reduced.

  Next, the relay board 100 will be described. The relay substrate 100 is provided with a second decoding circuit 101 and an ID information decoding circuit 102. A connector 115 connected to the connector 88 of the effect control board 43, a connector 116 to which the memory boards 120 and 130 are connected, and a connector 117 are provided.

  The ID information decoding circuit 102 receives ID information input from the ID information storage unit 126 of the first memory substrate 120 and the ID information storage unit 136 of the second memory substrate 130 through the terminals 1A, 1B, 2A, and 2B. Is decoded, and a mode signal is generated and output to the second decoding circuit 101. As this mode, four types of modes are set according to the storage capacity of the memory board connected to the connector 116 and the connector 117, and a mode signal corresponding to the mode is output. Specifically, when a 2 GB memory board is connected to both the connector 116 and the connector 117, “mode 0”, and when a 4 GB memory board is connected to the connector 116 and a 2 GB memory board is connected to the connector 117, the “mode” “Mode 2” when a 2 GB memory board is connected to the connector 116 and a 4 GB memory board is connected to the connector 117, and “Mode 3” when a 4 GB memory board is connected to both the connector 116 and the connector 117 A mode signal indicating is output. In the first embodiment, since the 4 GB first memory board 120 is connected to the connector 116 and the 2 GB second memory board 130 is connected to the connector 117, the ID information decoding circuit 102 to the second decoding circuit 101 are connected. Outputs a signal indicating "mode 1".

  Further, ID information indicating the storage capacities of the two memory boards connected to the relay board 100 is output from the ID information decoding circuit 102 to the display control CPU 91. The display control CPU 91 recognizes the storage capacity of the memory board connected via the connector 88 based on this ID information.

  The second decoding circuit 101 is connected to the display control CPU 91 of the effect control board 43, the first decoding circuit 125 of the first memory board 120, and the first decoding circuit 135 of the second memory board 130 via an address bus. ing. The second decoding circuit 101 determines mapping according to the mode signal input from the ID information decoding circuit 102. Here, the second decoding circuit 101 determines the mapping so that the addresses are continuous without any vacancy. Then, either one of the first memory substrate 120 and the second memory substrate 130 is selected in accordance with the memory substrate selection signal located in the upper bits of the chip select signal. In the relay board 100, a data bus is connected from the connectors 116 and 117 to the connector 115.

  Next, the relationship between the ID information input to the display control CPU 91 and the storage capacity of the memory boards 120 and 130 will be described with reference to FIGS. FIG. 5 is a diagram illustrating the relationship between the ID information input to the display control CPU 91 and the storage capacity recognized by the display control CPU 91. As shown in FIG. 4, two terminals ID0 and ID1 are connected from the display control CPU 91 to the connector 88. Then, the 4 GB first memory board 120 or the 2 GB second memory board 130 can be directly connected to the effect control board 43, and two memory boards can be connected via the relay board 100. As described above, in the ID information storage unit 126 of the 4 GB first memory substrate 120, the ID0 signal line 127 is connected to the power supply potential (High), and the ID1 signal line 128 is connected to the ground potential (Low). In the ID information storage unit 136 of the 2 GB second memory substrate 130, both the ID0 signal line 137 and the ID1 signal line 138 are connected to the ground potential (Low).

  When the memory boards 120 and 130 are directly connected to the effect control board 43 without using the relay board 100, the ID0 signal lines 127 and 137 are connected to ID0 of the display control CPU 91, and the ID1 signal lines 128 and 138 are display controlled. It is connected to ID1 of CPU91. Then, as shown in FIG. 5, when both ID0 and ID1 are “Low”, the display control CPU 91 recognizes that the capacity of the memory board is 2 GB, ID0 is “High”, and ID1 is “Low”. In this case, the capacity of the memory substrate is recognized as 4 GB.

  When two memory boards are connected to the effect control board 43 via the relay board 100, the ID0 signal line 127 of the first memory board 120 is input to 1A and the ID1 signal line 128 is input to 1B. The ID0 signal line 137 of the second memory board 130 is input to 2A, and the ID1 signal line 138 is input to 2B. The ID information of the two memory boards 120 and 130 is converted by the ID information decoding circuit 102 and output to ID0 and ID1 of the display control CPU 91.

  As shown in FIG. 5, when the 2 GB second memory board 130 is connected to both the connectors 116 and 117 of the relay board 100, “High” is set to ID0 of the display control CPU 91, and “Low” is set to ID1. ”Is input, and the display control CPU 91 recognizes that the capacity of the memory board is 4 GB. When the 4 GB first memory board 120 is connected to the connector 116 and the 2 GB second memory board 130 is connected to the connector 117, “Low” is input to ID 0 and “High” is input to ID 1. It is recognized that the capacity is 6 GB. Similarly, when a 4 GB memory board is connected to the connector 116 and a 2 GB memory board is connected to the connector 117, “Low” is input to ID 0 and “High” is input to ID 1. When the 4 GB first memory board 120 is connected to both the connectors 116 and 117, “High” is input to both ID 0 and ID 1 and the capacity is recognized as 8 GB. In this way, the display control CPU 91 recognizes the storage capacity of the memory board based on the ID information input by ID0 and ID1.

  With such a configuration, the pachinko machine 1 can use the ID information when decoding in the relay board 100 to continuously determine mapping without causing a space in the address. Therefore, for example, when one 4 GB first memory board 120 is used and when two 2 GB second memory boards 130 are used, the memory map is the same. In addition, when one 4 GB first memory board 120 and two 2 GB second memory board 130 are used, the memory map is the same regardless of which of the connectors 116 and 117 is connected to the 4 GB second memory board 130. It becomes. Therefore, even when the type and number of memory boards connected to the effect control board 43 are changed, there is no need to redesign the effect control board 43. In other words, the effect control board 43 can have versatility.

  Further, the pachinko machine 1 determines whether or not a memory substrate having an appropriate capacity is connected based on the ID information, and performs an operation such as an error notification based on the determination result, so that the memory substrates having different capacities can be obtained. While preventing the pachinko machine 1 from being installed in the amusement hall while being connected, it also prevents an illegal act caused by exchanging the memory board.

  Next, a memory substrate alignment confirmation process that is a main part of the present invention will be described. This memory board alignment confirmation process is executed by the display control CPU 91 of the effect control board 43 based on the command and information transmitted from the sub integrated board 58. The display control CPU 91 determines whether or not the capacity indicated by the appropriate memory information that is information on the appropriate memory board to be connected matches the capacity indicated by the ID information of the memory board that is actually connected to the connector 88. A determination is made, and the display of the error display unit 38 is controlled based on the determination result. Further, when the identity confirmation mode is set by an amusement hall employee or the like (hereinafter referred to as “employee”), whether or not the memory board is removed from the connector 88 is monitored. Prohibits the display of the liquid crystal display device 36 and prompts the employee to confirm the memory substrate.

  First, information transmitted from the sub integrated board 58 to the effect control board 43 will be described. The ROM 583 (see FIG. 3) of the sub-integrated board 58 stores appropriate memory information that is information relating to an appropriate memory board to be connected to the effect control board 43. When the pachinko machine 1 is turned on, an appropriate memory information notification signal that is a signal indicating the contents of the appropriate memory information is transmitted to the effect control board 43.

  Next, a command transmitted from the sub integrated board 58 to the effect control board 43 will be described. After the appropriate memory information notification signal is transmitted from the sub integrated substrate 58 to the effect control substrate 43, a command for instructing an operation related to the identity confirmation mode is transmitted. In the pachinko machine 1 of the first embodiment, the employee sets whether or not to execute the identity confirmation mode, which is a mode for monitoring whether or not the memory board is removed from the effect control board 43. Specifically, when the power of the pachinko machine 1 is turned on while the mode setting button 34 (see FIG. 3) is pressed, the identity confirmation mode flag stored in the RAM 582 of the sub-integrated board 58 is checked for identity. “1” indicating that the mode is being executed is stored. Then, an identity confirmation setting command for instructing setting of the identity confirmation mode is transmitted from the sub-integrated board 58 to the effect control board 43. On the other hand, when the power of the pachinko machine 1 is turned on while the mode release button 35 (see FIG. 3) is pressed, “0” indicating that the identity confirmation mode is not being executed is stored in the identity confirmation mode flag. The Then, an identity confirmation non-execution command instructing not to execute the identity confirmation mode is transmitted to the effect control board 43.

  In addition, as described above, even when power is not supplied to the pachinko machine 1, the backup battery 66 (see FIG. 3) supplies the backup power to the main board 41, the sub integrated board 58, and the effect control board. 43. Therefore, the storage content of the RAM 582 storing the identity confirmation mode flag is preserved even when the power supply to the pachinko machine 1 is cut off. If neither the mode setting button 34 nor the mode release button 35 is pressed when the power to the pachinko machine 1 is turned on, “1” is stored in the identity confirmation mode flag stored in the RAM 582 and “ON” is stored. ”, An identity confirmation execution command indicating that the identity confirmation mode is to be executed is transmitted to the effect control board 43. If the buttons 34 and 35 are not pressed and “0” is stored in the identity confirmation mode flag and is “OFF”, an identity confirmation non-execution command is transmitted.

  Next, with reference to FIG. 6, details of the memory substrate alignment confirmation process performed in the effect control substrate 43 will be described. FIG. 6 is a flowchart of a memory board alignment confirmation process performed by the display control CPU 91 of the effect control board 43. The flag used here includes an identity flag and is stored in the display control RAM 92. If the memory board connected via the connector 88 is the same without being removed, “1” is stored and “ON” is stored in this identity flag, and the memory board is removed even once. “0” is stored in “OFF”. Note that the initial value of the identity flag is “0”.

  When power is supplied to the pachinko machine 1, the display control CPU 91 starts a memory board alignment confirmation process. First, an appropriate memory information notification signal is received from the sub-integrated board 58, and appropriate memory information indicated by the received signal is stored in the display control RAM 92 (S1). In the first embodiment, the appropriate memory information is information on the storage capacity of the memory board, and the appropriate storage capacity of the memory board to be connected to the effect control board 43 is stored in the display control RAM 92.

  Next, the storage capacity indicated by the ID information input from the memory board connected via the connector 88 is stored in the display control RAM 92 (S2). As described above, in the display control CPU 91 of the effect control board 43, the storage capacity of the memory board connected to the effect control board 43 is 2 GB, 4 GB, 6 GB, or 8 GB regardless of the number of connected memory boards. This is recognized by the ID information of the ID information storage units 126 and 136 of the memory boards 120 and 130 (see FIG. 5).

  Next, it is determined whether or not the ID information input from the memory board matches the appropriate memory information notified from the sub-integrated board 58 (S3). If it is determined that they are not matched (S3: NO), a memory board having a storage capacity different from that of the memory board to be connected is connected to the effect control board 43. Therefore, “E” indicating that memory substrates having different capacities are connected is displayed on the error display unit 38 (S4), and the memory substrate alignment confirmation processing is terminated. With such a configuration, an amusement hall employee or a person who checks at a factory can easily grasp that a memory board having a different capacity is connected to the production control board 43, and can quickly repair or replace it. Can respond. Then, an appropriate memory board is connected by repair or replacement and the pachinko machine 1 is turned on, whereby the memory board alignment confirmation process is performed again.

  On the other hand, if it is determined that the ID information of the memory board matches the appropriate memory information of the sub-integrated board (S3: YES), the memory board having the same storage capacity as the memory board to be connected is produced. “8” indicating that it is connected to the control board 43 is displayed on the error display section 38 (S5). Therefore, the employee can easily grasp that a memory substrate having an appropriate capacity is connected. Furthermore, since “8” is displayed on the error display section 38 which is a 7-segment LED, it can be confirmed that all the segments of the error display section 38 are operating normally.

  Next, it is determined whether or not an identity confirmation setting command has been received from the sub-integrated board 58 (S6). When an instruction to set the identity confirmation mode is given by an employee and an identity confirmation setting command is received from the sub-integrated board 58 (S6: YES), the connected memory boards are the same without being removed. “1” indicating the presence is stored in the identity flag and is set to “ON” (S7). Then, whether or not the memory boards are the same is determined based on whether or not the identity flag is “ON” (S8).

  Here, the value of the identity flag when the memory board is removed from the connector 88 will be described. As described above, since the power for backup is supplied from the backup battery 66 to the effect control board 43, the stored content of the display control RAM 92 is retained even when the power to the pachinko machine 1 is not supplied. Regardless of whether or not power is supplied to the pachinko machine 1, the state of the identity flag set to “ON” is maintained. On the other hand, a connection line for supplying backup power connected from the power supply board 42 (see FIG. 3) to the display control RAM 92 has a structure via the relay board 100 and the memory boards 120 and 130. Therefore, the relay board 100 connected to the connector 88 or the memory boards 120 and 130 connected to the relay board 100 (when the memory boards 120 and 130 are directly connected to the connector 88, the memory board 120, When 130) is removed, the power supplied to the display control RAM 92 is shut off. As a result, the contents stored in the display control RAM 92 are erased, the initial value “0” is stored in the identity flag, and “OFF” is set. This makes it possible to determine whether or not the memory board has been removed with a simple configuration.

  Returning to the description of the flowchart of FIG. 6, if the identity flag is “ON” (S8: YES), it is determined that the same one is connected without removing the memory board, and this determination is made. Is repeated. When the memory board or the relay board 100 is removed and the identity flag is “OFF” (S8: NO), the display control data is prohibited from being transmitted to the VDP 80 (S9), and the VDP 80 Stop the production control. Further, “1” indicating that the memory board has been removed from the effect control board 43 is displayed on the error display unit 38 (S10), and the memory board alignment confirmation process is terminated. Therefore, the employee can easily grasp that problems such as fraud, connection failure, connection mistake, etc. have occurred in the pachinko machine 1. In addition, since the distorted image is not displayed on the liquid crystal display device 36, it is possible to reduce the possibility of giving the player an unpleasant feeling. Then, when processing such as confirmation of the memory substrate is performed and the power is turned on to the pachinko machine 1, the memory substrate alignment confirmation processing is performed again.

  If the identity confirmation setting command has not been received from the sub-integrated board 58 (S6: NO), it is determined whether or not the identity confirmation execution command has been received (S11). As described above, when the power to the pachinko machine 1 is turned on, if the identity confirmation mode flag stored in the RAM 582 of the sub-integrated board 58 is “ON”, the identity confirmation execution command is effect control. It is transmitted to the substrate 43. When the identity control execution command is received (S11: YES), the display control CPU 91 proceeds to the determination of S8, and the identity of the memory board is confirmed.

  If no identity confirmation execution command has been received from the sub-integrated board 58 (S11: NO), it is determined whether an identity confirmation non-execution command has been received (S12). If not received (S12: NO), the process returns to S6. On the other hand, when the identity confirmation mode flag of the sub-integrated board 58 is “OFF” and the identity confirmation non-execution command is received (S12: YES), the identity of the memory board is not confirmed. Then, the memory board alignment confirmation process is terminated.

  As described above, according to the pachinko machine 1 of the first embodiment, the appropriate memory information stored in advance in the ROM 583 of the sub-integrated board 58 and the ID of the memory board actually connected to the effect control board 43. If the information is not consistent, an error is displayed. Further, it is monitored whether or not the memory board or the relay board 100 is removed. When the memory board or the relay board 100 is removed, an error is displayed and control for prohibiting the effect by the liquid crystal display device 36 is performed. Therefore, the employee can easily grasp whether or not an appropriate memory board is connected to the presentation control board 43, and can take quick and appropriate measures such as repair, replacement, and confirmation. Further, since the relay board 100 uses the ID information for decoding, the type and number of memory boards that can be connected to the presentation control board 43 are matched to conditions such as the stock quantity of the memory boards and the ease of design. Various changes can be made. And even if it changes, the continuous memory map which does not produce a vacancy can be formed. Thus, when a plurality of memory boards are connected to the effect control board 43 via the relay board 100, the degree of freedom of connection is improved, but the frequency of connection errors may increase. However, according to the present invention, even when a connection error occurs, error notification and production prohibition can be performed. Accordingly, it is possible to improve the degree of freedom of connection of the memory board while preventing the gaming machine from operating in the game arcade while the memory board is incorrectly connected.

  The production control board 43 and the sub integrated board 58 of the first embodiment correspond to the “sub control board” of the present invention, the connector 88 corresponds to the “connecting portion”, and the ROM 583 of the sub integrated board 58 is “appropriate”. It corresponds to “memory information storage means”. In S3 shown in FIG. 6, the display control CPU 91 that determines whether or not an appropriate memory board that matches the appropriate memory information is connected to the connector 88 functions as a “memory board alignment determining unit”. Further, in S4 and S10, the display control CPU 91 that performs control to display an error on the error display unit 38 when it is determined that an appropriate memory board is not connected functions as an “unmatched operation control unit”. In S9, when it is determined that an appropriate memory board is not connected, the display control CPU 91 that prohibits the effect by the liquid crystal display device 36 functions as “effect control prohibiting means”. Further, the error display unit 38 corresponds to “error display unit”, and the ID information storage units 126 and 136 for storing ID information correspond to “ID information storage unit”. In addition, the display control RAM 92 that stores an identity flag that is “OFF” when the memory board is removed corresponds to “memory board connection detecting means”.

  Next, a pachinko machine according to a second embodiment of the present invention will be described with reference to FIG. FIG. 7 is a block diagram showing details of the effect control board 243 and its surrounding control circuits in the pachinko machine of the second embodiment.

  In the pachinko machine of the second embodiment, unlike the pachinko machine 1 of the first embodiment, the effect control board 243 is provided with two connectors 216 and 217, and two memory boards are not provided via the relay board. Can be connected. The ID information of the first embodiment is 2-bit information and has a simple configuration for identifying four types of storage capacities. In contrast, the ID information storage units 226 and 236 provided in the memory boards 220 and 230 of the second embodiment store not only their own storage capacity but also a unique identification number for each type of memory board. ing. The elements constituting the pachinko machine of the second embodiment are other than that the production control board 43 and the memory boards 120 and 130 are different in structure and the relay board 100 and the error display section 38 are not provided. Is the same as the pachinko machine 1 of the first embodiment. Therefore, the same components as those of the pachinko machine 1 are denoted by the same reference numerals, and the description of the mechanical and electrical configurations shown in FIGS. 1 to 3 is omitted or simplified.

  First, the effect control board 243 will be described. The effect control board 243 is provided with two connectors 216 and 217 for connecting a memory board or a relay board. Between the display control CPU 291 provided in the display control unit 248 and the connectors 216 and 217, an address bus and a data bus and a connection line for inputting ID information are provided.

  Next, the memory substrates 220 and 230 will be described. The memory board 220 includes two ROMs 221 and 222, a first decoding circuit 225 for selecting one of the ROMs 221 and 222, an ID information storage unit 226 for storing an identification number assigned to each type of memory board, A connector 229 for connecting to another board is provided. The ROMs 221 and 222 and the first decoding circuit 225 are connected to the display control CPU 291 via the connectors 229 and 216, and the ID information storage unit 226 is also connected to the display control CPU 291 via the connectors 229 and 216. Similarly to the memory board 220, the memory board 230 includes ROMs 231 and 232, a first decoding circuit 235, an ID information storage unit 236, and a connector 239. Note that the ID information storage units 226 and 236 of the second embodiment are configured by a ROM. The two memory boards 220 and 230 have the same storage capacity but different stored contents. Therefore, the identification numbers stored in the ID information storage units 226 and 236 are different.

  Next, the operation of the display control CPU 291 for checking the consistency of the memory substrate will be described. When the pachinko machine is turned on, information indicating the identification number is output from the ID information storage units 226 and 236 of the memory boards 220 and 230 to the display control CPU 291. The ROM 583 of the sub-integrated board 58 stores an identification number of an appropriate memory board to be connected to the connector 216 and an identification number of an appropriate memory board to be connected to the connector 217, respectively. Information indicating the number is transmitted to the display control CPU 291. Then, the display control CPU 291 determines whether or not the identification numbers of the memory boards 220 and 230 actually connected to the effect control board 243 match the identification numbers of the appropriate memory boards stored in the sub-integrated board 58. In the case of matching, normal display control data is transmitted to the VDP 80. On the other hand, when the identification numbers are different, or when the memory boards 220 and 230 are connected to the two connectors 216 and 217 in the reverse order, transmission of display control data to the VDP 80 is prohibited. A signal that stops the effect by the liquid crystal display device 36 and prohibits the effect by the speakers 32 and 33 and the illumination lamp 63 is transmitted to the sub-integrated board 58.

  As described above, in the pachinko machine according to the second embodiment, the identification information for identifying the type of the memory board is included in the ID information stored in the ID information storage units 226 and 236 of the memory boards 220 and 230. include. Then, the display control CPU 291 determines whether or not the identification numbers are matched in addition to the storage capacity of the memory board actually connected to the connectors 216 and 217, whereby the memory boards 220 and 230 and the connector 216 are determined. , 217 and the matching relationship (connection order) of the memory substrate can be accurately determined.

  Needless to say, the present invention is not limited to the above-described embodiment, and various modifications are possible. Hereinafter, a modification of the above embodiment will be described with reference to FIG. FIG. 8 is a flowchart of a memory board alignment confirmation process performed by the display control CPU 91 of the pachinko machine according to the modification. In the first embodiment, when the memory boards 120 and 130 or the relay board 100 are disconnected, all the contents of the display control RAM 92 are erased, thereby simplifying the structure and to the pachinko machine 1. The power consumption is reduced when the power supply is interrupted. On the other hand, in the modification shown in FIG. 8, even when the memory boards 120 and 130 or the relay board 100 are disconnected, the contents of the display control RAM 92 are not erased and the identity of the memory boards 120 and 130 is the same. It is characterized in that it is memorized that it cannot be secured. In the modification shown below, the contents of the memory board identity monitoring process performed by the display control CPU 91 and the structure around the display control RAM 92 (connection lines for power supply, etc.) are the pachinko machine of the first embodiment. Only 1 is different. Therefore, the same code | symbol is attached | subjected about the structure which is common in 1st embodiment, and description is abbreviate | omitted or simplified.

  The memory board identity monitoring process shown in FIG. 8 is always performed in the display control CPU 91 regardless of whether power is supplied to the pachinko machine. The power for performing this process is supplied from the power supply circuit 65 (see FIG. 3) when power is supplied to the pachinko machine. On the other hand, when no power is supplied to the pachinko machine, the power is supplied from the backup battery 66 (see FIG. 3). The memory board identity monitoring process is programmed to be performed every 500 msec in order to accurately grasp the identity of the memory board while suppressing the consumption of power when the backup battery 66 is used. It ends in 1 msec. In addition, the display control RAM 92 of the effect control board 43 is provided with an identity storage area for storing the identity of the memory board. In this identity storage area, “Z” is stored when the identity is maintained without disconnecting the memory board or the relay board 100, and “5” is obtained when the identity cannot be secured. Is stored. Note that once “5” is stored in the identity storage area, the stored contents are not changed until special processing is performed, and is stored by initialization processing when the power to the pachinko machine is turned on. The content is never changed.

  When the memory board identity monitoring process shown in FIG. 8 is started, first, all ROMs in the memory boards 120 and 130 are accessed, and the process of reading the contents of the ROM is performed (S21). This process is completed in about 100 nsec. Next, it is determined whether or not the contents of all ROMs have been read (S22). When the contents of the ROM are erased, when the memory boards 120 and 130 or the relay board 100 are disconnected, or when a connection failure occurs, the display control CPU 91 reads the contents of the ROM. I can't. Therefore, if there is at least one ROM whose contents cannot be read (S22: NO), it is determined that the identity of the memory boards 120 and 130 cannot be secured, and the identity storage area of the display control RAM 92 displays “ 5 "is stored (S23). Then, the memory board identity monitoring process ends. On the other hand, when the contents of all the ROMs have been read (S22: YES), this process ends.

  Then, the manufacturer who has collected the pachinko machine from the game hall attaches a test device to the effect control board 43 and causes the display control CPU 91 to transmit a test command. The display control CPU 91 reads the stored contents of the identity storage area in the display control RAM 92 only when a test command is received, and outputs the read contents to a test device. As a result, the manufacturer can confirm the identity of the memory boards 120 and 130. If the identity is not ensured (“5” is stored in the identity storage area), the memory boards 120 and 130 may be discarded without being reused, and illegal acts may be performed. It may be determined whether or not the memory boards 120 and 130 are to be reused by confirming whether or not a failure has occurred.

  The pachinko machine of the modified example described above cannot guarantee the identity of the memory boards 120 and 130 without erasing the contents of the display control RAM 92 even when the memory boards 120 and 130 or the relay board 100 are disconnected. I can remember that. As in the first and second embodiments, it is desirable to simultaneously check whether the ID information and the appropriate memory information match. As a result, when the memory boards 120 and 130 are illegally replaced, error display and production prohibition can be performed. Further, when a slight contact failure or the like of the connector occurs, the content stored in the display control RAM 92 is held in the game hall and a smooth game is played, while the manufacturer can detect a failure. That is, it is possible to confirm fraud and failure while performing smooth game progression. In addition, by mounting a backup battery 66 that is a secondary battery that can be charged with power supplied from the outside, the RAM backup and the memory board identity monitoring process are longer than when a battery that cannot be charged is used. Can be done for a period.

  The memory board identity monitoring process of the modified example is programmed to be performed every 500 msec, but is not limited to this form, and is based on the degree of power consumption, the time required for illegal ROM replacement, etc. It can be changed as appropriate. For example, the memory substrate identity monitoring process may be performed once or a predetermined number of times per day, or may be configured to be performed once or a predetermined number of times per week. Furthermore, it is good also as a structure performed at predetermined intervals outside the business hours of a game hall. In this manner, the timing for executing the memory board identity monitoring process may be determined by setting a specific interval or setting a specific time for processing. The power consumption can be reduced as the number of processes performed within a predetermined time is set to be smaller, while the failure and the fraud can be accurately detected as the number of processes is increased. In the modification, the memory board identity monitoring process is set to end in 1 msec, but this processing time can be changed according to the processing speed of the CPU.

  In the modification, an analog program timer using a motor and a shaft is used to measure a time interval of 500 msec for performing the memory substrate identity monitoring process. However, the program timer for measuring time may be either an analog method or a digital method, and the type of the program timer may be selected as appropriate. When a digital program timer is used, the display control CPU 91 and the program timer may be controlled separately.

  When a program timer is used, a battery for RAM backup and a battery for executing the operation of the program timer and the memory board identity monitoring process can be provided separately. The processing time of the memory board identity monitoring process of the modified example is set to be performed in a short time in order to suppress power consumption, but if all the power charged in the backup battery is consumed temporarily, The backup contents such as the display control RAM 92 are lost. Therefore, by separately providing a battery for RAM backup and a battery for executing the operation of the program timer and the memory board identity monitoring process, the risk of losing the backup contents of the RAM can be reduced. Further, a CPU that performs the memory substrate identity monitoring process and another CPU such as the display control CPU 91 may be provided separately.

  In addition, the backup battery 66 in the modified example is constituted by an electric double layer capacitor for backing up the stored contents of each RAM and a battery for operating the display control CPU 91 and the like. The capacitor may be another capacitor such as an aluminum electric field capacitor. As the battery used for the backup battery 66, various batteries such as a nickel cadmium battery, a lithium ion battery, a lead seal battery, an air zinc battery, an alkaline battery, a manganese battery, a silver oxide battery, a lithium battery, and a nickel metal hydride battery are used. Is possible.

  Further, in the modified example, “Z” is stored in the display control RAM 92 when the identity of the memory board is secured, and “5” is stored when it is not secured, but this may be changed. it can. For example, the result of the memory board identity monitoring process may be stored twice and it may be determined that the identity cannot be secured only when “5” is stored twice in succession. As a result, even if “5” is stored due to a bug or minor malfunction (for example, static electricity), it is determined that the identity is ensured if it is not continuous. Therefore, the bug or minor malfunction is the same on the memory board. The adverse effect on the sex monitoring process can be reduced.

  In the first and second embodiments, various changes can be made. First, in the first and second embodiments, the connection of the memory board to the effect control board 43 that controls the display of the liquid crystal display device 36 has been described, but the present invention can also be applied to other control boards. For example, when the memory board is connected to the sub-integrated board 58 or when the memory board is connected to the illumination lamp 63, the control device having the structure in which the memory board is connected to the board having a controller such as a CPU is used. The invention can be applied.

  In addition, the relay board 100 of the first embodiment is a board for connecting two memory boards to the effect control board 43, but by modifying the structure of the relay board 100, three or more memory boards can be obtained. It can also be connected to the production control board 43. In the first embodiment, the case where the 4 GB first memory board 120 and the 2 GB second memory board 130 are connected to the effect control board 43 has been described. However, memory boards having various capacities such as 6 GB and 8 GB are used. Of course, the present invention can be applied even in such a case. That is, the present invention can be applied when three or more types of memory boards are connected to one control board.

  In addition, the number of connectors for connecting the memory boards included in the effect control boards 43 and 243 is one in the first embodiment and two in the second embodiment, but this number can be changed. . Needless to say, a memory substrate without the first decoding circuits 125, 135, 225, 235 can be used.

  The ID information stored in the ID information storage units 126, 136, 226, and 236 indicates the storage capacity in the first embodiment and the identification number in the second embodiment. The contents and storage mode can be changed as appropriate. When installing a gaming machine in the amusement hall, it is necessary to apply for a number of matters including the type of each board and which board is connected to which connector, etc., only for gaming machines that have been approved. Can be installed in amusement halls. And if you install a different gaming machine than the one you applied for, you will be punished. Here, when a gaming machine is manufactured, etc., the gaming machine may be mistakenly configured with a different type or different connection form from the applied board, but even in this case, the game is normal if the predetermined conditions are matched. To be done. Therefore, by determining the consistency of the memory board using ID information that can finely identify the type of board, it is possible to prevent a gaming machine having a specification different from the application contents from being installed in the game hall. On the other hand, as shown in the first embodiment, if only the ID information indicating the storage capacity is used, it is possible to perform the judgment of consistency and the control according to the storage capacity with a simple configuration. Thus, the content and storage mode of the ID information can be appropriately selected according to the specifications of the gaming machine.

  The operation performed when it is determined that an inappropriate memory board is connected can also be changed. For example, in the first embodiment, only the error display is performed if the capacity of the memory board is different, and when the memory board is removed from the effect control board 43, the error display and the prohibition of the effect by the liquid crystal display device 36 are simultaneously performed. Even if the capacities are different, the production may be prohibited. In the first embodiment, the error display unit 38 is not provided as in the second embodiment, and only the production is prohibited. Further, the error display unit 38 of the first embodiment is configured to display only errors of the effect control board 43, but is shared with a display unit for displaying other errors such as errors of the payout control board 45. Alternatively, the error display may be performed using the speakers 32 and 33, the electric lamp 63, and the like.

  Moreover, the error display part 38 can also be comprised by components other than 7 segment LED, and the content of the error displayed on the error display part 38 can also be changed. For example, in the first embodiment, when it is determined that the ID information of the memory board matches the appropriate memory information of the sub-integrated board 58, all the seven segments in the error display unit 38 are turned on. (S5, see FIG. 6). Thereby, it is possible to determine whether or not 7 segments have failed. However, the display form of the error display unit 38 having seven segments is not limited to this, and other numbers, symbols, and characters may be displayed (see S4, S5, and S10). Further, in the case where display on the liquid crystal display device 36 is possible, a configuration may be adopted in which errors can be distinguished by symbols or characters displayed on the liquid crystal display device 36. In this case, if the display by the liquid crystal display device 36 is performed when it is determined that the memory substrates are aligned, there is a risk of misunderstanding for the player or the like. It is desirable not to perform.

  In the first embodiment, when the identity confirmation mode for confirming the identity of the memory board connected to the effect control board 43 is executed, the memory board is removed from the effect control board 43. In this case, it is determined that the identity cannot be secured, and an error is displayed. However, this operation can be changed. For example, the number of times that the memory board is removed from the effect control board 43 is stored in a storage medium such as a flash ROM, and the number of times of fraudulent acts or connector consumption is determined by reading and checking the number of times. It is also possible to make a judgment.

  Further, in the first embodiment, when a memory board having an appropriate capacity is connected to the effect control board 43, “8” is displayed on the error display section 38, but this can be changed. For example, “6” is displayed on the error display unit 38 if the storage capacity of the appropriate memory substrate to be connected is 6 GB in total, and “4” is displayed on the error display unit 38 if it is 4 GB, thereby indicating that the memory substrate is normal. In addition to the above, the capacity of the memory board may be displayed.

  In the first embodiment, the setting and release of the identity confirmation mode for confirming the identity of the memory board connected to the effect control board 43 is performed by pressing the mode setting button 34 and the mode release button 35. However, this is done by turning on the power to the pachinko machine 1, but this can be changed. For example, a key for setting and canceling the identity confirmation mode is manufactured, and the mode is set and canceled by turning on the power of the pachinko machine 1 while inserting the key into a predetermined key hole and turning it. If so, it is possible to more reliably prevent fraud.

  The gaming machine of the present invention is not limited to a pachinko machine, but can be applied to various gaming machines such as a pachikon machine and a pachislot machine, and its liquid crystal display control device.

It is the perspective view which looked at the state where the front frame 14 and the middle frame 13 of the pachinko machine 1 were opened from diagonally forward. 1 is a front view of a pachinko machine 1. FIG. 2 is a block diagram showing an electrical configuration of the pachinko machine 1. FIG. It is a block diagram showing details of the effect control board 43 and its surrounding control circuit. It is a figure which shows the relationship between ID information input into display control CPU91, and the memory capacity which display control CPU91 recognizes. 10 is a flowchart of a memory board alignment confirmation process performed by the display control CPU 91 of the effect control board 43. It is a block diagram which shows the detail of the presentation control board 243 in the pachinko machine of 2nd embodiment, and its surrounding control circuit. It is a flowchart of the memory board alignment confirmation process performed by display control CPU91 of the pachinko machine of a modification.

DESCRIPTION OF SYMBOLS 1 Pachinko machine 32, 33 Speaker 36 Liquid crystal display device 38 Error display part 41 Main board 43,243 Production control board 46 Illumination board 58 Sub-integrated board 63 Illumination lamp 80 VDP
88, 216, 217 connectors 91, 291 Display control CPU
92 Display control RAM
93 Display control ROM
100 Relay board 101 Second decoding circuit 102 ID information decoding circuit 115, 116, 117 Connector 118, 119, 229, 239 Connector 120, 130, 220, 230 Memory board 126, 136, 226, 236 ID information storage unit 581 CPU
583 ROM

Claims (5)

A main board that controls the main control of the game,
A sub-control board having a connection part connected to another board, receiving a signal transmitted from the main board and controlling the production;
A memory board that is connected to the connection portion of the sub control board and stores data used by the sub control board and includes ID information storage means for storing ID information for identifying the type of the board ;
Appropriate memory information storage means for storing in advance information on the appropriate memory substrate connected to the connection unit;
Using the information stored in the appropriate memory information storage means and the ID information stored in the ID information storage means, the appropriate information that matches the information stored in the appropriate memory information storage means Memory substrate alignment determining means for determining whether a memory substrate is connected to the connection unit;
Non-matching operation control means for controlling a predetermined operation performed when the memory board matching judgment means judges that the appropriate memory board is not connected ;
A relay board for connecting the connection portion of the sub-control board and a plurality of the memory boards;
The ID information storage means stores at least ID information indicating a storage capacity of the memory board,
The relay board is
A gaming machine comprising: a decoding circuit that generates a signal for selecting one of the plurality of memory boards using the ID information . An error display means for notifying that the appropriate memory board is not connected to the sub-control board;
The non-matching operation control means controls the error display means to display an error when the memory board matching judgment means judges that the appropriate memory board is not connected. The gaming machine according to claim 1. Production control prohibiting means for prohibiting production control by the sub-control board,
The operation control means at the time of inconsistency controls the effect control prohibiting means to control the effect by the sub control board when the memory substrate alignment determining means determines that the appropriate memory substrate is not connected. The gaming machine according to claim 1, wherein the gaming machine is prohibited. A memory board connection detecting means for detecting whether or not the memory board is continuously connected to the connection portion of the sub-control board;
The memory substrate alignment determining unit determines that the appropriate memory substrate is not connected to the connection unit when the memory substrate connection detecting unit determines that the memory substrate is not continuously connected. The gaming machine according to any one of claims 1 to 3 , characterized in that The memory board, gaming machine according to any of claims 1 to 4, comprising the ID information display unit for displaying the ID information for identifying a type of the substrate.

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