JP4584075B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device having a semiconductor element.

  2. Description of the Related Art Conventionally, a so-called active matrix driving display panel or semiconductor integrated circuit including a thin film transistor (hereinafter also referred to as “TFT”) or a semiconductor element typified by a MOS transistor has a light exposure process using a photomask ( Hereinafter, it is manufactured by forming a resist mask by a photolithography process and selectively etching various thin films.

  In the photolithography process, a resist is applied to the entire surface of the substrate and pre-baked, and then the resist is exposed to ultraviolet rays and the like through a photomask, and developed to form a resist mask. Thereafter, using the resist mask as a mask, a thin film (thin film formed of a semiconductor material, an insulator material, or a conductor material) existing in a region other than a semiconductor region or a portion to be a wiring is removed by etching to remove the semiconductor region or Wiring is formed.

In addition, in order to reduce the loss of raw materials required for film formation, a technique for forming a film on a semiconductor wafer using a device capable of forming a linear pattern with a small diameter by continuously discharging a resist from a nozzle is patented. It is described in Document 1.
JP 2000-188251 A

  However, when a semiconductor region having a desired shape is formed by etching a semiconductor film using a conventional photolithography process, a resist is applied to the surface of the semiconductor film. At this time, since the surface of the semiconductor film is directly exposed to the resist, there is a problem that the semiconductor film is contaminated by impurities such as oxygen, carbon, and heavy metal elements contained in the resist. Due to this contamination, impurity elements are mixed in the semiconductor film, and the characteristics of the semiconductor element are deteriorated. In particular, TFTs have a problem of causing variation and deterioration in transistor characteristics.

  In addition, in the process of forming a wiring and a semiconductor region using a photolithography process, most of the wiring, the semiconductor film, and the resist material are wasted, and the number of processes for forming the wiring and the semiconductor region is large, and the throughput is increased. Decreases.

In addition, it is difficult for an exposure apparatus used in the photolithography process to perform exposure processing on a large area substrate at a time. For this reason, in a method for manufacturing a semiconductor device using a large-area substrate, a plurality of exposure times are required, and there is a problem in that yield is reduced due to mismatch between adjacent patterns.

  Furthermore, in order to form a fine semiconductor element having a small occupation area by a droplet discharge method, it is necessary to discharge a raw material solution having a small droplet diameter. For this purpose, it is only necessary to reduce the diameter of the discharge port. In this case, the composition of the raw material solution adheres to the tip of the discharge port, dries, and solidifies, resulting in clogging and the like. Is difficult to discharge continuously and stably. As a result, there is a problem in that the throughput and yield of a semiconductor device formed with the semiconductor element are reduced.

  The present invention has been made in view of such a situation, and provides a method for forming a semiconductor element having a semiconductor region with a fine structure without using a resist. In addition, a manufacturing method of a semiconductor device capable of reducing cost with a small number of steps is provided. In addition, a manufacturing method of a semiconductor device capable of reducing cost by reducing raw materials is provided. Further, a method for manufacturing a semiconductor device which can improve throughput and has high mass productivity is provided. In addition, a method for manufacturing a semiconductor device with little variation is provided.

    The gist of the present invention is to form a semiconductor region having a desired shape by irradiating a part of a semiconductor film with laser light to form an insulating layer and then etching the semiconductor film using the insulating layer as a mask. .

  In addition, the gist of the present invention is to form a semiconductor element having a semiconductor region having the desired shape and a semiconductor device formed of the semiconductor element.

  The insulating layer formed on the semiconductor film is a silicon oxide film in which the surface of the semiconductor film is oxidized. The insulating layer and the semiconductor film can have a selection ratio in an etching step, and the semiconductor film can be selectively etched using the insulating layer as a mask.

As a method for etching a semiconductor film, a dry etching method or a wet etching method can be given. As a dry etching method, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , SF ₆ , NF ₃ , CHF ₃ , ClF ₃ , or the like, or Etching can be performed using O ₂ . As the wet etching method, etching can be performed using an alkaline solution such as hydrazine or an aqueous solution containing tetramethylammonium hydroxide (TMAH, chemical formula: (CH ₃ ) ₄ NOH.

  In addition, a semiconductor region having an arbitrary width can be formed by appropriately controlling the width of the laser beam spot. Therefore, by using a laser beam drawing apparatus or the like and irradiating a semiconductor film with a laser beam having a narrow beam spot width, a semiconductor region having a narrow width and a fine shape (typically, a width of 20 μm or less, preferably , 0.5 to 15 μm). Since a semiconductor element having such a semiconductor region occupies a small area, a semiconductor device integrated with high density can be manufactured.

  Another embodiment of the present invention is a semiconductor device including a semiconductor element including the semiconductor region as an active layer. Examples of the semiconductor element include a TFT, a memory element, a diode, a photoelectric conversion element, a capacitor element, and a resistance element. Examples of the TFT include a forward stagger type TFT, an inverted stagger type TFT (channel etch type TFT or channel protection type TFT), a bottom gate TFT, and a coplanar type TFT such as a top gate TFT.

  In the present invention, examples of the semiconductor device include an integrated circuit including a semiconductor element, a display device, a wireless tag, and an IC tag. Typical examples of the display device include a liquid crystal display device, a light emitting display device, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Display). And display devices such as electrophoretic display devices (electronic paper).

  In the present invention, the display device refers to a device using a display element, that is, an image display device. In addition, a connector, for example, a module in which a flexible printed wiring (FPC), TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package) is attached to the display panel, a printed wiring board at the end of the TAB tape or TCP is provided. It is assumed that the display device includes all provided modules or modules in which an IC (Integrated Circuit) or a CPU is directly mounted on a display element by a COG (Chip On Glass) method.

  In the present invention, a part of the semiconductor film can be irradiated with laser light, an insulating layer can be formed in an arbitrary region, and the semiconductor film can be etched using the insulating layer as a mask. For this reason, it is possible to form a semiconductor region having a desired shape at a predetermined place without using a photolithography process using a known resist.

  Further, by reducing the spot diameter of the laser beam, the irradiation area of the laser beam can be reduced. In particular, by using a laser beam drawing apparatus, a predetermined place can be irradiated with laser light having a fine beam spot. For this reason, an insulating layer having a fine shape can be formed. In addition, a fine-shaped semiconductor region can be formed using a fine-shaped insulating layer as a mask.

  Therefore, it is possible to form a semiconductor element with a fine shape while avoiding the mixing of an impurity element into the semiconductor film by resist coating, and a highly integrated semiconductor device with little variation can be manufactured. Is possible. In addition, since a semiconductor region having a desired shape can be formed without going through a photolithography process using a resist, the number of steps can be reduced and raw materials can be reduced. As a result, cost reduction is possible.

In addition, when forming a semiconductor region, wiring, or the like, by using a droplet discharge method, a relative position between a nozzle that is a droplet discharge port including the material of those films and a substrate is changed. Droplets can be ejected at any location. Further, the thickness and thickness of the film pattern to be formed can be adjusted by the relative relationship between the nozzle diameter, the droplet discharge amount, and the moving speed between the nozzle and the substrate on which the discharge is formed. Therefore, a film pattern can be accurately formed at a desired location even on a large-area substrate having a side exceeding 1 to 2 m. In addition, since there is no mismatch between adjacent film patterns, the yield can be improved. As a result, a semiconductor device can be manufactured with a small number of steps and high yield.

  Furthermore, a liquid crystal television and an EL television each including the semiconductor device formed by the above manufacturing process can be manufactured at low cost.

  The best mode for carrying out the invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the embodiment modes. In the drawings, common portions are denoted by the same reference numerals, and detailed description thereof is omitted.

(Embodiment 1)
In this embodiment mode, a process for forming a semiconductor region having a desired shape by irradiation with a laser beam (hereinafter also referred to as laser light) will be described with reference to FIGS.

  As shown in FIG. 1, a first insulating layer 102 is formed over a substrate 101, and a semiconductor film 103 is formed over the first insulating layer. At this time, when the surface of the semiconductor film 103 is exposed to oxygen, the surface of the semiconductor film is oxidized and the second insulating layer 104 is formed. Note that the second insulating layer 104 formed by oxidizing the surface of the semiconductor film in this manner is also called a natural oxide film.

  As the substrate 101, a glass substrate, a quartz substrate, a substrate formed of an insulating material such as ceramic such as alumina, a plastic substrate, a silicon wafer, a metal plate, or the like can be used. When the substrate 101 is a glass substrate, a large area substrate such as 320 mm × 400 mm, 370 mm × 470 mm, 550 mm × 650 mm, 600 mm × 720 mm, 680 mm × 880 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, 1150 mm × 1300 mm should be used. Can do.

  Representative examples of plastic substrates include PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PES (polyethersulfone sulfone), polypropylene, polypropylene sulfide, polycarbonate, polyetherimide, polyphenylene sulfide, polyphenylene oxide, polysulfone, or polyphenylene. Examples thereof include a plastic substrate made of taramide and a substrate formed of an organic material in which inorganic particles having a diameter of several nm are dispersed. Further, the surface of the substrate does not have to be flat, and may have irregularities or curved surfaces.

  The first insulating layer 102 is formed with a single layer or a stacked structure of an insulating film containing silicon nitride, silicon oxide, or other silicon by a thin film formation method such as a plasma CVD method or a sputtering method. In addition, from the viewpoint of the blocking effect of impurities from the substrate and the interface characteristics between the first insulating layer 102 and the semiconductor region, a silicon nitride film (silicon nitride oxide film), oxidized from the side in contact with the substrate. A stacked structure of a silicon film and a silicon nitride film (silicon nitride oxide film) is preferable.

  As the semiconductor film 103, an amorphous semiconductor, a semi-amorphous semiconductor in which an amorphous state and a crystalline state are mixed (also referred to as SAS), and crystal grains of 0.5 nm to 20 nm are observed in the amorphous semiconductor. A film having any state selected from microcrystalline semiconductors that can be formed is formed. In particular, a microcrystalline state in which grains of 0.5 nm to 20 nm can be observed is called a so-called microcrystal (μc).

  The semiconductor film can be formed using silicon, silicon germanium (SiGe), or the like as a main component. In addition to the main component, an acceptor element or a donor element such as phosphorus, arsenic, or boron may be included. The film thickness of the semiconductor film is 10 to 150 nm, preferably 30 to 70 nm.

  The second insulating layer 104 is a silicon oxide film formed by allowing a semiconductor film to come into contact with oxygen in the atmosphere and react. Therefore, the thickness of the second insulating layer 104 is thin, typically 5 to 15 nm, preferably 10 nm.

  Next, as illustrated in FIG. 1B, the semiconductor film 103 is irradiated with laser light 111, so that a third insulating layer 121 illustrated in FIG. 1C is partially formed. Here, the second insulating layer 104 is irradiated with the laser beam 111 using a laser beam drawing apparatus or a laser beam direct drawing apparatus. At this time, in the region irradiated with the laser light, the second insulating layer and the semiconductor film are oxidized by the energy of the laser light, and the third insulating layer 121 is formed. Note that the third insulating layer 121 is a region where the thickness of part of the second insulating layer is increased.

  The region that is not irradiated with the laser beam 111 remains as the second insulating layer. The second insulating layer exposed around the third insulating layer is referred to as a fourth insulating layer 122. The atmosphere at the time of laser light irradiation is an oxygen atmosphere or an air atmosphere.

  The third insulating layer 121 is formed of an oxide layer, and is typically a semiconductor oxide layer. The thickness of the third insulating layer 121 is preferably twice or more the thickness of the second insulating layer 104. The third insulating layer 121 is preferably a dense insulating layer, and has an etching rate lower than that of the second insulating layer 104. Typically, the third insulating layer 121 is an insulating layer whose etching rate is half or less. Is preferred.

  Note that it is preferable to reduce the hydrogen concentration in the semiconductor film 103 before the second insulating layer is irradiated with laser light. Typically, a semiconductor film is formed by reducing the hydrogen concentration. Alternatively, hydrogen may be extracted by heating the semiconductor film 103. By reducing the hydrogen concentration or dehydrogenating, it is possible to reduce the desorption of hydrogen that occurs when the semiconductor film is irradiated with laser light and the resulting surface roughness of the semiconductor film.

  Here, a laser beam direct writing apparatus will be described with reference to FIG. As shown in the figure, a laser beam direct drawing apparatus 1001 includes a personal computer (hereinafter referred to as a PC) 1002 that executes various controls when irradiating a laser beam, a laser oscillator 1003 that outputs a laser beam, and a laser. A power source 1004 of the oscillator 1003, an optical system (ND filter) 1005 for attenuating the laser beam, an acousto-optic modulator (AOM) 1006 for modulating the intensity of the laser beam, and an enlargement or reduction of the cross section of the laser beam An optical system 1007 composed of a lens for changing the optical path, a mirror for changing the optical path, etc., a substrate moving mechanism 1009 having an X stage and a Y stage, and D / D for digital-to-analog conversion of control data output from the PC Acoustic light according to the analog voltage output from the A converter 1010 and the D / A converter A driver 1011 for controlling the modulator 1006, and a driver 1012 for outputting a driving signal for driving the substrate moving mechanism 1009.

As the laser oscillator 1003, a laser oscillator that can oscillate ultraviolet light, visible light, or infrared light can be used. Laser oscillators include excimer laser oscillators such as KrF, ArF, XeCl, and Xe, gas laser oscillators such as He, He—Cd, Ar, He—Ne, and HF, and crystals such as YAG, YVO ₄ , YLF, and YAlO _3. A solid-state laser oscillator using a crystal doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm, or a semiconductor laser oscillator such as GaN, GaAs, GaAlAs, or InGaAsP can be used. In the solid-state laser oscillator, it is preferable to apply the second to fifth harmonics of the fundamental wave.

  Next, a laser beam irradiation method using a laser beam direct drawing apparatus will be described. When the substrate 1008 is mounted on the substrate moving mechanism 1009, the PC 1002 detects the position of the marker attached to the substrate by the camera. Next, the PC 1002 generates movement data for moving the substrate movement mechanism 1009 based on the detected marker position data and drawing pattern data input in advance. Thereafter, the PC 1002 controls the output light amount of the acousto-optic modulator 1006 via the driver 1011, so that the laser beam output from the laser oscillator 1003 is attenuated by the optical system 1005 and is predetermined by the acousto-optic modulator 1006. To control the amount of light. On the other hand, the optical path and the beam shape of the laser beam output from the acousto-optic modulator 1006 are changed by the optical system 1007 and condensed by the lens, and then irradiated on the composition (first pattern) on the substrate. To do. At this time, according to the movement data generated by the PC 1002, the movement of the substrate moving mechanism 1009 is controlled in the X direction and the Y direction. As a result, the laser beam is irradiated to a predetermined place, and the third insulating layer 121 is formed.

  Here, the laser beam is irradiated by scanning the laser beam in the X and Y axis directions. In this case, it is preferable to use a polygon mirror, a galvanometer mirror, or an acousto-optic deflector (AOD) for the optical system 1007. Alternatively, the third insulating layer may be formed in a predetermined region of the substrate by moving the laser beam in one direction of the X axis or the Y axis and moving the substrate in the other direction of the X axis or the Y axis.

  Here, the third insulating layer is formed in the region irradiated with the laser beam. For this reason, when the laser beam is irradiated once, the width of the third insulating layer is approximately the width of the beam spot. In order to form the third insulating layer with a finer width, it is preferable to irradiate a laser beam with a lower wavelength. In this embodiment mode, a laser beam having any wavelength of ultraviolet light or infrared light is used. As a result, the width of the beam spot can be reduced.

  Further, the third insulating layer 121 functions as a mask for partially etching the semiconductor film 103 later. For this reason, it is possible to form a semiconductor element with a small shape and a small occupation area by irradiating the laser beam 111 with a narrow beam spot width. The width of the beam spot at this time is preferably 20 μm or less, more preferably 0.5 to 15 μm. By forming an insulating layer functioning as a mask using a spot having such a width, a semiconductor device in which semiconductor elements are integrated at high density can be formed.

  On the other hand, when forming a mask for forming a relatively large area such as a pixel electrode or wiring, the beam spot width is preferably large. By forming an insulating layer functioning as such a mask, throughput can be improved.

  The intensity of the laser beam spot shows a Gaussian distribution 180 as shown in FIG. The Gaussian distribution has an apex that is wide and narrow with respect to the beam spot width of the laser light. FIG. 25B shows a top view of the substrate when the third insulating layer is formed by scanning such a laser beam spot in one direction.

  As shown in FIG. 25B, when the semiconductor film is irradiated with laser light having a Gaussian intensity, a third insulating layer 181 having a curved end is formed. Note that a region surrounded by a broken line is a region of the third insulating layer 181. In addition, a fourth insulating layer 122 that is a natural oxide film is formed around the third insulating layer 181. After the fourth insulating layer 122 is removed, the semiconductor film is etched by a subsequent process using the third insulating layer 181 having such a shape as a mask, and the mask is removed, so that FIG. Such a semiconductor region 182 having a curved end, typically a continuously repeated curved region, can be formed.

  On the other hand, in addition to the optical system 1007 of the laser beam direct drawing apparatus of FIG. 22, a wavefront conversion optical element can be used so that the intensity of the laser beam spot is trapezoidal or rectangular parallelepiped (top flat type). . By using the wavefront converting optical element, as shown in FIG. 26A, the intensity of the beam spot of the laser light is trapezoidal or rectangular parallelepiped. For this reason, the energy intensity at the beam spot of the laser beam is constant (top flat type). FIG. 26B shows a top view of the substrate when the third insulating layer is formed by scanning such a laser beam spot in one direction.

  In FIG. 26B, when a laser beam having trapezoidal or rectangular parallelepiped intensity is irradiated, a third insulating layer 191 having a linear end is formed. Note that a region surrounded by a broken line is a region of the third insulating layer 191. A fourth insulating layer 122 that is a natural oxide film is formed around the third insulating layer 191. After the fourth insulating layer 122 is removed, the semiconductor film is etched by a subsequent process using the third insulating layer 191 having such a shape as a mask, and the mask is removed, so that FIG. Such a semiconductor region 192 having a linear end portion can be formed.

  Typical examples of the wavefront converting optical element include a diffractive optical element, a refractive optical element, a reflective optical element, and an optical waveguide. Typical examples of the diffractive optical element include a holographic optical element and a binary optical element. An optical waveguide condenses radiated light in a certain region and guides and transmits the energy flow parallel to the axis of the path. A light pipe or an optical fiber can be used as the optical waveguide. The light pipe is usually used to send light from one end to the other end by reflection, and is drawn out into a shape such as a cone, a pyramid, a cylinder, or a prism. In addition, light transmission includes reflection by a mirror and one having two reflection surfaces facing each other. The laser beam incident on the optical waveguide is repeatedly reflected in the optical waveguide and reaches the exit. A surface having a uniform light energy density distribution is formed at the beam spot at the exit of the optical waveguide.

  In addition, when the laser beam spot is not scanned but irradiated to one place, a third insulating layer depending on the shape of the beam spot can be formed. Using such a third insulating layer as a mask, the semiconductor film is etched in a later process, the first insulating layer is exposed, and the mask is removed to form a circular, elliptical, or rectangular semiconductor region. It is possible to form.

  In addition, the laser beam 111 is activated so that the surfaces of the semiconductor film 103 and the second insulating layer 104 are activated and easily react to each other, so that the insulating layer is formed between the semiconductor film and the second insulating layer. It is preferable to control. As a result, the semiconductor film 103 after irradiation with the laser light is not completely melted and is an amorphous semiconductor film, SAS, or μc.

  Next, as shown in FIG. 1D, the fourth insulating layer 122 is removed, and a part of the semiconductor film is exposed, so that the third insulating layer remains on the semiconductor film.

  As a method for removing the fourth insulating layer 122, a known method such as wet etching or dry etching is used. At this time, etching conditions are controlled as appropriate so that the third insulating layer 121 remains.

Next, as shown in FIG. 1E, the semiconductor film 103 can be etched using the third insulating layer 121 as a mask to form a semiconductor region 132 having a desired shape. Examples of the etching method of the semiconductor film 103 include a dry etching method and a wet etching method. As a dry etching method, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , SF ₆ , NF ₃ , CHF ₃ , ClF ₃ , or the like, or Etching can be performed using O ₂ . As a wet etching method, etching can be performed using an alkaline solution such as an aqueous solution containing hydrazine or tetramethylammonium hydroxide (TMAH, chemical formula: (CH ₃ ) ₄ NOH).

  Through the above steps, a semiconductor region having a fine shape can be formed without using a resist.

(Embodiment 2)
In this embodiment mode, a process for forming a semiconductor region having a desired shape by a process different from that in Embodiment Mode 1 is described with reference to FIGS. In the present embodiment, the order of the second insulating layer removing step and the third insulating layer forming step is different from that of the first embodiment.

  As shown in FIG. 2A, as in Embodiment 1, a first insulating layer 102 is formed over a substrate 101, and a semiconductor film 103 is formed over the first insulating layer. At this time, the semiconductor film is oxidized on the surface of the semiconductor film 103, and the second insulating layer 104 is formed.

  Next, as shown in FIG. 2B, the second insulating layer 104 is removed by a wet etching method, a dry etching method, or the like, so that the semiconductor film 103 is exposed.

  Next, as shown in FIG. 2C, a part of the semiconductor film 103 is irradiated with the laser light 111 in the same manner as in Embodiment Mode 1, and as shown in FIG. Then, a third insulating layer 141 is formed. Here, since the laser beam emitted from the laser beam direct writing apparatus is irradiated, it is possible to irradiate the laser beam having a minute beam diameter. For this reason, the third insulating layer 141 also has a fine shape.

  The third insulating layer 141 is formed using an oxide layer, and is typically a semiconductor oxide layer. The thickness of the third insulating layer 141 is preferably twice or more than the thickness of the second insulating layer 104 in order to function as a mask for etching the semiconductor film 103 later. The third insulating layer 141 is preferably a dense insulating layer and preferably has an etching rate lower than that of the second insulating layer. Typically, the third insulating layer 141 is an insulating layer having an etching rate of half or less. .

  Next, as illustrated in FIG. 2E, the semiconductor region 103 is formed by etching the semiconductor film 103 using the third insulating layer 141 as a mask.

  Through the above steps, a semiconductor region having a fine shape can be formed without using a resist.

(Embodiment 3)
In this embodiment mode, a process for forming a semiconductor region having a different crystal state from that in Embodiment Mode 1 or 2 will be described with reference to FIGS. Note that although this embodiment mode is described using the process order of Embodiment Mode 1, the process order of Embodiment Mode 2 can also be used.

  As shown in FIG. 3A, as in Embodiment 1, a first insulating layer 102 is formed over a substrate 101, and a semiconductor film 103 is formed over the first insulating layer. At this time, the semiconductor film is oxidized on the surface of the semiconductor film 103, and the second insulating layer 104 is formed.

  Next, as illustrated in FIG. 3B, a part of the second insulating layer 104 is irradiated with a laser beam 151. Here, since the laser beam emitted from the laser beam direct writing apparatus is irradiated, it is possible to irradiate the laser beam having a minute beam diameter. At this time, by controlling the intensity of the laser light, the region irradiated with the laser light in the semiconductor film 103 is melted. Further, an unmelted semiconductor film 153 remains around the melted semiconductor film region 152.

  After that, by naturally cooling the melted semiconductor, as shown in FIG. 3C, the semiconductor film is oxidized and the third insulating layer 162 is formed by irradiation with laser light, and has crystallinity. A semiconductor region 161 is formed. The third insulating layer 162 is formed using an oxide layer, and is typically a semiconductor oxide layer.

  Further, the second insulating layer remains around the third insulating layer 162. Here, the second insulating layer remaining around the third insulating layer 162 is referred to as a fourth insulating layer 163. Here, the thickness of the third insulating layer 162 is preferably twice or more the thickness of the fourth insulating layer 163. The third insulating layer 162 is preferably a dense insulating layer, and has an etching rate lower than that of the second insulating layer. Typically, the third insulating layer 162 is an insulating layer having an etching rate of half or less. preferable.

  Next, as illustrated in FIG. 3D, the fourth insulating layer 163 is removed by a wet etching method, a dry etching method, or the like, so that the semiconductor film 103 is exposed. Through this step, the third insulating layer 162 functioning as a mask can be formed. Note that etching conditions are controlled as appropriate so that the third insulating layer 162 remains.

  Next, as illustrated in FIG. 3E, the semiconductor film 103 is etched using the third insulating layer 162 as a mask, so that a semiconductor region 171 having a desired shape is formed. As a method for etching the semiconductor film 103, dry etching, wet etching, or the like described in Embodiment 1 is used as appropriate. Here, etching is performed using the third insulating layer 162 as a mask, so that the semiconductor region 171 having crystallinity remains.

  Through the above steps, a semiconductor region having a fine shape and crystallinity can be formed without using a resist.

(Embodiment 4)
In this embodiment, a method for manufacturing a semiconductor element will be described with reference to FIGS. In this embodiment mode, a channel etch type TFT of an inverted stagger type TFT is described as a typical example of a semiconductor element. In the following fourth to seventh embodiments, a process for forming a semiconductor element using the second embodiment will be described. However, the present invention is not limited to this, and the first embodiment or the third embodiment is appropriately used. It is possible to use.

  As shown in FIG. 4A, a first conductive layer 202 is formed over a substrate 201. The first conductive layer 202 is made of metal such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, and Ba. Alternatively, ITO (indium tin oxide) used as a metal nitride or transparent conductive film, ITO having silicon oxide as a composition, organic indium, organic tin, zinc oxide (ZnO), or the like is appropriately selected and formed. As a method for forming the first conductive layer 202, a droplet discharge method, a printing method, an electroplating method, a PVD method, or a CVD method is appropriately selected.

  When the u-th conductive layer is formed using the PVD method or the CVD method, the photosensitive material is dropped by a droplet discharge method, or exposure and development of the photosensitive material using a photolithography process or a laser beam direct drawing apparatus. Then, a mask is formed over the conductive film, and the conductive film is etched into a desired shape using the mask to form a first conductive layer.

  In the case where the first conductive layer is formed by a droplet discharge method, a composition in which the metal particles are dissolved or dispersed in an organic resin is discharged from a discharge port (hereinafter referred to as a nozzle). As the organic resin, one or more selected from organic resins that function as a binder of metal particles, a solvent, a dispersant, and a coating agent can be used. Typically, known organic resins such as polyimide, acrylic, novolac resin, melamine resin, phenol resin, epoxy resin, silicon resin, furan resin, diallyl phthalate resin, and the like can be given.

  The viscosity of the composition is preferably 5 to 20 mPa · s, which is to prevent the drying from occurring and to smoothly discharge the metal particles from the discharge port. The surface tension is preferably 40 mN / m or less. Note that the viscosity of the composition may be appropriately adjusted according to the solvent to be used and the application.

  The diameter of the metal particles contained in the composition depends on the diameter of each nozzle, a desired pattern shape, etc., but is preferably as small as possible for preventing nozzle clogging and producing a high-definition pattern, and preferably A particle size of 0.1 μm or less is preferred. The metal particles are formed by a known method such as an electrolytic method, an atomizing method, or a wet reduction method, and the particle size is generally about 0.5 nm to 10 μm. However, when formed by a gas evaporation method, the nanomolecule protected by the dispersant is as fine as about 7 nm. Further, when the surface of each particle is covered with a coating agent, the nanoparticle does not aggregate in the solvent, is stably dispersed at room temperature, and exhibits almost the same behavior as a liquid.

  The step of discharging the composition may be performed under reduced pressure. This is because the organic resin of the composition is volatilized before the composition is discharged and landed on the object to be processed, and the energy density of the laser beam can be weakened in the process of firing the metal particles. is there.

  In the present embodiment, by using a droplet discharge method, an Ag paste in which silver particles of several nm are dispersed is selectively discharged onto the substrate 201 and fired, whereby the first silver particles are fired. A conductive layer 202 is formed. The first conductive layer 202 is formed by irregularly overlapping fine particles, which are conductors, three-dimensionally. That is, it is composed of three-dimensional aggregate particles. For this reason, the surface has fine unevenness. Further, since the fine particles are fired and the particle size of the particles is increased depending on the heating temperature and time of the first conductive layer 202, the layer has a large surface height difference. The region where the fine particles are melted may have a polycrystalline structure. In this case, an etching process using a mask pattern is not necessary, so that the manufacturing process can be greatly simplified.

  Next, a first insulating layer 221 functioning as a gate insulating film, a first semiconductor film 222, and a conductive second semiconductor film 223 are formed over the first conductive layer 202.

  The first insulating layer 221 is formed using a single layer or a stacked structure of an insulating film containing silicon nitride, silicon oxide, or other silicon by a thin film formation method such as a plasma CVD method or a sputtering method. The first insulating layer preferably has a stacked structure of a silicon nitride film (silicon nitride oxide film), a silicon oxide film, and a silicon nitride film (silicon nitride oxide film) from the side in contact with the first conductive layer. . In this structure, since the gate electrode is in contact with the silicon nitride film, deterioration due to oxidation can be prevented.

  The first semiconductor film 222 is formed using a film having any state selected from an amorphous semiconductor, SAS, μc, and a crystalline semiconductor. In any case, silicon, silicon germanium (SiGe) or the like is the main component, and the film thickness is preferably 10 to 100, more preferably 20 to 60 nm.

  The crystalline semiconductor film can be formed by crystallizing an amorphous semiconductor film or SAS by heating or laser irradiation. Alternatively, a crystalline semiconductor film may be directly formed.

  Further, on the amorphous semiconductor film, titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), zirconium (Zr), tantalum (Ta), vanadium (V). Alternatively, a crystalline semiconductor film may be formed by adding a metal catalyst such as niobium (Nb), chromium (Cr), platinum (Pt), palladium (Pd) and heating. However, when the crystalline semiconductor film is formed by this method, it is preferable to remove the metal catalyst in a later step. As this removal method, a method of adding an impurity (typically argon, phosphorus, or a rare gas) to a part of the crystalline semiconductor film and heating to move the catalytic element to a region to which the impurity is added, There is a method of forming a semiconductor film having the above-described impurities on the surface of the crystalline semiconductor film and heating to move the catalytic element to the semiconductor film having impurities.

  The second semiconductor film 223 is formed using a conductive amorphous semiconductor, SAS, and μc. In the case of forming an n-channel TFT, a Group 15 element, typically phosphorus or arsenic is added. In the case of forming a p-channel TFT, an element belonging to Group 13, typically boron, is added. The second semiconductor film is formed by a plasma CVD method in which a gas containing a group 13 or group 15 element such as boron, phosphorus, or arsenic is added to a silicide gas.

  Next, after the oxide film formed on the surface of the second semiconductor film 223 is removed, a part of the second semiconductor film is irradiated with laser light 224. Here, laser light emitted from a laser beam direct writing apparatus is used. As a result, a second insulating layer 231 is formed as shown in FIG. Here, part of the second semiconductor film 223 is oxidized by the energy of laser light, and a silicon oxide film is formed as the second insulating layer. In addition, the second semiconductor film is not completely melted and is an amorphous semiconductor, SAS, or μc.

  Next, as illustrated in FIG. 4C, the second semiconductor film 223 is etched using the second insulating layer 231 as a mask to form a second semiconductor region 232. Next, the first semiconductor film 222 is etched using the second insulating layer 231 to form the first semiconductor region 233. Thereafter, the second insulating layer 231 is removed.

  The first semiconductor film and the second semiconductor film can be etched as appropriate by using the etching method for the first semiconductor film described in Embodiment 1.

  Next, second conductive layers 241 and 242 functioning as a source electrode and a drain electrode are formed over the second semiconductor region 232 using a conductive material. For the second conductive layers 241 and 242, the material and the formation method of the first conductive layer described as the first conductive layer 202 in this embodiment can be used as appropriate. Here, a solution Ag paste in which silver particles of several nm are dispersed is selectively discharged and baked to form second conductive layers 241 and 242.

  Next, using the second conductive layers 241 and 242 as masks, the exposed portions of the second semiconductor region 232 are etched and divided to form third semiconductor regions 251 and 252 that function as a source region and a drain region. . In this step, the first semiconductor region 233 partially etched is referred to as a fourth semiconductor region 253. The fourth semiconductor region 253 functions as a channel region.

  Note that in the case where the fourth semiconductor region is formed using a SAS or a crystalline semiconductor film, the third semiconductor region that functions as a source region and a drain region functions as a gate electrode as in this embodiment. In addition to the structure covering one conductive layer, a so-called self-aligned structure in which the end portion of the third semiconductor region and the end portion of the first conductive layer coincide with each other can be employed. Furthermore, the third semiconductor region can be formed so as not to cover the first conductive layer and to be spaced apart from each other. In this structure, off-state current can be reduced, so that contrast can be improved when the TFT is used as a switching element of a display device. Further, a TFT having a so-called multi-gate electrode structure in which the fourth semiconductor region covers the plurality of first conductive layers may be used. Also in this case, the off current can be reduced.

  Next, a passivation film is preferably formed over the second conductive layers 241 and 242 and the third semiconductor region 253. The passivation film is formed using a thin film formation method such as plasma CVD or sputtering, and silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxynitride, or aluminum oxide, diamond-like carbon (DLC), nitrogen-containing carbon (CN) and other insulating materials can be used.

  Through the above steps, a channel-etched TFT having a finely shaped semiconductor region can be manufactured. In addition, a highly integrated semiconductor device with little variation can be manufactured.

(Embodiment 5)
In this embodiment mode, a channel protection type TFT in a bottom gate TFT as a semiconductor element will be described with reference to FIG.

  As shown in FIG. 5A, a first conductive layer 202 functioning as a gate electrode is formed over a substrate 201 by a process similar to that in Embodiment 4, and then a first insulating layer functioning as a gate insulating film. 221 and a first semiconductor film 222 are formed. Next, a protective film 301 is formed over the first semiconductor film 222 and in a region overlapping with the first conductive layer 202.

  The protective film 301 is preferably formed using a heat-resistant polymer material, and a liquid polymer material having an aromatic ring and a heterocyclic ring as a main chain, a small aliphatic portion, and a highly polar heteroatom group is used as a liquid. It is preferable to form by discharging droplets. Typical examples of such a polymer material include polyimide and polybenzimidazole. In the case of using polyimide, a solution containing polyimide can be discharged from the discharge port onto the first semiconductor film 222 and baked at 200 ° C. for 30 minutes.

  Next, a second semiconductor film (a semiconductor film having conductivity) 323 is formed. Note that the second semiconductor film 323 can be formed using a material and a manufacturing method similar to those of the second semiconductor film 223 of Embodiment 2.

  Next, after removing the oxide film formed on the surface of the second semiconductor film 323, a part of the second semiconductor film 323 is irradiated with laser light 224. Here, laser light emitted from a laser beam direct writing apparatus is used. As a result, as shown in FIG. 5B, a second insulating layer 331 is formed. Here, part of the second semiconductor film 323 is oxidized by the energy of laser light, and a silicon oxide film is formed as the second insulating layer.

  Next, as illustrated in FIG. 5C, the second semiconductor film 323 is etched using the second insulating layer 331 as a mask to form a first semiconductor region 332. Next, the second semiconductor region 233 is formed by etching the first semiconductor film 222 using the second insulating layer 331 by a method similar to that in Embodiment 4. Thereafter, the second insulating layer 331 is removed.

  Next, as illustrated in FIG. 5D, the second conductive layer 341 is formed using a conductive material. As the second conductive layer 341, the material and method described for the first conductive layer 202 described in Embodiment 4 are used as appropriate. Here, the second conductive layer 341 formed with a stacked structure of a molybdenum film, an aluminum film, and a molybdenum film is formed by a sputtering method.

  Next, the photosensitive material 342 is discharged or applied onto the second conductive layer 341 and then dried. As the photosensitive material, a negative photosensitive material or a positive photosensitive material that is sensitive from ultraviolet light to infrared light is used.

  As the photosensitive material, a resin material having photosensitivity such as an epoxy resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin is used. In addition, organic materials having photosensitivity such as benzocyclobutene, parylene, and polyimide can be used. In addition, a typical positive photosensitive material includes a photosensitive material having a novolak resin and a naphthoquinonediazide compound as a photosensitive agent, and representative negative photosensitive materials include a base resin, diphenylsilanediol, and an acid generator. And a photosensitive material having an agent. In the present embodiment, a negative photosensitive material is used.

  Next, the photosensitive material 342 is irradiated with a laser beam 343 using a laser beam direct drawing apparatus, exposed, and then developed. As a result, a mask 351 as shown in FIG. 5E is formed.

  Next, as illustrated in FIG. 5F, the second conductive layer is etched using a mask 351 to form a third conductive layer 352 functioning as a source electrode and a drain electrode. In addition, the first semiconductor region 332 is etched using the mask 351 to form a third semiconductor region 353 that functions as a source region and a drain region. Through this step, the protective film 301 is exposed.

  Note that the method for forming the third conductive layer 352 functioning as the source electrode and the drain electrode is not limited to this embodiment mode, and the formation process of the second conductive layers 241 and 242 described in Embodiment Mode 4 can be used. good. Further, the step of forming the third conductive layer 352 functioning as the source electrode and the drain electrode in this embodiment may be applied to the second conductive layers 241 and 242 in Embodiment 4.

  Thereafter, similarly to Embodiment Mode 4, it is preferable to form a passivation film over the third conductive layer 352.

  Through the above steps, a channel protective TFT having a finely shaped semiconductor region can be manufactured. In addition, a highly integrated semiconductor device with little variation can be manufactured.

(Embodiment 6)
In this embodiment mode, a method for manufacturing a forward staggered TFT among top gate TFTs will be described with reference to FIGS.

  As shown in FIG. 6A, first conductive layers 411 and 412 are formed over the substrate 201. As this material and a manufacturing method, a material similar to that of the first conductive layer 202 in Embodiment 4 can be used as appropriate.

  Next, a first semiconductor film 413 having conductivity is formed over the first conductive layer. The first semiconductor film 413 can be manufactured using a material and a manufacturing method similar to those of the second semiconductor film 223 described in Embodiment 4.

  Next, after removing the oxide film formed on the surface of the first semiconductor film 413, a part of the first semiconductor film 413 is irradiated with a laser beam 414, so that the first semiconductor film 413 as illustrated in FIG. First insulating layers 421 and 422 that function as one mask are formed.

  Next, the first semiconductor film is etched using the first insulating layers 421 and 422 to form first semiconductor regions 423 and 424 as illustrated in FIG. Note that the first semiconductor region functions as a source region and a drain region. Next, a second semiconductor film 425 is formed. The second semiconductor film 425 can be manufactured using a material and a method which are similar to those of the first semiconductor film 222 described in Embodiment 4, as appropriate.

  Next, part of the second semiconductor film 425 is irradiated with laser light 432, so that a second insulating layer 441 functioning as a second mask as illustrated in FIG. 6D is formed.

  Next, the exposed portion of the second semiconductor film is etched using TMAH (tetramethylammonium hydroxide) to form a second semiconductor region 451 as shown in FIG. The second semiconductor region 451 functions as a channel region.

  Next, a second conductive layer 452 functioning as a gate electrode is formed over the second insulating layer 441. The second conductive layer 452 is formed using a material and a method similar to those of the first conductive layer in Embodiment 4. The second insulating layer 441 functions as a gate insulating film. Note that after the second insulating layer 441 is removed, an insulating layer functioning as a gate insulating film may be newly formed by using a method and a material which are similar to those of the first insulating layer 221 of Embodiment 4 as appropriate. good.

  Through the above steps, a channel-order staggered TFT having a finely shaped semiconductor region can be manufactured. In addition, a highly integrated semiconductor device with little variation can be manufactured.

(Embodiment 7)
In this embodiment mode, a method for manufacturing a coplanar TFT among top gate TFTs will be described with reference to FIGS.

  As shown in FIG. 7A, a first insulating layer 501 is formed over the substrate 201. The first insulating layer 501 functions as a blocking film for preventing impurities from the substrate from diffusing into a semiconductor region to be formed later. Therefore, the first insulating layer 501 is formed using an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The first insulating layer 501 is formed with a single-layer film or a structure in which two or more layers are stacked.

  Next, a semiconductor film 502 is formed over the first insulating layer 501. Next, after removing the oxide film formed on the surface of the semiconductor film 502, a predetermined region of the semiconductor film 502 is irradiated with a laser beam 503 in a manner similar to that in Embodiment 4, so that FIG. A second insulating layer 511 as shown is formed.

  Next, as illustrated in FIG. 7C, the semiconductor region 502 is formed by etching the semiconductor film 502 with TMAH using the second insulating layer 511 as a mask.

  Next, as shown in FIG. 7D, the second insulating layer 511 is removed. Next, a third insulating layer 521 that functions as a gate insulating film is formed over the semiconductor region 512 and the first insulating layer 501. The second insulating layer 511 can be formed using a material and a manufacturing method similar to those of the first insulating layer 221 described in Embodiment 4.

  Next, the first conductive layer 522 is formed. The first conductive layer is formed using a material and a method similar to those of the first conductive layer 202 described in Embodiment 4. Note that the first conductive layer 522 functions as a gate electrode.

  Next, as illustrated in FIG. 7E, an impurity is added to the semiconductor region 512 using the first conductive layer 522 as a mask. Next, after an insulating film containing hydrogen is formed, the impurity element added to the semiconductor region is activated by heating at 400 to 550 ° C., and the semiconductor region is hydrogenated to form the impurity region (the source region and the source region). Drain regions) 541 and 542 are formed. The semiconductor region covered with the first conductive layer 522 functions as the channel region 543. Note that a GRTA method, an LRTA method, or a laser annealing method can be used as the activation or hydrogenation step instead of the heat treatment.

  Note that although a single-gate TFT is shown in this embodiment mode, the present invention is not limited to this, and a multi-gate electrode structure may be used. Although a TFT with a self-aligned structure is shown, a TFT having a lightly doped drain (LDD) structure or a GOLD (Gate Overlapped LDD) structure can be used. In the LDD structure, a region to which an impurity element is added at a low concentration is provided between a channel region and a source region or a drain region formed by adding an impurity element at a high concentration, and this region is referred to as an LDD region. I'm calling. A TFT having this structure can reduce an off-current value. The GOLD structure is a structure in which an LDD region is disposed so as to overlap a gate electrode with a gate insulating film interposed therebetween, and has an effect of relaxing an electric field near the drain and preventing deterioration due to hot carrier injection.

  Next, a fourth insulating layer 544 is formed over the substrate. As a material of the fourth insulating layer, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride and other inorganic insulating materials, acrylic acid, methacrylic acid and derivatives thereof, or polyimide ( Among the compounds composed of silicon, oxygen and hydrogen formed from a heat-resistant polymer such as polyimide, aromatic polyamide, polybenzimidazole, or a siloxane polymer material typified by silica glass, Si— An inorganic siloxane polymer containing an O-Si bond, or hydrogen bonded to silicon represented by alkylsiloxane polymer, alkylsilsesquioxane polymer, hydrogenated silsesquioxane polymer, hydrogenated alkylsilsesquioxane polymer is methyl. It can be an insulating material of an organic siloxane polymer substituted by or organic groups such as phenyl. As a forming method, a known method such as a CVD method, a coating method, or a printing method is used. Note that the surface of the fourth insulating layer can be planarized by the application method, which is suitable for later pixel electrode formation. Here, the fourth insulating layer 544 is formed by a coating method.

  Next, a mask pattern is formed by a droplet discharge method, and part of the fourth insulating layer 544 and the third insulating layer 521 is removed using the mask pattern, so that impurity regions 541 and 542 in the semiconductor region are removed. A part is exposed to form an opening. Next, second conductive layers 545 and 546 are formed in the opening by using a method similar to that of the first conductive layer 202 of Embodiment 4 as appropriate. The second conductive layers 545 and 546 function as a source electrode and a drain electrode.

  Through the above steps, a coplanar TFT having a finely shaped semiconductor region can be manufactured. In addition, a highly integrated semiconductor device with little variation can be manufactured.

  Next, a method for manufacturing an active matrix substrate and a display panel having the active matrix substrate will be described with reference to FIGS. In this embodiment, a liquid crystal display panel will be described as a representative example of a display panel. FIG. 11 is a top view of the active matrix substrate, and FIGS. 8 to 10 schematically show cross-sectional structures corresponding to AB of the connection terminal portion and CD of the pixel portion.

  As shown in FIG. 8A, first conductive layers 802 and 803 are formed over the surface of the substrate 801. The first conductive layer is made of metal particles such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, and Ba. And a composition formed of organic resin is discharged and baked. The first conductive layer 802 functions as a later gate line, and the first conductive layer 803 functions as a later gate electrode. Here, an AN100 glass substrate manufactured by Asahi Glass Co., Ltd. is used as the substrate 801. In addition, the first conductive layers 802 and 803 are formed by discharging a composition in which Ag (silver) particles are dispersed by a droplet discharge method and heating the composition.

  Next, a gate insulating film 804 is formed by a CVD method. As the gate insulating film 804, a silicon nitride film with a thickness of 50 nm is formed, and then a silicon oxynitride film (SiON (O> N)) with a thickness of 50 nm is formed.

  Next, a first semiconductor film 805 and an n-type second semiconductor film 806 are formed. As the first semiconductor film 805, an amorphous silicon film with a thickness of 150 nm is formed. Next, after removing the oxide film on the surface of the amorphous silicon film, a semi-amorphous silicon film having a thickness of 50 nm is formed as the second semiconductor film 806 by a similar method. Here, the first semiconductor film and the second semiconductor film are formed by a CVD method.

  Next, after the oxide film formed on the surface of the second semiconductor film is removed, a part of the second semiconductor film 806 is irradiated with a laser beam 807 using a laser beam direct writing apparatus, so that FIG. ), A silicon oxide film 811 is formed on the surface of the second semiconductor film.

Next, as shown in FIG. 8C, the second semiconductor film 806 is etched using the silicon oxide film 811 to form a first semiconductor region 812. Similarly, the first semiconductor film is etched to form a second semiconductor region 813. Here, the first semiconductor film and the second semiconductor film are etched using a mixed gas having a flow rate ratio of CF ₄ : O ₂ = 10: 9. Thereafter, the silicon oxide film 811 is peeled off.

  Next, as shown in FIG. 9A, second conductive layers 821 and 822 are formed by a droplet discharge method. The second conductive layers 821 and 822 function as a later source line (source electrode) and a drain electrode, respectively. Here, the second conductive layers 821 and 822 are formed by discharging a composition in which Ag (silver) particles are dispersed and heating at 200 ° C. for 30 minutes.

  Note that, instead of the above process, the conductive layer is discharged and fired onto the first semiconductor region by a droplet discharge method. Next, a photosensitive material is applied or discharged onto the conductive layer and baked, and a portion of the photosensitive material is exposed and developed using laser light emitted from a laser beam direct drawing apparatus to form a mask. The second conductive layers 821 and 822 may be formed using a mask. In this case, a mask with a fine structure can be formed, and the distance between the source line and the drain electrode or the source electrode can be reduced.

  Next, using the second conductive layers 821 and 822 as a mask, the first semiconductor region is etched to form third semiconductor regions 823 and 824 and a fourth semiconductor region. The third semiconductor regions 823 and 824 function as a source region and a drain region, or a contact layer. At this time, the second semiconductor region is also etched. The fourth semiconductor region 825 which is the etched second semiconductor region functions as a channel region.

  Next, as illustrated in FIG. 9B, a third conductive layer 831 functioning as a pixel electrode is formed over the second conductive layer. As a typical example of the material of the third conductive layer 831, a light-transmitting conductive film or a reflective conductive film can be given. As a material for the light-transmitting conductive film, indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc oxide added with gallium (GZO), indium tin oxide containing silicon oxide, or the like Is mentioned. In addition, as a material for the conductive film having reflectivity, a metal such as aluminum (Al), titanium (Ti), silver (Ag), and tantalum (Ta), or a concentration less than the stoichiometric composition ratio with the metal is used. A metal material containing nitrogen, or aluminum nitride, titanium nitride, tantalum nitride, or the like which is a nitride of the metal can be given. As a method for forming the third conductive layer 831, a sputtering method, an evaporation method, a CVD method, a coating method, or the like is appropriately used. Here, indium tin oxide (ITO) containing silicon oxide with a thickness of 110 nm is formed as the third conductive layer 831 by a droplet discharge method.

  Through the above steps, an active matrix substrate can be formed. Note that the top surface structure corresponding to the cross-sectional structures AB and CD in FIG. 9B is shown in FIG.

Next, as illustrated in FIG. 9B, a protective film 832 is formed. As the protective film 832, a silicon oxide film having a thickness of 100 nm is formed by a sputtering method using a silicon target and argon and oxygen (flow ratio Ar: N ₂ = 1: 1) as a sputtering gas. A silicon nitride film with a thickness of 100 nm is formed by a sputtering method using argon and nitrogen (flow ratio Ar: O ₂ = 1: 1).

  Next, an insulating film is formed so as to cover the protective film 832 by a printing method or a spin coating method, and an alignment film 833 is formed by rubbing. Note that the alignment film 833 can also be formed by an oblique evaporation method.

  Next, as shown in FIG. 10A, in a counter substrate 881 provided with an alignment film 883 and a second pixel electrode (counter electrode) 882, a closed loop shape is formed in a region around the pixel portion by a droplet discharge method. The sealing material 871 is formed. The sealant 871 may be mixed with a filler, and the counter substrate 881 may be formed with a color filter, a shielding film (black matrix), or the like.

  Next, after a liquid crystal material is dropped inside the closed loop formed of the sealant 871 by a dispenser type (dropping type), an alignment film 883 and a second pixel electrode (counter electrode) 882 are provided in vacuum. The counter substrate 881 and the active matrix substrate are bonded to each other, and ultraviolet curing is performed to form a liquid crystal layer 884 filled with a liquid crystal material. Note that as a method for forming the liquid crystal layer 884, a dip type (pumping type) in which a liquid crystal material is injected using a capillary phenomenon after the counter substrate is bonded can be used instead of the dispenser type (dropping type).

  Next, part of the protective film 832 and the gate insulating film 804 in the connection terminal portion of the gate line and the source line is removed, and the connection terminals of the gate line and the source line are exposed.

  Next, as illustrated in FIG. 10B, a wiring substrate, typically an FPC (Flexible Print Circuit), (a wiring connected to a third conductive layer functioning as a gate line) is connected through a connection conductive layer 885. A substrate 886) is attached. Furthermore, it is preferable to seal the connection portion between the wiring board and the connection terminal portion with a sealing resin. With this structure, it is possible to prevent moisture from the cross section from entering the pixel portion and deteriorating.

  Through the above process, a liquid crystal display panel can be manufactured. Note that a protection circuit for preventing electrostatic breakdown, typically a diode or the like, may be provided between the connection terminal and the source line (gate line) or in the pixel portion. In this case, it is possible to prevent electrostatic breakdown by manufacturing in the same process as the above TFT and connecting the gate wiring layer of the pixel portion and the drain or source wiring layer of the diode.

  Note that any of Embodiment Modes 1 to 7 can be applied to this example.

  FIG. 12A illustrates a TN (twisted nematic) mode, an IPS (in-plane-switching) mode, an MVA (multi-domain vertical alignment) mode, an ASM (axially symmetrical aligned codec). Sectional drawing of the liquid crystal module which is a Bend mode and performs a color display using a white light and a color filter is shown.

  As shown in FIG. 12A, an active matrix substrate 1601 and a counter substrate 1602 are fixed with a sealant 1600, and a pixel portion 1603 and a liquid crystal layer 1604 are provided therebetween to form a display region. Yes.

  The colored layer 1605 is necessary when performing color display. In the case of the RGB method, a colored layer corresponding to each color of red, green, and blue is provided corresponding to each pixel. Polarizers 1606 and 1607 are disposed outside the active matrix substrate 1601 and the counter substrate 1602. In addition, a protective film 1616 is formed on the surface of the polarizing plate 1606 to reduce external impact.

  A wiring board 1610 is connected to a connection terminal 1608 provided on the active matrix substrate 1601 through an FPC 1609. The wiring board 1610 incorporates a pixel drive circuit (IC chip, driver IC, etc.), an external circuit 1612 such as a control circuit and a power supply circuit.

  A cold cathode tube 1613, a reflector 1614, an optical film 1615, and an inverter (not shown) are backlight units, and these serve as light sources and project light onto the liquid crystal display panel. A liquid crystal panel, a light source, a wiring board, an FPC, and the like are held and protected by a bezel 1617.

  FIG. 12 (B) uses a cold cathode tube or a diode that emits light of R (red), G (green), and B (blue) without using a color filter as in the field sequential mode, and by time division. It is sectional drawing of the liquid crystal module which can synthesize | combine an image and can perform a color display. Compared with FIG. 12A, no color filter is provided. Here, cold cathode tubes 1621 to 1623 that emit light respectively in R (red), G (green), and B (blue) are provided in the reflector 1614. Further, a controller (not shown) for controlling the light emission of these cold cathode tubes is provided. Further, since the liquid crystal layer 1624 is filled with ferroelectric liquid crystal and can operate at high speed, an image can be synthesized using time division.

  Note that an image may be synthesized by time division using liquid crystal alignment such as the OCB mode.

  In this embodiment, a method for manufacturing a light-emitting display panel, which is one of typical display panels, will be described with reference to FIGS. FIG. 15 shows a top structure of the pixel portion, and FIGS. 13 and 14 schematically show cross-sectional structures corresponding to AB (switching TFT) and CD (drive TFT) of the pixel portion in FIG. It is shown in.

  As shown in FIG. 13A, a first insulating layer 902 is formed with a thickness of 100 to 1000 nm over a substrate 901. Here, a 100-nm-thick silicon nitride oxide film using a plasma CVD method and a 50-nm-thick silicon oxynitride film using a low-pressure thermal CVD method are stacked as the first insulating layer.

  Next, an amorphous semiconductor film is formed with a thickness of 10 to 100 nm. Here, an amorphous silicon film 903 having a thickness of 50 nm is formed by using a low pressure thermal CVD method. Next, after removing the oxide film formed on the surface of the amorphous semiconductor film, a part of the amorphous semiconductor film is irradiated with a laser beam 904 by using a laser beam direct writing apparatus, and FIG. Silicon oxide films 911 and 912 as shown in FIG. At this time, in a region irradiated with laser light, a part of the amorphous semiconductor film is melted and then cooled and crystallized. At this time, the crystallized semiconductor regions are denoted by 913 and 914, and the amorphous semiconductor region remaining around the crystallized semiconductor region is denoted by 915.

  Next, the amorphous semiconductor regions 915 are etched using the silicon oxide films 911 and 912 as masks, so that semiconductor regions 921 and 922 having crystallinity as illustrated in FIG. 13C are formed. Next, a second insulating layer 923 that functions as a gate insulating film is formed. Here, a silicon oxide film is formed by a CVD method.

Next, a channel doping process in which a p-type or n-type impurity element is added at a low concentration in a region to be a channel region of the TFT is performed over the entire surface or selectively. This channel doping process is a process for controlling the TFT threshold voltage. Here, boron is added by an ion doping method in which plasma excited without mass separation of diborane (B ₂ H _6). Note that an ion implantation method for performing mass separation may be used.

  Next, first conductive layers 924 to 926 functioning as gate electrodes and a first conductive layer 927 functioning as a capacitor wiring are formed. Here, the first conductive layers 924 to 927 are formed by discharging an Ag paste by a droplet discharge method, irradiating with laser light, and baking.

Next, phosphorus is added to the semiconductor region in a self-aligning manner using the first conductive layers 924 to 927 as masks, so that high-concentration impurity regions 930 to 934 are formed. The phosphorus concentration in the high concentration impurity region is adjusted to 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ (typically 2 × 10 ^{20 to} 5 × 10 ²⁰ atoms / cm ³ ). Note that a region of the semiconductor regions 921 and 922 having crystallinity that overlaps with the first conductive layers 924 to 927 serves as a channel region.

  Next, a third insulating layer 935 that covers the first conductive layers 924 to 927 is formed. Here, an insulating film containing hydrogen is formed. Thereafter, the impurity element added to the semiconductor region is activated and the semiconductor region is hydrogenated. As the insulating film containing hydrogen, a silicon nitride oxide film (SiNO film) obtained by a sputtering method is used.

  Next, after an opening reaching the semiconductor region is formed, second conductive layers 941 to 944 are formed. The second conductive layer 941 functions as a source line, the second conductive layer 942 functions as a first connection wiring, the second conductive layer 943 functions as a power supply line and a capacitor wiring, and the second conductive layer 944 functions as a second connection wiring. In this embodiment, a laminated film having a three-layer structure in which a molybdenum film, an aluminum-silicon alloy film, and a molybdenum film are continuously formed by sputtering is formed, and then etched into a desired shape to form a third conductive layer. Form.

  Next, as illustrated in FIG. 14A, a fourth insulating layer 951 is formed. As the fourth insulating layer, an insulating layer that can be planarized is preferable. As the insulating layer that can be planarized, a material and a method similar to those of the fourth insulating layer 544 described in Embodiment 7 can be used as appropriate. Here, an acrylic resin film is formed. Note that as the fourth insulating layer, an organic material obtained by dissolving or dispersing a material that absorbs visible light, such as a black pigment or a dye, is used, so that the stray light absorption of a light-emitting element to be formed later can be reduced. It is absorbed by the layer, and the contrast of each pixel can be improved.

  Next, an opening is provided in the fourth insulating layer by known photolithography and etching in the fourth insulating layer, and a part of the second conductive layer (second connection wiring) 944 is exposed. Next, a third conductive layer 952 is formed. The third conductive layer functions as a first pixel electrode. The third conductive layer 952 is formed by stacking a reflective conductive film and a light-transmitting conductive film. Here, an aluminum film containing 1 to 20% nickel and ITO containing silicon oxide are stacked by a sputtering method. Note that aluminum containing 1 to 20% nickel is preferable because it does not corrode even in contact with the oxide ITO. After that, part of the reflective conductive film and the light-transmitting conductive film is etched, so that the third conductive layer 952 is formed.

  Note that the top surface structure corresponding to the cross-sectional structures AB and CD in FIG. 14A is shown in FIG.

  Next, a fifth insulating layer 961 serving as a partition wall (also referred to as a barrier or a bank) is formed so as to cover an end portion of the third conductive layer 952. The fifth insulating layer is made of a photosensitive or non-photosensitive organic material (polyimide, acrylic, polyamide, polyimide amide, resist or benzocyclobutene), or an SOG film (for example, an SiOx film containing an alkyl group). Used in the range of 8 μm to 1 μm. The fifth insulating layer is preferably formed using a photosensitive material because its side surface has a shape in which the radius of curvature continuously changes and the upper thin film is formed without being cut off.

  The fifth insulating layer may be a light-blocking insulator by dissolving or dispersing a material that absorbs visible light, such as a dye or a black pigment, in the organic material. In this case, since the fifth insulating layer functions as a black matrix, it can absorb stray light from a light-emitting element to be formed later. As a result, the contrast of each element is improved. Further, by providing the fourth insulating layer 951 also with a light-blocking insulator, a total light-blocking effect with the fifth insulating layer 961 can be obtained.

  Next, a layer 962 containing a light-emitting substance is formed over the surface of the third conductive layer 952 and the end portion of the fifth insulating layer 961 by an evaporation method, a coating method, a droplet discharge method, or the like. After that, a fourth conductive layer 963 functioning as a second pixel electrode is formed over the layer 962 containing a light-emitting substance. Here, ITO containing silicon oxide is formed by a sputtering method. As a result, a light-emitting element can be formed using the third conductive layer, the layer containing a light-emitting substance, and the fourth conductive layer. The materials of the conductive layer and the layer containing a light-emitting substance that constitute the light-emitting element are appropriately selected, and the thicknesses of the layers are also adjusted.

  Note that before the layer 962 containing a light-emitting substance is formed, heat treatment is performed at 200 ° C. under atmospheric pressure to remove moisture adsorbed in or on the surface of the fifth insulating layer 961. Further, heat treatment is performed at 200 to 400 ° C., preferably 250 to 350 ° C. under reduced pressure, and a layer 962 containing a light-emitting substance is formed without being exposed to the air as it is by a vacuum evaporation method or a droplet discharge method under reduced pressure. Is preferred.

  A light-emitting element formed using the above materials emits light by being forward-biased. A pixel of a display device formed using a light-emitting element can be driven by a simple matrix method or an active matrix method. In any case, each pixel emits light by applying a forward bias at a specific timing, but is in a non-light emitting state for a certain period. By applying a reverse bias during this non-light emitting time, the reliability of the light emitting element can be improved. The light emitting element has a degradation mode in which the light emission intensity decreases under a constant driving condition and a degradation mode in which the non-light emitting area is enlarged in the pixel and the luminance is apparently decreased. However, alternating current that applies a bias in the forward and reverse directions. By performing a typical drive, the progress of deterioration can be slowed and the reliability of the light emitting device can be improved.

  Next, a light-transmitting protective layer 964 that covers the light-emitting element and prevents moisture from entering is formed. As the light-transmitting protective layer 964, a silicon nitride film, a silicon oxide film, a silicon oxynitride film (SiNO film (composition ratio N> O) or SiON film (composition ratio N <O)) obtained by a sputtering method or a CVD method is used. A thin film mainly containing carbon (for example, a DLC film or a CN film) can be used.

  Through the above process, a light-emitting display panel can be manufactured. Note that a protective circuit for preventing electrostatic breakdown, typically a diode or the like, may be provided between the connection terminal and the source wiring layer (gate wiring layer) or in the pixel portion. In this case, electrostatic breakdown can be prevented by manufacturing the TFT in the same process as the above-described TFT and connecting the gate wiring layer of the pixel portion and the drain wiring layer or source wiring layer of the diode.

  A mode of a light-emitting element applicable in the above embodiment will be described with reference to FIGS.

  FIG. 16A shows an example in which the first pixel electrode 11 is formed of a light-transmitting oxide conductive material. The first pixel electrode 11 is formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. Yes. A layer 16 containing a light emitting material in which a hole injection layer (HIL) or a hole transport layer (HTL) 41, a light emitting layer (EM) 42, an electron transport layer (ETL) or an electron injection layer (EIL) 43 are stacked thereon. Is provided. The second pixel electrode 17 is formed of a first electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or MgAg and a second electrode layer 34 formed of a metal material such as aluminum. A pixel having this structure can emit light from the first pixel electrode 11 side as indicated by an arrow in the drawing.

  FIG. 16B shows an example in which light is emitted from the second pixel electrode 17 side. The first pixel electrode 11 is made of a metal such as aluminum or titanium or a concentration less than the stoichiometric composition ratio with the metal. The first electrode layer 35 is formed of a metal material containing nitrogen and the second electrode layer 32 is formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. A layer 16 containing a light emitting material in which a hole injection layer or hole transport layer 41, a light emitting layer 42, an electron transport layer or an electron injection layer 43 are stacked is provided thereon. The second pixel electrode 17 is formed of a third electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or CaF and a fourth electrode layer 34 formed of a metal material such as aluminum. By setting the layer to a thickness of 100 nm or less and transmitting light, light can be emitted from the second pixel electrode 17 side.

  FIG. 16E illustrates an example in which light is emitted from both directions, that is, from the first electrode side and the second electrode side. The first pixel electrode 11 has a light-transmitting conductive film having a high work function. As the second pixel electrode 17, a light-transmitting conductive film having a small work function is used. Typically, the first pixel electrode 11 is formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%, and the second pixel electrode 17 is formed of LiF having a thickness of 100 nm or less. Alternatively, the third electrode layer 33 containing an alkali metal or alkaline earth metal such as CaF or the like and the fourth electrode layer 34 formed of a metal material such as aluminum may be used. In addition, a layer 16 containing a light-emitting substance in which a hole injection layer or hole transport layer 41, a light emitting layer 42, an electron transport layer or an electron injection layer 43 are stacked is provided over the first pixel electrode 11.

  FIG. 16C illustrates an example in which light is emitted from the first pixel electrode 11 side, and a layer containing a light-emitting substance is an electron transport layer or an electron injection layer 43, a light emitting layer 42, a hole injection layer or a hole. The structure which laminated | stacked the order of the transport layer 41 is shown. The second pixel electrode 17 includes a second electrode layer 32 formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic% from the side of the layer 16 containing a light emitting substance, a metal such as aluminum or titanium, Alternatively, the first electrode layer 35 is formed using a metal material containing nitrogen at a concentration equal to or less than the stoichiometric composition ratio to the metal. The first pixel electrode 11 is formed of a third electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or CaF and a fourth electrode layer 34 formed of a metal material such as aluminum. By setting the layer to a thickness of 100 nm or less and allowing light to pass therethrough, light can be emitted from the first pixel electrode 11 side.

  FIG. 16D shows an example in which light is emitted from the second pixel electrode 17 side, and the layer 16 containing a light-emitting substance is formed as an electron transport layer or an electron injection layer 43, a light emitting layer 42, a hole injection layer or a positive layer. A configuration in which the hole transport layer 41 is laminated in this order is shown. The first pixel electrode 11 has a structure similar to that of the second pixel electrode 17 in FIG. 16A, and is formed to be thick enough to reflect light emitted from the layer containing a light-emitting substance. The second pixel electrode 17 is made of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. In this structure, when the hole injection layer 41 is formed of an inorganic metal oxide (typically molybdenum oxide or vanadium oxide), oxygen introduced when the second pixel electrode 17 is formed is supplied. Thus, the hole injection property is improved, and the driving voltage can be lowered.

  FIG. 16F illustrates an example in which light is emitted from both directions, that is, from the first pixel electrode side and the second pixel electrode side. The first pixel electrode 11 has a light-transmitting property and a work function. A small conductive film is used, and a conductive film having translucency and a high work function is used for the second pixel electrode 17. Typically, the first pixel electrode 11 is formed of a third electrode layer 33 containing an alkali metal or alkaline earth metal such as LiF or CaF having a thickness of 100 nm or less and a metal material such as aluminum. And the second pixel electrode 17 may be formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. In addition, a structure in which a layer containing a light-emitting substance is stacked on the first pixel electrode 11 in the order of an electron transport layer or electron injection layer 43, a light emitting layer 42, a hole injection layer or a hole transport layer 41 is shown.

  A pixel circuit of the light-emitting display panel described in the above embodiment and an operation configuration thereof will be described with reference to FIGS. There are two types of operation configurations of the light-emitting display panel, in which a video signal input to a pixel is defined by voltage and a current is defined by current in a display device in which a video signal is digital. There are two types of video signals defined by voltage, one having a constant voltage applied to the light emitting element (CVCV) and one having a constant current applied to the light emitting element (CVCC). In addition, a video signal is defined by current, there are a constant voltage applied to the light emitting element (CCCV) and a constant current applied to the light emitting element (CCCC). In this embodiment, a pixel that performs a CVCV operation will be described with reference to FIGS. A pixel that performs the CVCC operation will be described with reference to FIGS.

  In the pixel shown in FIGS. 17A and 17B, a source line 3710 and a power supply line 3711 are arranged in the column direction, and a gate line 3714 is arranged in the row direction. In addition, the pixel includes a switching TFT 3701, a driving TFT 3703, a capacitor element 3702, and a light emitting element 3705.

  Note that the switching TFT 3701 and the driving TFT 3703 operate in a linear region when turned on. The driving TFT 3703 has a role of controlling whether or not a voltage is applied to the light emitting element 3705. Both TFTs preferably have the same conductivity type in terms of manufacturing process. In this embodiment, the TFTs are formed as p-channel TFTs. The driving TFT 3703 may be a depletion type TFT as well as an enhancement type. The ratio (W / L) of the channel width W to the channel length L (W / L) of the driving TFT 3703 is preferably 1 to 1000 depending on the mobility of the TFT. The larger the W / L, the better the electrical characteristics of the TFT.

  In the pixel shown in FIGS. 17A and 17B, the switching TFT 3701 controls input of a video signal to the pixel. When the switching TFT 3701 is turned on, the video signal is input into the pixel. Then, the voltage of the video signal is held in the capacitor 3702.

  In FIG. 17A, when the power line 3711 is Vss and the counter electrode of the light emitting element 3705 is Vdd, that is, in FIGS. 16C and 16D, the counter electrode of the light emitting element is an anode, and the driving TFT 3703 The electrode connected to is a cathode. In this case, luminance unevenness due to characteristic variations of the driving TFT 3703 can be suppressed.

  In FIG. 17A, when the power supply line 3711 is Vdd and the counter electrode of the light emitting element 3705 is Vss, that is, in FIGS. 16A and 16B, the counter electrode of the light emitting element is a cathode, and the driving TFT 3703 The electrode connected to is the anode. In this case, when a video signal whose voltage is higher than Vdd is input to the source line 3710, the voltage of the video signal is held in the capacitor 3702, and the driving TFT 3703 operates in a linear region. It is possible to improve.

  The pixel shown in FIG. 17B has the same pixel structure as that shown in FIG. 17A except that a TFT 3706 and a gate line 3715 are added.

  The TFT 3706 is controlled to be turned on or off by a newly arranged gate line 3715. When the TFT 3706 is turned on, the charge held in the capacitor 3702 is discharged, and the driving TFT 3703 is turned off. That is, the arrangement of the TFT 3706 can forcibly create a state in which no current flows through the light emitting element 3705. Therefore, the TFT 3706 can be called an erasing TFT. Therefore, the structure in FIG. 17B can improve the light emission duty ratio because the lighting period can be started simultaneously with or immediately after the start of the writing period without waiting for signal writing to all the pixels. Is possible.

  In the pixel having the above operation configuration, the current value of the light-emitting element 3705 can be determined by the driving TFT 3703 that operates in a linear region. With the above structure, variation in TFT characteristics can be suppressed, and luminance unevenness of a light-emitting element due to variation in TFT characteristics can be improved, so that a display device with improved image quality can be provided.

  Next, a pixel that performs the CVCC operation will be described with reference to FIGS. In the pixel illustrated in FIG. 17C, a power supply line 3712 and a current control TFT 3704 are provided in the pixel configuration illustrated in FIG.

  The pixel shown in FIG. 17E is different from the pixel shown in FIG. 17C in that the gate electrode of the driving TFT 3703 is connected to a power supply line 3712 arranged in the row direction. It is a configuration. That is, both pixels shown in FIGS. 17C and 17E show the same equivalent circuit diagram. However, in the case where the power supply line 3712 is arranged in the column direction (FIG. 17C) and in the case where the power supply line 3712 is arranged in the row direction (FIG. 17E), each power supply line has a different layer. It is formed of a conductive film. Here, attention is paid to the wiring to which the gate electrode of the driving TFT 3703 is connected, and FIGS. 17C and 17E are shown separately to show that the layers for producing these are different.

  Note that the switching TFT 3701 operates in a linear region, and the driving TFT 3703 operates in a saturation region. The driving TFT 3703 has a role of controlling a current value flowing through the light emitting element 3705, and the current controlling TFT 3704 has a role of operating in a saturation region and controlling supply of current to the light emitting element 3705.

  The pixels shown in FIGS. 17D and 17F are the same as those shown in FIGS. 17C and 17E, respectively, except that an erasing TFT 3706 and a gate line 3715 are added. The pixel configuration is the same as that shown in E).

Note that the CVCC operation can also be performed in the pixels shown in FIGS. 17A and 17B. In addition, in the pixel having the operation configuration shown in FIGS. 17C to 17F, Vdd and Vss are appropriately changed depending on the direction of current flow of the light-emitting element, as in FIGS. 17A and 17B. Is possible.

  In the pixel having the above structure, since the current control TFT 3704 operates in a linear region, a slight change in Vgs of the current control TFT 3704 does not affect the current value of the light emitting element 3705. That is, the current value of the light emitting element 3705 can be determined by the driving TFT 3703 operating in the saturation region. With the above structure, it is possible to provide a display device in which luminance unevenness of a light-emitting element due to variation in TFT characteristics is improved and image quality is improved.

  In particular, in the case of forming a thin film transistor having an amorphous semiconductor or the like, it is preferable to increase the area of the semiconductor film of the driving TFT because the variation of the TFT can be reduced. Thus, the pixel shown in FIGS. 17A and 17B can increase the aperture ratio because the number of TFTs is small.

  Note that although a structure including the capacitor 3702 is shown, the present invention is not limited to this, and the capacitor 3702 is not provided in the case where the capacity for holding a video signal can be covered by a gate capacitor or the like. May be.

  In addition, when the semiconductor region of the thin film transistor is formed using an amorphous semiconductor film, a threshold value is likely to shift. Therefore, it is preferable to provide a circuit for correcting the threshold value in or around the pixel.

  Such an active matrix light-emitting device is considered to be advantageous because it can be driven at a low voltage because a TFT is provided in each pixel when the pixel density is increased. On the other hand, a passive matrix light-emitting device in which a TFT is provided for each column can be formed. A passive matrix light-emitting device has a high aperture ratio because a TFT is not provided for each pixel.

  In the display device of the present invention, the screen display driving method is not particularly limited. For example, a dot sequential driving method, a line sequential driving method, a surface sequential driving method, or the like may be used. Typically, a line sequential driving method is used, and a time-division gray scale driving method or an area gray scale driving method may be used as appropriate. The video signal input to the source line of the display device may be an analog signal or a digital signal, and a drive circuit or the like may be designed in accordance with the video signal as appropriate.

  As described above, various pixel circuits can be employed.

  In this embodiment, as an example of a display panel, the appearance of a light-emitting display panel will be described with reference to FIG. FIG. 18A is a top view of a panel in which a space between a first substrate and a second substrate is sealed with a first sealant 1205 and a second sealant 1206. FIG. ) Corresponds to a cross-sectional view taken along line AA ′ of FIG.

  In FIG. 18A, 1201 indicated by a dotted line is a source line (source line) driver circuit, 1202 is a pixel portion, and 1203 is a gate line (gate line) driver circuit. In this embodiment, the source line driver circuit 1201, the pixel portion 1202, and the gate line driver circuit 1203 are in a region sealed with a first sealant and a second sealant. As the first sealing material, it is preferable to use a highly viscous epoxy resin containing a filler. As the second sealing material, it is preferable to use an epoxy resin having a low viscosity. The first sealing material 1205 and the second sealing material 1206 are preferably materials that do not transmit moisture and oxygen as much as possible.

Further, a desiccant may be provided between the pixel portion 1202 and the first sealant 1205. Further, in the pixel portion, a desiccant may be provided over the gate line or the source line. As the desiccant, it is preferable to use a substance that adsorbs water (H ₂ O) by chemical adsorption such as an oxide of an alkaline earth metal such as calcium oxide (CaO) or barium oxide (BaO). However, the present invention is not limited to this, and a substance that adsorbs water by physical adsorption such as zeolite or silica gel may be used.

  By providing the desiccant in a region overlapping with the gate line and the source line and fixing the desiccant granular material to the second substrate 1204 in a highly moisture-permeable resin, the aperture ratio is increased. Intrusion of moisture into the display element and deterioration due to the penetration can be suppressed without lowering.

  Here, as the highly moisture-permeable resin, an organic material or an inorganic material such as an acrylic resin, an epoxy resin, a siloxane polymer, polyimide, PSG (phosphorus glass), or BPSG (phosphorus glass) can be used.

  Note that reference numeral 1210 denotes a connection wiring for transmitting a signal input to the source line driver circuit 1201 and the gate line driver circuit 1203. An FPC (flexible printed wiring) 1209 serving as an external input terminal is connected via a connection wiring 1208. Receive video and clock signals.

  Next, a cross-sectional structure is described with reference to FIG. A driver circuit and a pixel portion are formed over the first substrate 1200, and includes a plurality of semiconductor elements typified by TFTs. A source line driver circuit 1201 and a pixel portion 1202 are shown as driver circuits. Note that as the source line driver circuit 1201, a CMOS circuit in which an n-channel TFT 1221 and a p-channel TFT 1222 are combined is formed.

  In this embodiment, a source line driver circuit, a gate line driver circuit, and a TFT of a pixel portion are formed over the same substrate. For this reason, the volume of the light emitting display panel can be reduced.

  The pixel portion 1202 is formed of a plurality of pixels including a switching TFT 1211, a driving TFT 1212, and a first pixel electrode (anode) 1213 made of a reflective conductive film electrically connected to the drain thereof. .

  In addition, as an interlayer insulating film 1220 of these TFTs 1211, 1212, 1221, 1222, an inorganic material (silicon oxide, silicon nitride, silicon oxynitride, etc.), an organic material (polyimide, polyamide, polyimide amide, benzocyclobutene), or It can be formed using a material mainly composed of a siloxane polymer.

  In addition, insulators (called partition walls, barriers, banks, or the like) 1214 are formed at both ends of the first pixel electrode (anode) 1213. In order to improve the coverage (coverage) of the film formed over the insulator 1214, a curved surface having a curvature is formed at the upper end portion or the lower end portion of the insulator 1214.

  Further, an organic compound material is deposited on the first pixel electrode (anode) 1213 to selectively form a layer 1215 containing a light-emitting substance. In addition, the second pixel electrode 1216 is formed over the layer 1215 containing a light-emitting substance.

  For the layer 1215 containing a light-emitting substance, the structure shown in Example 4 can be used as appropriate.

  In this manner, a light-emitting element 1217 including the first pixel electrode (anode) 1213, the layer 1215 containing a light-emitting substance, and the second pixel electrode (cathode) 1216 is formed. The light-emitting element 1217 emits light toward the second substrate 1204 side.

  In addition, a protective stack 1218 is formed in order to seal the light emitting element 1217. The protective laminate includes a laminate of a first inorganic insulating film, a stress relaxation film, and a second inorganic insulating film. Next, the protective laminate 1218 and the second substrate 1204 are bonded with the first sealant 1205 and the second sealant 1206. Note that the second sealing material is preferably dropped using an apparatus for discharging the composition. After the sealing material is dropped or discharged from the dispenser to apply the sealing material onto the active matrix substrate, the second substrate and the active matrix substrate are bonded together in a vacuum and then cured by ultraviolet curing. it can.

  The connection wiring 1208 and the FPC 1209 are electrically connected by an anisotropic conductive film or an anisotropic conductive resin 1227. Furthermore, it is preferable that the connection portion between each wiring layer and the connection terminal is sealed with a sealing resin. With this structure, moisture from the cross section can be prevented from entering and deteriorating the light emitting element.

  Note that a space filled with an inert gas such as nitrogen gas may be provided between the second substrate 1204 and the protective stack 1218. It is possible to enhance prevention of moisture and oxygen from entering.

  In addition, a colored layer can be provided over the second substrate 1204. In this case, a full color display can be performed by providing a light emitting element capable of emitting white light in the pixel portion and separately providing a colored layer showing RGB. Further, full color display can be performed by providing a light emitting element capable of emitting blue light in the pixel portion and separately providing a color conversion layer or the like. Furthermore, each pixel portion, a light emitting element that emits red, green, and blue light can be formed, and a colored layer can be used. Such a display module has high color purity of each RBG and enables high-definition display.

  Further, a polarizing plate and a retardation plate may be provided on the surface of the second substrate 1204.

  Alternatively, the light-emitting display panel may be formed using one of the first substrate 1200 and the second substrate 1204, or a substrate such as a film or resin. When sealing is performed without using the counter substrate in this manner, the weight, size, and thickness of the display device can be improved.

  Furthermore, a light emitting display module can be formed by connecting an external circuit such as a power supply circuit and a controller to the light emitting display panel.

  Note that any of Embodiment Modes 1 to 7 can be applied to this example.

  In addition, examples of the liquid crystal display panel and the light emitting display panel are shown as the display panel, and examples of the liquid crystal display module and the light emitting display module are shown as the display module. However, the present invention is not limited to this, and DMD (Digital Micromirror Device; Digital) The present invention can be appropriately applied to display panels or display modules such as micromirror devices), PDPs (Plasma Display Panels), FEDs (Field Emission Displays), and electrophoretic display devices (electronic paper).

  In this embodiment, mounting of a driver circuit on the display panel described in the above embodiment will be described with reference to FIGS.

  As shown in FIG. 19A, a source line driver circuit 1402 and gate line driver circuits 1403a and 1403b are mounted around the pixel portion 1401. In FIG. 19A, as a source line driver circuit 1402 and gate line driver circuits 1403a and 1403b, a known anisotropic conductive adhesive and a mounting method using an anisotropic conductive film, a COG method, wire bonding The IC chip 1405 is mounted on the substrate 1400 by a method, a reflow process using a solder bump, or the like. Here, the COG method is used. Then, an IC chip and an external circuit are connected via an FPC (flexible printed circuit) 1406.

  Note that a part of the source line driver circuit 1402, for example, an analog switch may be formed over the substrate 1400, and the other part may be separately mounted using an IC chip.

  As shown in FIG. 19B, in the case where a TFT is formed using SAS or a crystalline semiconductor, the pixel portion 1401 and gate line driver circuits 1403a and 1403b are integrally formed on a substrate, and the source line driver circuit 1402 and the like are formed. May be separately mounted as an IC chip. In FIG. 19B, an IC chip 1405 is mounted on a substrate 1400 as a source line driver circuit 1402 by a COG method. Then, the IC chip and an external circuit are connected through the FPC 1406.

  Note that a part of the source line driver circuit 1402, for example, an analog switch may be integrally formed on the substrate, and the other part may be separately mounted using an IC chip.

  Further, as shown in FIG. 19C, the source line driver circuit 1402 and the like may be mounted by a TAB method instead of the COG method. Then, the IC chip and an external circuit are connected through the FPC 1406. In FIG. 19C, the source line driver circuit is mounted by the TAB method, but the gate line driver circuit may be mounted by the TAB method.

  When the IC chip is mounted by the TAB method, a pixel portion can be provided larger than the substrate, and a narrow frame can be achieved.

  The IC chip is formed using a silicon wafer, but an IC (hereinafter referred to as a driver IC) in which a circuit is formed on a glass substrate may be provided instead of the IC chip. Since an IC chip is taken out from a circular silicon wafer, the shape of the base substrate is limited. On the other hand, the driver IC has a mother substrate made of glass and has no restriction in shape, so that productivity can be improved. Therefore, the shape of the driver IC can be set freely. For example, when the length of the long side of the driver IC is 15 to 80 mm, the required number can be reduced as compared with the case where the IC chip is mounted. As a result, the number of connection terminals can be reduced, and the manufacturing yield can be improved.

  The driver IC can be formed using a crystalline semiconductor formed over a substrate, and the crystalline semiconductor is preferably formed by irradiation with continuous wave laser light. A semiconductor film obtained by irradiation with continuous wave laser light has few crystal defects and large crystal grains. As a result, a transistor having such a semiconductor film has favorable mobility and response speed, can be driven at high speed, and is suitable for a driver IC.

  FIG. 20A is a perspective view showing one mode of an ID chip which is one of the present invention. Reference numeral 2101 denotes an integrated circuit, 2102 denotes an antenna, and the antenna 2102 is connected to the integrated circuit 2101. Reference numeral 2103 denotes a substrate, and 2104 denotes a cover material. The integrated circuit 2101 and the antenna 2102 are formed over the substrate 2103, and the cover material 2104 overlaps the substrate 2103 so as to cover the integrated circuit 2101 and the antenna 2102. Note that the cover material 2104 is not necessarily used, but the mechanical strength of the ID chip can be increased by covering the integrated circuit 2101 and the antenna 2102 with the cover material 2104. Further, an antenna may cover the integrated circuit. That is, the area occupied by the integrated circuit and the area occupied by the antenna may be equal.

  By forming the integrated circuit 2101 using the semiconductor element described in the above embodiment mode, an ID chip with little variation can be manufactured with high yield.

  FIG. 20B is a perspective view showing one mode of an IC card which is one of the present invention. Reference numeral 2105 denotes an integrated circuit, 2106 denotes an antenna, and the antenna 2106 is connected to the integrated circuit 2105. Reference numeral 2108 denotes a substrate functioning as an inlet sheet, and 2107 and 2109 correspond to cover materials. The integrated circuit 2105 and the antenna 2106 are formed on an inlet sheet 2108, and the inlet sheet 2108 is sandwiched between two cover members 2107 and 2109. Note that the IC card of the present invention may include a display device connected to the integrated circuit 2105.

  By forming the integrated circuit 2105 with the semiconductor element described in the above embodiment mode or the above embodiments, an IC card with little variation can be manufactured with high yield.

  FIG. 21 shows a typical block diagram of an ID chip typified by a non-contact RFID (Radio Frequency Identification) tag, a wireless tag, etc. which is one of the present invention. FIG. 21 shows a configuration having a simple function of reading fixed data such as authentication data. In the figure, an ID chip 1301 includes an antenna 1302, a high-frequency circuit 1303, a power supply circuit 1304, a reset circuit 1305, a clock generation circuit 1306, a data demodulation circuit 1307, a data modulation circuit 1308, a control circuit 1309, and a nonvolatile memory (NVM). ) 1310 and ROM 1311.

  In this embodiment, any one of the power supply circuit 1304, the reset circuit 1305, the clock generation circuit 1306, the data demodulation circuit 1307, the data modulation circuit 1308, and the control circuit 1309 includes the semiconductor element described in the above embodiment mode or the above embodiment mode. Can be used. As described above, an ID chip can be efficiently manufactured.

  Further, all the circuits shown in FIG. 21 are formed on a glass substrate, a flexible substrate, or a semiconductor substrate. The antenna 1302 may be formed over a glass substrate, a flexible substrate, or a semiconductor substrate, or may be outside the substrate and connected to a semiconductor integrated circuit inside the substrate.

  The high frequency circuit 1303 is a circuit that receives an analog signal from the antenna 1302 and outputs the analog signal received from the data modulation circuit 1308 from the antenna 1302. The power supply circuit 1304 generates a constant power supply from the received signal, the reset circuit 1305 generates a reset signal, the clock generation circuit 1306 generates a clock signal, and the data demodulation circuit 1307 extracts data from the received signal. A circuit and data modulation circuit 1308 is a circuit that generates an analog signal to be output to an antenna based on a digital signal received from a control circuit or changes antenna characteristics, and an analog unit is configured by the above circuits.

On the other hand, the control circuit 1309 receives data extracted from the received signal and performs data reading. Specifically, an address signal of the NVM 1310 or the ROM 1311 is generated, data is read, and the read data is sent to the data modulation circuit. The digital circuit is composed of the above circuits.

  As electronic devices including the semiconductor device described in any of Embodiments and Examples, a television device (also simply referred to as a television or a television receiver), a digital camera, a digital video camera, a mobile phone device (simply a mobile phone or a mobile phone) Also, a portable information terminal such as a PDA, a portable game machine, a computer monitor, a computer, an audio reproduction device such as a car audio, and an image reproduction device including a recording medium such as a home game machine. A specific example will be described with reference to FIG.

  A portable information terminal illustrated in FIG. 23A includes a main body 9201, a display portion 9202, and the like. As the display portion 9202, any of those shown in Embodiment Modes 1 to 7 and Examples 1 to 8 can be used. By using the display device which is one embodiment of the present invention, a portable information terminal capable of high-quality display can be provided at low cost.

  A digital video camera shown in FIG. 23B includes a display portion 9701, a display portion 9702, and the like. As the display portion 9701, the display modes in Embodiment Modes 1 to 7 and Examples 1 to 8 can be applied. By using the display device which is one embodiment of the present invention, a digital video camera capable of high-quality display can be provided at low cost.

  A portable terminal illustrated in FIG. 23C includes a main body 9101, a display portion 9102, and the like. As the display portion 9102, the display modes shown in Embodiment Modes 1 to 7 and Examples 1 to 8 can be applied. By using the display device which is one embodiment of the present invention, a portable terminal capable of high-quality display can be provided at low cost.

  A portable television device shown in FIG. 23D includes a main body 9301, a display portion 9302, and the like. The display portion 9302 can be any of those shown in Embodiment Modes 1 to 7 and Examples 1 to 8. By using the display device which is one embodiment of the present invention, a portable television device capable of high-quality display can be provided at low cost. Such a television device can be widely applied from a small one mounted on a portable terminal such as a cellular phone to a medium-sized one that can be carried and a large one (for example, 40 inches or more). .

  A portable computer shown in FIG. 23E includes a main body 9401, a display portion 9402, and the like. As the display portion 9402, any of those shown in Embodiment Modes 1 to 7 and Examples 1 to 8 can be used. By using the display device which is one embodiment of the present invention, a portable computer capable of high-quality display can be provided at low cost.

  A television device illustrated in FIG. 23F includes a main body 9501, a display portion 9502, and the like. As the display portion 9502, any of those shown in Embodiment Modes 1 to 7 and Examples 1 to 8 can be used. By using the display device which is one embodiment of the present invention, a television device capable of high-quality display can be provided at low cost.

  Among the electronic devices listed above, those using a secondary battery can extend the usage time of the electronic device as much as power consumption is reduced, and can save the trouble of charging the secondary battery.

  In this example, a cross section of a semiconductor region formed using Embodiment Mode 2 is described with reference to FIGS.

  An amorphous silicon film having a thickness of 54 nm was formed on a glass substrate by a CVD method. Next, the oxide film formed on the surface of the amorphous silicon film was removed using a hydrofluoric acid aqueous solution.

Next, a part of the amorphous silicon film was irradiated with laser light (wavelength: 532 nm, beam diameter: 15 to 20 μm) emitted from a YVO ₄ laser. At this time, a silicon oxide film was formed in the region irradiated with the laser light.

  Next, the amorphous silicon film was etched using tetramethylammonium hydroxide. At this time, the amorphous silicon film was exposed to tetramethylammonium hydroxide at 50 to 60 degrees for 150 to 200 seconds. As a result, the region of the amorphous silicon film not covered with the silicon oxide film was removed.

Thereafter, the silicon oxide film was removed. At this time, the step shape of the region in which a part of the amorphous silicon film is etched is obtained as a stylus type surface shape inspection apparatus DEKTAK ³ ST.
The measurement results (manufactured by Nippon Vacuum Technology Co., Ltd.) are shown in FIG.

  The horizontal axis of FIG. 24 indicates the width of the measurement region, and the vertical axis indicates the unevenness of the substrate surface. Protrusions having a thickness of 500 to 530 nm were formed in a region having a width of about 10 μm (horizontal axis of 35 to 46 μm). When the region was observed with an optical microscope, it was a region where a part of the amorphous silicon film was etched.

  From the above results, it is possible to form a silicon oxide film by irradiating the amorphous silicon film with laser light, and to etch the amorphous silicon film using the silicon oxide film as a mask.

10A and 10B are cross-sectional views illustrating a manufacturing process of a semiconductor region according to the present invention. 10A and 10B are cross-sectional views illustrating a manufacturing process of a semiconductor region according to the present invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A to 8D are top views illustrating a manufacturing process of a semiconductor device according to the present invention. Sectional drawing explaining the structure of the liquid crystal display module which concerns on this invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A and 8B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the invention. 8A to 8D are top views illustrating a manufacturing process of a semiconductor device according to the present invention. 4A and 4B each illustrate a mode of a light-emitting element that can be applied to the present invention. 4A and 4B each illustrate a circuit of a light-emitting element applicable to the present invention. 4A and 4B are a top view and cross-sectional views illustrating a structure of a light-emitting display panel of the present invention. FIG. 6 is a top view illustrating a method for mounting a driver circuit of a display device according to the present invention. FIG. 11 is a perspective view illustrating an example of a semiconductor device of the invention. FIG. 11 is a block diagram illustrating an example of a semiconductor device of the invention. 1A and 1B illustrate a laser beam direct drawing apparatus applicable to the present invention. 10A and 10B each illustrate an example of an electronic device. FIG. 6 illustrates a cross section of a semiconductor region formed according to the present invention. FIG. 6 is a top view illustrating the shape of a semiconductor region according to the present invention. FIG. 6 is a top view illustrating the shape of a semiconductor region according to the present invention.

Claims (4)

Some of the first oxide layer formed on the semi-conductor film is irradiated with a laser beam, after a portion of the first oxide layer was altered to the second oxide layer, said first Removing the exposed portion of the oxide layer of 1;
A method for manufacturing a semiconductor device, wherein the semiconductor film is etched using the second oxide layer as a mask to form a semiconductor region. Oite to claim 1,
The method for manufacturing a semiconductor device, wherein the laser light is light emitted from a laser beam drawing apparatus. Oite to claim 1 or claim 2,
The method for manufacturing a semiconductor device , wherein the semiconductor region is amorphous. Oite to claim 1 or claim 2,
The method for manufacturing a semiconductor device , wherein the semiconductor region is crystalline.

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