JP2004356637A - Tft and manufacturing method therefor - Google Patents

Tft and manufacturing method therefor Download PDF

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JP2004356637A
JP2004356637A JP2004165131A JP2004165131A JP2004356637A JP 2004356637 A JP2004356637 A JP 2004356637A JP 2004165131 A JP2004165131 A JP 2004165131A JP 2004165131 A JP2004165131 A JP 2004165131A JP 2004356637 A JP2004356637 A JP 2004356637A
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Fumimasa Yo
文昌 葉
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Abstract

<P>PROBLEM TO BE SOLVED: To provide excellent performance TFTs (thin-film transistors) which can solve the conventional problems especially relating to the manufacturing method of a crystal TFT, using excimer laser annealing and the related TFT. <P>SOLUTION: A semiconductor island used as active region is formed, and insulating coating film used as gate insulated film is formed on it. Semiconductor film and the insulating coating film are treated by laser annealing, at the same time. As a result of this, the semiconductor island grows transversely in crystallization, in all directions, and the insulating coating film is turned quality high in simultaneously. Moreover, regarding the patterning of the semiconductor film, it can be patterned, without using resist in such a way that a light irradiating the semiconductor through a mask makes an extremely thin oxide film formed partially on the surface, and the semiconductor film, in which the ultra-thin oxide film is not formed on the surface, is removed by gas-phase etching executed, after the formation in a state with the semiconductor film being kept in an oxygen atmosphere. A high performance single crystal TFT, superior in transistor characteristics and of proper yield, can be manufactured, in such a manner that these processes are executed continuously, without exposing to conditions which not exposed by atmosphere. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

発明の詳細な説明DETAILED DESCRIPTION OF THE INVENTION

産業上の利用分野Industrial applications

本発明は、薄膜トランジスタに関し、特にエキシマレーザアニールを使用する結晶薄膜トランジスタの製造方法及びかかる薄膜トランジスタに関する。The present invention relates to a thin film transistor, and more particularly, to a method of manufacturing a crystalline thin film transistor using excimer laser annealing and such a thin film transistor.

まず最初に、本明細書で使用する単語について説明しておく。First, words used in the present specification will be described.

本明細書においては、原則として「半導体」とはシリコン(硅素、Si)やゲルマニウム等の材料的なものを指し、「トランジスタ」とはこれら半導体を使用して形成された真空管、スイッチ等の素子的なものを指すものとする。またエネルギービームとは、光、レーザ光、電子、X線、などのビームをさす。In this specification, in principle, "semiconductor" refers to materials such as silicon (silicon, Si) and germanium, and "transistor" refers to elements such as vacuum tubes and switches formed using these semiconductors. Shall be referred to as a typical thing. The energy beam refers to a beam of light, laser light, electron, X-ray, or the like.

近年、薄膜トランジスタ(以下、「TFT」とも記す)を用いて、各画素毎に独立して駆動するアクティブマトリクス液晶表示素子(LCD)やアクティブマトリクス有機EL表示素子の研究開発が活発に行われている。そして、このTFTは大別して、多結晶シリコン薄膜トランジスタ(以下、「poly−Si TFT」とも記す)と非晶質シリコン薄膜トランジスタ(以下、「a−Si TFT」とも記す)に分けられる。In recent years, research and development of an active matrix liquid crystal display element (LCD) or an active matrix organic EL display element that independently drives each pixel using a thin film transistor (hereinafter also referred to as “TFT”) have been actively performed. . This TFT is roughly classified into a polycrystalline silicon thin film transistor (hereinafter, also referred to as “poly-Si TFT”) and an amorphous silicon thin film transistor (hereinafter, also referred to as “a-Si TFT”).

そして多結晶シリコン薄膜トランジスタは高い移動度を有することから、将来画素の駆動だけではなく、周辺駆動回路、更には情報処理回路をもガラス上に一体化することが、期待されている。Since polycrystalline silicon thin film transistors have high mobility, it is expected that not only driving of pixels but also peripheral driving circuits and further information processing circuits will be integrated on glass in the future.

十分に高速な情報処理回路をも薄膜トランジスタで形成するには、電子移動度を単結晶シリコンに近い500cm/vs以上にする必要があるとされている。このような高性能薄膜トランジスタを実現するには、良質なシリコン膜とゲート絶縁膜を作製する必要がある。しかし現状では、シリコン膜に関して言えば多結晶シリコン膜しか得られず、その結晶粒界は電子の散乱中心となるため、結晶粒界の存在は移動度を低下させてしまう。一方でゲート絶縁膜に関して言うと、低温堆積であるが故に、固定電荷と界面準位が大きくなる。また、現在の製造方法ではゲート絶縁膜の堆積前にトランジスタの活性領域半導体島を形成するために一回のフォトリソグラフィ工程が入り、この工程が半導体/ゲート絶縁膜界面を損ねてしまう。絶縁膜と半導体/ゲート絶縁膜界面の品質はトランジスタの閾値電圧を変動させるだけではなく移動度も低下させてしまう。従って、高性能なTFT特性を得るためには、TFTのチャネル部分の粒界を極力少なくすほか、良質なゲート絶縁膜と良質なシリコン/ゲート絶縁膜界面を形成する必要がある。It is said that in order to form a sufficiently high-speed information processing circuit using a thin film transistor, the electron mobility needs to be 500 cm 2 / vs or more, which is close to that of single crystal silicon. In order to realize such a high-performance thin film transistor, it is necessary to manufacture a high-quality silicon film and a gate insulating film. However, at present, only a polycrystalline silicon film can be obtained with respect to a silicon film, and the crystal grain boundary becomes a scattering center of electrons, so that the presence of the crystal grain boundary lowers the mobility. On the other hand, as for the gate insulating film, fixed charge and interface states increase due to low-temperature deposition. In addition, in the current manufacturing method, one photolithography step is performed to form an active region semiconductor island of a transistor before the gate insulating film is deposited, and this step damages the semiconductor / gate insulating film interface. The quality of the interface between the insulating film and the semiconductor / gate insulating film not only fluctuates the threshold voltage of the transistor but also lowers the mobility. Therefore, in order to obtain high-performance TFT characteristics, it is necessary to minimize the grain boundaries in the channel portion of the TFT and to form a good gate insulating film and a good silicon / gate insulating film interface.

現在500℃以下の低温で多結晶薄膜を形成する方法に非晶質シリコン膜をエキシマレーザーで照射して、溶融させてから凝固する際に結晶化させる方法がある。この方法はガラス基板に熱ダメージを与えないことから、有望な方法とされている。しかしこの方法では粒径が小さく、且つ結晶粒の位置を制御することが難しく、従って単結晶TFTの実現は難しかった。As a method of forming a polycrystalline thin film at a low temperature of 500 ° C. or less at present, there is a method of irradiating an amorphous silicon film with an excimer laser to melt and then crystallize when solidifying. This method is considered to be a promising method because it does not cause thermal damage to the glass substrate. However, in this method, the grain size is small, and it is difficult to control the positions of the crystal grains, so that it is difficult to realize a single crystal TFT.

このような問題の解決法として最近、結晶を横方向に成長させて、トランジスタのチャネルをこの横方向結晶成長方向と平行に配置し、キャリアがチャネルを通過する際に跨る結晶粒界をなくすことで移動度を400cm2/vs以上にできることが実証されている。このため、近年では横方向結晶成長を実現させてTFTに利用する技術が盛んに開発されている。一般に横方向結晶成長はシリコン膜内に温度勾配を発生させればよく、そうすれば結晶は低温部から高温部に向かって横方向成長する。主な方法として、レーザ強度を空間的に強弱をつけることであるが、この強弱は例えば局所的にレーザ光を遮るマスク法、レーザ光干渉を発生させる位相シフト法などが考案されている。しかし、これらの方法はレーザ光源を変調させる必要があるために、高価な光学装置を必要とし、薄膜トランジスタの製造コストを上げる要因となる。また、望むところに横方向結晶粒を発生させる結晶粒の位置制御も簡単な方法では実現されていない。現在、第一世代の低温多結晶ポリシリコン薄膜トランジスタの生産は始まっているが、しかしこれは均一レーザ光を半導体膜に照射させて結晶をランダムに発生させる第一世代のレーザアニール装置を用いており、このレーザアニール装置では簡単に横方向結晶成長と結晶粒位置制御が実現できていない。この装置で横方向結晶成長と結晶粒位置制御が実現できれば、新たに高額なレーザアニール装置を購入しなくてすむので、第一世代レーザアニール装置での均−レーザ光を用いた新方法の発明が望まれている。As a solution to such a problem, recently, a crystal is grown in a lateral direction, and a channel of a transistor is arranged in parallel with the lateral crystal growth direction to eliminate a crystal grain boundary that crosses when a carrier passes through the channel. Has demonstrated that the mobility can be increased to 400 cm 2 / vs or more. For this reason, in recent years, techniques for realizing lateral crystal growth and using it for TFTs have been actively developed. In general, the lateral crystal growth may be performed by generating a temperature gradient in the silicon film, so that the crystal grows laterally from a low temperature portion to a high temperature portion. The main method is to vary the laser intensity spatially. For example, a mask method that locally blocks laser light and a phase shift method that generates laser light interference have been devised. However, these methods need to modulate the laser light source, require expensive optical devices, and increase the manufacturing cost of the thin film transistor. Further, position control of crystal grains for generating lateral crystal grains where desired is not realized by a simple method. Currently, the production of the first-generation low-temperature polycrystalline polysilicon thin-film transistors has begun, but this uses a first-generation laser annealing device that randomly generates crystals by irradiating the semiconductor film with uniform laser light. However, this laser annealing apparatus cannot easily realize lateral crystal growth and control of crystal grain position. If lateral growth and crystal grain position control can be realized with this apparatus, it is not necessary to purchase a new expensive laser annealing apparatus, and the invention of a new method using uniform laser light in the first generation laser annealing apparatus. Is desired.

一方で、薄膜トランジスタの良質ゲート絶縁膜形成に関して言えば、トランジスタの製造温度が基板耐熱温度である500℃に制限されているため、十分に満足される絶縁膜の製造方法は確立されていない。絶縁膜の堆積に関しては、PECVD法が考えられるが、しかしこの方法ではプラズマによって絶縁膜にダメージが生じる。現在このプラズマによるダメージを軽減するためにECR−PECVD法で絶縁膜を堆積する方法や、絶縁膜堆積後に高圧水蒸気、酸素プラズマなどで絶縁膜をアニールする方法などが考案されているが、前者では装置が高く、後者においては工程が繁雑なってしまう問題点が残される。On the other hand, regarding the formation of a high-quality gate insulating film of a thin film transistor, since the manufacturing temperature of the transistor is limited to 500 ° C., which is the substrate heat-resistant temperature, a sufficiently satisfactory method of manufacturing an insulating film has not been established. Regarding the deposition of the insulating film, a PECVD method can be considered, but in this method, the insulating film is damaged by the plasma. At present, a method of depositing an insulating film by ECR-PECVD or a method of annealing the insulating film with high-pressure steam or oxygen plasma after depositing the insulating film have been devised in order to reduce the damage caused by the plasma. The apparatus is expensive, and in the latter case, the problem of complicating the process remains.

これら以外に低温堆積したシリコン窒化膜をレーザ照射して高温アニールする方法が考案されたが、しかし、シリコン窒化膜のレーザ光に対する吸収係数が高かった故にレーザ光は膜の深くまでは浸透できず、表面しかアニールされなく、従ってこの方式では絶縁膜の充分な向上効果は得られなかった。In addition to these methods, a method was devised in which a silicon nitride film deposited at a low temperature was irradiated with a laser and then annealed at a high temperature. However, only the surface was annealed, so that this method did not provide a sufficient effect of improving the insulating film.

更に、現在一般的に実用されているトップゲート式薄膜トランジスタの作製工程では、まずトランジスタ活性層となる半導体島をフォトリソグラフィによってパターニングしてから、ゲート絶縁膜を表面に形成する。しかしこのフォトリソグラフィ工程では、半導体膜表面はレジストを塗布されたり、大気暴露されたりと幾種の工程を含み、その間に半導体膜表面が汚染したり塵が付着したりしてしまう。それゆえ半導体膜とゲート絶縁膜間の界面を清浄に保つことができなく、トランジスタの特性降下や不具合が生じてしまう。レジストを用いた従来のパターニング方式では、レジストの半導体膜への表面汚染と大気暴露が避けられず、故にレジストを用いず、且つ半導体膜の堆積から半導体島のパターニングとゲート絶縁膜の堆積までの間、大気暴露をしなくてもよい新しいパターニング方式が望まれる。Further, in a manufacturing process of a top gate type thin film transistor which is currently generally used, first, a semiconductor island to be a transistor active layer is patterned by photolithography, and then a gate insulating film is formed on the surface. However, in this photolithography process, the surface of the semiconductor film includes various steps such as application of a resist and exposure to the air, during which the surface of the semiconductor film is contaminated or dust adheres. Therefore, the interface between the semiconductor film and the gate insulating film cannot be kept clean, resulting in a decrease in transistor characteristics and inconvenience. In the conventional patterning method using a resist, surface contamination of the resist to the semiconductor film and exposure to the air are inevitable, so no resist is used, and from the deposition of the semiconductor film to the patterning of the semiconductor island and the deposition of the gate insulating film. In the meantime, a new patterning method that does not require exposure to the air is desired.

本発明は、かかる課題を解決することで優れた性能の薄膜トランジスタを提供することを目的とする。An object of the present invention is to provide a thin film transistor having excellent performance by solving such a problem.

課題を解決するための手段Means for solving the problem

まず最初に半導体膜を結晶化させる手段を図1(a)から図1(f)の断面図を用いて説明する。図の方向に関しては左側にxyzそれぞれの方向を表記した。基板10はxy方向と平行に置いてある。まず基板10上にパッシベーション膜15としてSiO2膜を堆積する。その後パッシベーション膜15上に半導体膜20fを堆積してから図1(b)に示すように半導体膜20fを薄膜トランジスタの活性領域となる半導体島20にパターニングする。この半導体膜20f形成から半導体島20へのパターニングまでの工程を半導体島形成工程とする。半導体島20の表面形状は後で説明するが、図10Aから図10Dに示す形状とする。続いて図1(c)に示す通り半導体島20の表面に絶縁性被覆膜30aを形成する。これを被覆膜形成工程とする。First, means for crystallizing a semiconductor film will be described with reference to the cross-sectional views of FIGS. Regarding the directions in the figure, the directions of xyz are shown on the left side. The substrate 10 is placed parallel to the xy directions. First, an SiO 2 film is deposited as a passivation film 15 on the substrate 10. After that, a semiconductor film 20f is deposited on the passivation film 15, and then the semiconductor film 20f is patterned into a semiconductor island 20 to be an active region of the thin film transistor as shown in FIG. The process from the formation of the semiconductor film 20f to the patterning of the semiconductor island 20 is referred to as a semiconductor island formation process. Although the surface shape of the semiconductor island 20 will be described later, the shape is shown in FIGS. 10A to 10D. Subsequently, an insulating coating film 30a is formed on the surface of the semiconductor island 20, as shown in FIG. This is referred to as a coating film forming step.

続いてレーザ光40を基板へ入射させる。これを結晶化工程とする。この際、レーザ光は図1(d)に示すように基板10の半導体島20が形成されている一面からでの入射でも、或いは図1(d)−2に示されるように基板10の半導体島20が形成されている面の反対側から入射させても同じ効果が得られる。レーザ光を半導体島に照射させて溶融させると、半導体島20の周囲部では横方向熱流出50aと下方向熱流出50bがあるのに対して島の中心部では下方向熱流出50bしかないため、島の周囲部の温度降下は島の中心部のそれに比べて早い。したがって半導体島の周囲部は中央部に先んじて結晶核が発生して半導体島の中央部に向かって横方向成長する。Subsequently, the laser light 40 is incident on the substrate. This is a crystallization step. At this time, the laser light may be incident from one surface of the substrate 10 on which the semiconductor island 20 is formed as shown in FIG. 1D, or the semiconductor light may be incident on the substrate 10 as shown in FIG. The same effect can be obtained even if the light is incident from the opposite side of the surface on which the island 20 is formed. When a semiconductor island is irradiated with a laser beam and melted, there is a lateral heat outflow 50a and a downward heat outflow 50b around the semiconductor island 20, whereas there is only a downward heat outflow 50b in the center of the island. The temperature drop around the island is faster than that at the center of the island. Therefore, crystal nuclei are generated in the peripheral portion of the semiconductor island ahead of the central portion and grow laterally toward the central portion of the semiconductor island.

図10(a)〜図10(d)の様々な形状を持つ半導体島20を結晶化させた後の結晶粒の様相を図11(a)〜図11(d)に示す。y方向の島幅とx方向の島幅が同じ場合では結晶成長がぶつかり合ったことにより生じた大粒界201aがX字型に存在する。一方でx方向の島幅とy方向の島幅の差を大きくした図11(b)では、x方向と平行なる粒界は、半導体島のx方向の両端201cをぬいて中心の一本201bのみになる。従ってこの構造でトランジスタを作る際に、図7(b)もしくは図8(b)で示すように、トランジスタのチャネルのキャリア進行方向を狭い横幅をもつy方向にして、且つx方向に伸びる中央粒界201bを避けてチャネルを作製すれば、キャリアがチャネル内で横切る結晶粒界をなくすことができる。島のx方向の両端部ではキャリアが横切る結晶粒界201cは存在するが、島のx方向とy方向の幅の差異を大きくすれば、その影響は小さくできる。このようにしてトランジスタの性能を飛躍的に向上することができる。また、半導体島20のチャネル領域表面は極めて平坦性であるため、更にトランジスタの特性は均一となる。FIGS. 11 (a) to 11 (d) show aspects of crystal grains after crystallizing the semiconductor islands 20 having various shapes shown in FIGS. 10 (a) to 10 (d). When the island width in the y direction and the island width in the x direction are the same, a large grain boundary 201a generated by collision of crystal growth exists in an X shape. On the other hand, in FIG. 11B in which the difference between the island width in the x direction and the island width in the y direction is large, a grain boundary parallel to the x direction is formed by exposing both ends 201c of the semiconductor island in the x direction and having one center 201b. Only. Therefore, when manufacturing a transistor with this structure, as shown in FIG. 7B or FIG. 8B, the carrier traveling direction of the channel of the transistor is set to the y direction having a narrow lateral width, and the central grain extending in the x direction is formed. If a channel is formed avoiding the boundary 201b, a crystal grain boundary where carriers cross in the channel can be eliminated. At both ends of the island in the x direction, there is a crystal grain boundary 201c traversed by carriers. However, the effect can be reduced by increasing the difference in width between the island in the x direction and the y direction. Thus, the performance of the transistor can be dramatically improved. Further, since the surface of the channel region of the semiconductor island 20 is extremely flat, the characteristics of the transistor become more uniform.

更に、半導体島20を例えば図10(c)に示す通り長辺をのこぎり状にすれば、結晶化後は図11(c)に示す通り、凹部20xで発生した結晶粒が凸部20yで発生した結晶粒より先んじて半導体島20の中央に到達するので、結晶粒の数を制御することができる。Furthermore, if the semiconductor island 20 is formed into a saw-like shape on the long side as shown in FIG. 10C, after crystallization, crystal grains generated in the concave portion 20x are generated in the convex portion 20y as shown in FIG. 11C. Since the particles reach the center of the semiconductor island 20 earlier than the crystal grains, the number of crystal grains can be controlled.

更に図10(d)にしめしたように半導体島20に半導体半島210を形成すれば、結晶核はこの半導体半島210から優先して発生し、図11(d)の矢印に示される方向に向かって結晶成長し、その結果半導体島20は単結晶化する。Further, when the semiconductor peninsula 210 is formed in the semiconductor island 20 as shown in FIG. 10D, the crystal nucleus is preferentially generated from the semiconductor peninsula 210 and moves in the direction indicated by the arrow in FIG. As a result, the semiconductor island 20 is monocrystallized.

この図10(a)から図10(d)に示した半導体島20の形状に限らず、その形状を変化させて結晶成長を操ることができる。The crystal growth can be controlled not only by the shape of the semiconductor island 20 shown in FIGS. 10A to 10D but also by changing the shape.

後続するトランジスタ作製工程では、図1(c)に半導体島20上に形成された絶縁性被覆膜30aは、このままゲート絶縁膜として利用できる。この絶縁性被覆膜30aは図1(d)に半導体島20をレーザ40照射する際に同時に高温アニールされるため、良好な絶縁特性、低い界面準位と固定電荷などが得られ、トランジスタの高性能化に寄与する。In a subsequent transistor manufacturing process, the insulating coating film 30a formed on the semiconductor island 20 in FIG. 1C can be used as it is as a gate insulating film. Since the insulating coating film 30a is simultaneously annealed at a high temperature when the semiconductor island 20 is irradiated with the laser 40 in FIG. 1D, good insulating characteristics, low interface states, fixed charges, and the like are obtained. Contributes to higher performance.

絶縁性被覆膜30aにレーザ光40に対して光吸収性を持たない場合には、しかし、横方向結晶成長距離は2ミクロン程度と限られる。仮に図10(b)及び(c)に示した半導体島20のy方向の島幅が横方向結晶成長可能距離の2倍以上であれば、周辺部から中央に向かって横方向結晶成長可能距離までは成長するが、横方向結晶成長は島の中心部までは到達できず、図11(e)に示すように島の中心部で結晶核発生による微結晶領域205が発生してしまう。In the case where the insulating coating film 30a does not have a light absorbing property for the laser beam 40, however, the lateral crystal growth distance is limited to about 2 microns. If the width of the semiconductor island 20 in the y direction shown in FIGS. 10B and 10C is twice or more the distance in which the lateral crystal growth is possible, the lateral crystal growth distance from the peripheral portion toward the center is possible. However, the lateral crystal growth cannot reach the center of the island, and a microcrystalline region 205 is generated at the center of the island due to the generation of crystal nuclei as shown in FIG.

一方で図10(d)に示す半導体島20に関して言えば、半導体島20と半導体半島210の接続部分220から任意の半導体島20の周辺部までの距離が横方向結晶成長距離の2ミクロンよりも長い場合でも、図11(f)に示されるように接続部分220から2ミクロン以上離れてる部分では結晶核発生による微結晶領域205が発生する。したがって寸法が大きい半導体島20を結晶化させる場合では、結晶成長距離を増加させる方法を利用する必要が生じる。On the other hand, regarding the semiconductor island 20 shown in FIG. 10D, the distance from the connection portion 220 between the semiconductor island 20 and the semiconductor peninsula 210 to the peripheral portion of an arbitrary semiconductor island 20 is larger than the lateral crystal growth distance of 2 μm. Even in a long case, as shown in FIG. 11 (f), a microcrystalline region 205 due to the generation of a crystal nucleus occurs in a portion separated from the connection portion 220 by 2 μm or more. Therefore, when crystallizing the semiconductor island 20 having a large size, it is necessary to use a method of increasing the crystal growth distance.

そこで本発明では半導体島20の溶融時間の延ばして横方向結晶成長距離を増加させるために、図1(e)に示すように照射するレーザ光に対して1000〜40000cm−1、望ましくは4000〜14000cm−1の吸収係数をもつ半透明膜30bを被覆膜30a上に形成した。図2に横方向結晶成長距離の半透明膜30bの厚さに対する依存性を示した。ここでの半透明膜の吸収係数は12000cm−1であった。Therefore in order to increase the lateral crystal growth distance by extending the melting time of the semiconductor island 20 in the present invention, 1000~40000cm -1 with respect to the laser beam to be irradiated as shown in FIG. 1 (e), preferably 4000 to A translucent film 30b having an absorption coefficient of 14000 cm -1 was formed on the coating film 30a. FIG. 2 shows the dependence of the lateral crystal growth distance on the thickness of the translucent film 30b. Here, the absorption coefficient of the translucent film was 12000 cm −1 .

図2からわかることに横方向結晶成長距離は半透明膜30bの膜厚によって増加することがわかる。そして半透明膜30bの厚さによって横方向結晶成長距離を伸ばし、図10(a)〜図10(d)のより大きい半導体島20を横方向結晶成長させることができる。例えば図10(b)と(c)で半導体島20のy方向の島幅が10ミクロン以上の場合、横方向結晶成長距離は5ミクロン以上必要であるので、図2から半透明膜30bの厚さは300nm以上にすれば、図11(e)に示した微結晶領域205の発生が防げる。もしくは図10(d)の場合で半導体半島210と半導体島20の付け根部分220から半導体島20の任意の端までの距離が5ミクロンの場合では、横方向結晶成長距離は5ミクロン以上必要であるので、図2から半透明膜30bの厚さは300nm以上にすればよい。FIG. 2 shows that the lateral crystal growth distance increases with the thickness of the translucent film 30b. Then, the lateral crystal growth distance is extended by the thickness of the translucent film 30b, and the larger semiconductor islands 20 shown in FIGS. 10A to 10D can be laterally grown. For example, in FIGS. 10B and 10C, when the island width of the semiconductor island 20 in the y direction is 10 μm or more, the lateral crystal growth distance needs to be 5 μm or more. When the thickness is 300 nm or more, the generation of the microcrystalline region 205 shown in FIG. 11E can be prevented. Alternatively, in the case of FIG. 10D, when the distance from the base portion 220 of the semiconductor peninsula 210 and the semiconductor island 20 to an arbitrary end of the semiconductor island 20 is 5 μm, the lateral crystal growth distance needs to be 5 μm or more. Therefore, the thickness of the translucent film 30b may be set to 300 nm or more from FIG.

この絶縁性被覆膜30aと半透明膜30bはレーザアニールを経ているので、よい絶縁特性を有する。したがって続いてトランジスタを作成する際には、この絶縁性被覆膜30aの少なくとも一部、もしくは絶縁性被覆膜30aと半透明膜30bの少なくとも一部をそのままトランジスタのゲート絶縁膜として利用できる。Since the insulating coating film 30a and the translucent film 30b have undergone laser annealing, they have good insulating properties. Therefore, when a transistor is subsequently formed, at least a part of the insulating coating film 30a or at least a part of the insulating coating film 30a and the translucent film 30b can be used as it is as a gate insulating film of the transistor.

続いて従来の技術の課題で、図1(b)で半導体島20をパターニングする場合、従来のレジストを用いたフォトリソグラフィでは、半導体島20の表面が汚染されやすく、従ってトランジスタを作製する際に完璧な半導体/ゲート絶縁膜の界面が得られないことをこれまでに述べた。本発明では、非晶質半導体膜の表面を酸化させる、或いは、非晶質半導体膜の一部を結晶性に相変化させると、元の非晶質半導体膜よりエッチング速度が遅くなるが故に半導体膜をパターニングできることを発明した。Next, in the case of patterning the semiconductor island 20 in FIG. 1B as a problem of the conventional technology, the surface of the semiconductor island 20 is easily contaminated by photolithography using a conventional resist, and therefore, when the transistor is manufactured, It has been mentioned above that a perfect semiconductor / gate insulating film interface cannot be obtained. In the present invention, when the surface of an amorphous semiconductor film is oxidized or a part of the amorphous semiconductor film is changed to a crystalline phase, the etching rate is lower than that of the original amorphous semiconductor film. Invented that the film can be patterned.

図3に原子状水素のシリコン膜のエッチング速度をしめす。非晶質シリコン膜、結晶シリコン膜、酸化シリコン膜とではエッチング速度は大きく違った。従って非晶質シリコン膜、結晶シリコン膜、酸化シリコン膜間の選択エッチングが可能となる。ここではシリコン膜と酸化シリコン膜間のエッチング速度の違いを利用したパターニング方法を表面酸化パターニング方式とし、非晶質シリコン膜と結晶シリコン膜のエッチング速度の違いを利用したパターニング方法を相変換パターニング方式とする。FIG. 3 shows the etching rate of the atomic hydrogen silicon film. The etching rates of the amorphous silicon film, the crystalline silicon film, and the silicon oxide film were significantly different. Therefore, selective etching between the amorphous silicon film, the crystalline silicon film, and the silicon oxide film can be performed. Here, the patterning method using the difference in etching rate between the silicon film and the silicon oxide film is referred to as a surface oxidation patterning method, and the patterning method using the difference in etching rate between an amorphous silicon film and a crystalline silicon film is referred to as a phase conversion patterning method. And

まず表面酸化パターニング方式を図4を用いて説明する。図4(a)に示されるように、半導体膜20fを酸素2の雰囲気に保った状態で、フォトマスク3を通した光ビーム41を照射する。すると光ビーム41が照射された部分の半導体膜20fの表面に酸化膜22が形成される。このときフォトマスク3の光を通過するパターンがシリコン膜に表面酸化膜22となって転写される。この後図4(b)に示すように原子状水素1等で気相エッチングすると酸化膜22は半導体膜20fに対してエッチング速度が著しく遅いので、表面が酸化膜22で覆われていない部分を選択除去することができる。この結果、フォトマスク3の光を通過するパターン通りに半導体島20が形成される。First, the surface oxidation patterning method will be described with reference to FIG. As shown in FIG. 4A, a light beam 41 passing through the photomask 3 is irradiated while the semiconductor film 20f is kept in an atmosphere of oxygen 2. Then, an oxide film 22 is formed on the surface of the semiconductor film 20f where the light beam 41 has been irradiated. At this time, the pattern of the photomask 3 that transmits light is transferred to the silicon film as the surface oxide film 22. Thereafter, as shown in FIG. 4 (b), when the oxide film 22 is vapor-phase etched with atomic hydrogen 1 or the like, the etching rate of the oxide film 22 is much lower than that of the semiconductor film 20f. Can be selectively removed. As a result, the semiconductor islands 20 are formed according to the pattern of the photomask 3 that allows the light to pass.

続いて図5を用いて相変換パターニング方式について述べる。まず図5(a)に示されたように非晶質半導体膜20fにフォトマスク3を通したレーザ40を照射する。するとレーザ光照射された部分は結晶化半導体膜20gとなる。すなわちフォトマスク3の光を通過するパターンが結晶性半導体となって転写される。この後図5(b)に示す通りに、原子状水素1等を用いて結晶性半導体となっていない部分を選択除去する。この結果、フォトマスク3の光を通過するパターン通りに半導体島20が形成される。Next, a phase conversion patterning method will be described with reference to FIG. First, as shown in FIG. 5A, the amorphous semiconductor film 20f is irradiated with the laser 40 through the photomask 3. Then, the portion irradiated with the laser beam becomes the crystallized semiconductor film 20g. That is, the pattern of the photomask 3 that passes light is transferred as a crystalline semiconductor. Thereafter, as shown in FIG. 5B, a portion which is not a crystalline semiconductor is selectively removed using atomic hydrogen 1 or the like. As a result, the semiconductor islands 20 are formed according to the pattern of the photomask 3 that allows the light to pass.

以上ではエッチングガスとして原子状水素1を用いたが、これ以外にも、水素イオン、CF4、NF4などのフッ化炭素系或いはフッ化窒素系ガスのプラズマを利用しても同じ効果がえられる。In the above description, atomic hydrogen 1 was used as an etching gas. However, the same effect can be obtained by using a plasma of a hydrogen fluoride gas, such as a carbon fluoride gas such as CF4 and NF4, or a nitrogen fluoride gas.

また以上では新しい半導体膜のパターニング方法を示したが、もちろんこの発明は半導体に限られるものではなく、金属膜のパターニングへも応用可能であることは言うまでもない。Although a new method of patterning a semiconductor film has been described above, it is needless to say that the present invention is not limited to a semiconductor and can be applied to patterning of a metal film.

以上に示した新しい半導体膜結晶化方法、ゲート絶縁膜形成方法、パターニング方法などの発明を組み合わせると、少なくとも、図1(a)の半導体膜の形成、図1(b)の半導体島のパターニング、図1(c)のゲート絶縁膜の形成、までを、大気暴露させない状態で完成させることができる。By combining inventions such as the new semiconductor film crystallization method, gate insulating film forming method, and patterning method described above, at least the formation of the semiconductor film of FIG. 1A, the patterning of the semiconductor island of FIG. The process up to the formation of the gate insulating film in FIG. 1C can be completed without being exposed to the air.

この発明を実現できるマルチチャンバー半導体装置製造装置の一例を図6に示す。半導体装置の製造手順を図6と図1を用いて説明する。まず図6気相成膜室114において図1(a)の基板10表面にパッシベーション膜15としてSiO2を堆積する。続いて基板10を図6気相成膜室113に搬送して半導体膜20fを形成する。その後基板10を図6のレーザ照射露光室112に搬送して、表面酸化パターニング方式によれば図4(a)で示した通りに光41としてレーザ光をフォトマスクを通して半導体膜20fへ入射させて、半導体膜20fの一部の表面にフォトマスク通りに表面酸化膜を形成させた。または相変換パターニング方式によれば図5(b)で示した通りにレーザ光をフォトマスクに通して半導体膜20fへ入射させて、半導体膜20fの一部をフォトマスク通りに結晶化させた。FIG. 6 shows an example of a multi-chamber semiconductor device manufacturing apparatus capable of realizing the present invention. The manufacturing procedure of the semiconductor device will be described with reference to FIGS. First, SiO 2 is deposited as a passivation film 15 on the surface of the substrate 10 in FIG. Subsequently, the substrate 10 is transported to the vapor deposition chamber 113 in FIG. 6 to form the semiconductor film 20f. After that, the substrate 10 is transferred to the laser irradiation exposure chamber 112 in FIG. 6, and according to the surface oxidation patterning method, as shown in FIG. Then, a surface oxide film was formed on a part of the surface of the semiconductor film 20f according to a photomask. Alternatively, according to the phase conversion patterning method, as shown in FIG. 5B, a laser beam is passed through a photomask and made incident on the semiconductor film 20f, and a part of the semiconductor film 20f is crystallized according to the photomask.

続いて基板10を図6の気相エッチング室118に搬送して図4(b)に示されたように表面に酸化膜22が形成されていない半導体膜20f、もしくは図5(b)に示された結晶に相変換されていない半導体膜20f、を気相エッチングにより除去して、図1(b)に示されるような半導体島20を形成した。半導体島20の表面形状は図10(a)〜10(d)のいずれでもよい。Subsequently, the substrate 10 is transferred to the vapor-phase etching chamber 118 shown in FIG. 6, and the semiconductor film 20f having no oxide film 22 formed on the surface as shown in FIG. 4B, or as shown in FIG. 5B. The semiconductor film 20f, which has not been converted into the crystal, is removed by vapor phase etching to form a semiconductor island 20 as shown in FIG. The surface shape of the semiconductor island 20 may be any of FIGS.

続いて基板10を気相成膜室114に搬送して、図1(c)に示す通りに表面に絶縁性被覆膜30a、半透明膜30bなどを堆積する。これ以降では基板10を大気に暴露してもよいが、引き続きのレーザアニールの段階でも図6の半導体装置製造装置が利用できる。再び基板を図6のレーザ照射露光室112に搬送して図1(d)もしくは図1(f)に示すようにレーザ光40を照射し、半導体島20を結晶化させる。これで一連のプロセスを大気暴露させない状態で完成することができる。この方法では特に半導体島20/ゲート絶縁膜30a間の界面品質が確保でき、歩留まり高く均一度の高い高性能トランジスタが形成できる。Subsequently, the substrate 10 is transported to the vapor deposition chamber 114, and an insulating coating film 30a, a translucent film 30b, and the like are deposited on the surface as shown in FIG. Thereafter, the substrate 10 may be exposed to the atmosphere, but the semiconductor device manufacturing apparatus of FIG. 6 can be used even in the subsequent laser annealing stage. The substrate is transported again to the laser irradiation exposure chamber 112 in FIG. 6 and irradiated with the laser light 40 as shown in FIG. 1D or 1F to crystallize the semiconductor island 20. Thus, a series of processes can be completed without being exposed to the atmosphere. According to this method, particularly, the quality of the interface between the semiconductor island 20 and the gate insulating film 30a can be ensured, and a high-performance transistor with high yield and high uniformity can be formed.

もちろん、このマルチチャンバーにもう一つ金属膜堆積室を附けて引き続きゲート電極となる金属膜もしくは低抵抗半導体膜を堆積して、図4と図5に示したパターニング方法と同じ要領で、ゲート電極をパターニングすることもできる。また図6ではレーザ照射露光室112を気相エッチング室として兼用してもよい。またこの発明は薄膜トランジスタに限らず、あらゆる薄膜デバイスに応用可能である。Of course, another metal film deposition chamber is attached to this multi-chamber and a metal film or a low-resistance semiconductor film to be a gate electrode is successively deposited, and the gate electrode is deposited in the same manner as the patterning method shown in FIGS. Can be patterned. In FIG. 6, the laser irradiation exposure chamber 112 may also be used as a gas phase etching chamber. The present invention is not limited to thin film transistors, but can be applied to any thin film device.

発明の実施形態Embodiment of the Invention

以下、本発明の実施形態による薄膜半導体装置及びその製造方法について詳細に説明する。Hereinafter, a thin film semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described in detail.

(実施例1)実施例1においては、本発明におけるトランジスタの作製方法を図1(a)〜図1(f)を用いて説明する。まず図1(a)にてガラス基板10上にパッシベーション膜15として酸化シリコン膜をTEOS(テトラエトキシシラン)を原料に用いたPECVDにより300℃にて300nm堆積する。続いて半導体膜20fとして非晶質シリコン膜をジシランを原料に用いたLPCVD法で500℃にて50nm堆積する。そして図1(b)の通り非晶質シリコン膜をパターニングして半導体島20とした。ここで半導体島20の表面形状は、図10(a)(b)(c)(d)に示す通りである。ここで半導体島20の本体の寸法は1μm×2μmから15μm×30μmの寸法をもつ。次に図1(c)の通り、半導体島20の上に絶縁性被覆膜30aとしてSiO膜をTEOS(テトラエトキシシラン)と酸素と窒素を原料に用いたPECVDを用いて300℃で100nm堆積した。そして一部の半導体島20の表面に図1(e)に示されるように半透明膜30bとしてTMS(テトラメチルシラン)と酸素と窒素を原料に用いたPECVDを用いて300℃で、レーザ光40に対して吸収係数が10000cm−1のSiON膜を500nm形成した。(Embodiment 1) In Embodiment 1, a method for manufacturing a transistor of the present invention will be described with reference to FIGS. First, in FIG. 1A, a silicon oxide film is deposited as a passivation film 15 on a glass substrate 10 by PECVD using TEOS (tetraethoxysilane) at 300 ° C. to a thickness of 300 nm. Subsequently, an amorphous silicon film is deposited as a semiconductor film 20f by LPCVD using disilane as a raw material at 50 ° C. to a thickness of 50 nm. Then, as shown in FIG. 1B, the amorphous silicon film was patterned to form a semiconductor island 20. Here, the surface shape of the semiconductor island 20 is as shown in FIGS. 10 (a), (b), (c) and (d). Here, the main body of the semiconductor island 20 has a size of 1 μm × 2 μm to 15 μm × 30 μm. Next, as shown in FIG. 1C, a SiO 2 film is formed as an insulating coating film 30 a on the semiconductor island 20 at 300 ° C. and 100 nm by PECVD using TEOS (tetraethoxysilane) and oxygen and nitrogen as raw materials. Deposited. Then, as shown in FIG. 1E, a laser beam is applied to the surface of some of the semiconductor islands 20 at 300 ° C. using TMS (tetramethylsilane), PECVD using oxygen and nitrogen as raw materials as a semitransparent film 30b. A 40 nm SiON film having an absorption coefficient of 10,000 cm −1 was formed at a thickness of 500 nm.

まず図1(d)に示す構造において、レーザ光40を半導体島20に照射して結晶化させた。半導体島20の表面形状が図10(a)〜図10(c)においてy方向の島幅が4ミクロン以下の場合では結晶化後の半導体島の結晶粒成長様相は図11(a)〜図11(c)に示す通りとなるが、y方向の島幅がこの寸法を越えると横方向結晶成長距離の不足により図11(e)のように微結晶領域205が生じてしまう。もしくは半導体島の形状が図10(d)に示す場合で、半導体半島210と半導体島20の接続部220から半導体島の任意の端までの距離が2ミクロン以下の場合では、レーザアニール後の半導体島20は図11(d)に示す通り単結晶化するが、この寸法を超えるとやはり図11(f)に示すように半導体島20の一部に微結晶化領域205が生じてしまった。図11(e)や図11(f)などに示される微結晶化領域の発生を防ぐために、図1(e)に示されるとおり、図1(c)の表面に、半透明膜30bとしてSiON膜を堆積した。ここでSiON半透明膜30bはTEOS(テトラエトキシシラン)と酸素と窒素を原料に用いたPECVDを用いて300℃で500nm堆積した。半透明膜の吸収係数は照射するレーザ光に対してof2000−20000cm−1,望ましくは4000−12000cm−1のものを用いた。そして図1(f)に示すようにレーザ光40を半導体島20に照射して結晶化を図った。この結果、図10(a)〜図10(d)に示される半導体島20は図11(a)〜図11(d)の通りに結晶化した。First, in the structure shown in FIG. 1D, the semiconductor island 20 was irradiated with a laser beam 40 to be crystallized. When the surface shape of the semiconductor island 20 is 4 μm or less in the y direction in FIGS. 10A to 10C, the crystal growth state of the semiconductor island after crystallization is shown in FIGS. As shown in FIG. 11C, when the island width in the y-direction exceeds this dimension, the microcrystalline region 205 is generated as shown in FIG. Alternatively, in the case where the shape of the semiconductor island is as shown in FIG. 10D and the distance from the connection portion 220 between the semiconductor peninsula 210 and the semiconductor island 20 to an arbitrary end of the semiconductor island is 2 μm or less, the semiconductor after laser annealing is performed. Although the island 20 is monocrystallized as shown in FIG. 11D, if the size exceeds this size, a microcrystallized region 205 is formed in a part of the semiconductor island 20 as shown in FIG. 11F. As shown in FIG. 1E, the surface of FIG. 1C is made of SiON as a translucent film 30b in order to prevent the generation of the microcrystallized region shown in FIGS. 11E and 11F. The film was deposited. Here, the SiON translucent film 30b was deposited at 300 ° C. and 500 nm by PECVD using TEOS (tetraethoxysilane), oxygen and nitrogen as raw materials. Absorption coefficient of the semi-transparent film Of2000-20000cm -1 with respect to the laser beam to be irradiated, preferably with those 4000-12000cm -1. Then, as shown in FIG. 1F, the semiconductor island 20 was irradiated with a laser beam 40 to achieve crystallization. As a result, the semiconductor islands 20 shown in FIGS. 10A to 10D crystallized as shown in FIGS. 11A to 11D.

続いてトップゲート型トランジスタの作製工程に入るが、図11(b)〜図11(d)に示された半導体島20はそのままトランジスタの活性層として残す。図1(d)に示されるように半導体島20の上には絶縁性被覆膜30aが形成されているが、これをそのままトランジスタのゲート絶縁膜とした。もしくは図1(f)に示すように半透明膜30bが表面に形成されている場合では半透明膜30bを選択エッチングして図1(d)の構造とした。この場合でも絶縁性被覆膜30aはゲート絶縁膜とした。Subsequently, a process for manufacturing a top gate transistor is started, but the semiconductor island 20 shown in FIGS. 11B to 11D is left as an active layer of the transistor. As shown in FIG. 1D, an insulating coating film 30a is formed on the semiconductor island 20, and this is used as it is as a gate insulating film of the transistor. Alternatively, when the translucent film 30b is formed on the surface as shown in FIG. 1F, the translucent film 30b is selectively etched to obtain the structure shown in FIG. Also in this case, the insulating coating film 30a was a gate insulating film.

続いて図7〜図9を用いてトランジスタの作製工程を説明する。まず図1(d)の絶縁性被覆膜30aの上に例えばTa金属膜をスパッタ堆積法を用いて堆積し、その後Ta金属膜をパターニングしてゲート電極60とした。ここでゲート電極60の形状は図11(b)〜図11(d)に示した半導体島20の形状によって決まった。Next, a manufacturing process of the transistor will be described with reference to FIGS. First, for example, a Ta metal film was deposited on the insulating coating film 30a of FIG. 1D by using a sputter deposition method, and then the Ta metal film was patterned to form a gate electrode 60. Here, the shape of the gate electrode 60 is determined by the shape of the semiconductor island 20 shown in FIGS. 11B to 11D.

まず図11(b)と図11(c)の半導体島20の構造の場合を説明する。この場合ではゲート電極60は図7(a)(b)に示したデュアルゲート構造、もしくは図8(a)(b)のシングルゲート構造とすることができる。これらの場合では、ゲート電極60を半導体島20の中央粒界201bを避けるようにして配置させる。一方で半導体島20の形状が図11(d)であれば、この半導体島は単結晶であるので、ゲート電極60はシングルゲートでもマルチゲートでもよい。図9(a)(b)にシングルゲートを配置させた例を示す。本実施例においても図9(a)(b)に示したとおりにゲート電極60を配置させた。First, the case of the structure of the semiconductor island 20 in FIGS. 11B and 11C will be described. In this case, the gate electrode 60 can have a dual gate structure shown in FIGS. 7A and 7B or a single gate structure shown in FIGS. 8A and 8B. In these cases, the gate electrode 60 is arranged so as to avoid the central grain boundary 201b of the semiconductor island 20. On the other hand, if the shape of the semiconductor island 20 is as shown in FIG. 11D, since the semiconductor island is a single crystal, the gate electrode 60 may be a single gate or a multi-gate. FIGS. 9A and 9B show examples in which a single gate is arranged. Also in the present embodiment, the gate electrode 60 is arranged as shown in FIGS.

続く工程において図7(c)(d)、もしくは図8(c)(d)、もしくは図9(c)(d)に示されるように、ゲート電極60をマスクとしてシリコン島のソース20bとドレイン20cとなる場所、及び201b近傍の両チャネルの結合部を自己整合的にイオン注入法でアクセプタイオン或いはドナーイオンを注入した。In a subsequent step, as shown in FIGS. 7C, 7D, 8C, 8D, or 9C, 9D, the source 20b and the drain of the silicon island are formed using the gate electrode 60 as a mask. Acceptor ions or donor ions were implanted in a self-aligned manner by ion implantation at the location 20c and at the junction of both channels near 201b.

その後、図7(e)(f)、もしくは図8(e)(f)、もしくは図9(e)(f)に示すように、層間絶縁膜90としてPECVDにより500nmのSiOをTEOSを用いたPECVD法で形成する。そしてレーザ或いはファーネスによるアニールでソースドレイン領域20b、20cと両チャネル結合部のドーパントの活性化と層間絶縁膜90の改質をおこなった。ソースドレイン領域のコンタクトホール87を形成し、コンタクトホールを介してソース電極70とドレイン電極80をそれぞれ形成して、TFTを完成させた。Thereafter, as shown in FIGS. 7 (e) and (f), FIGS. 8 (e) and (f), or FIGS. 9 (e) and (f), 500 nm of SiO 2 is formed by TECVD using TEOS as the interlayer insulating film 90. It is formed by the PECVD method. Then, the dopants in the source / drain regions 20b and 20c and the channel coupling portion were activated and the interlayer insulating film 90 was reformed by annealing with laser or furnace. A contact hole 87 in the source / drain region was formed, and a source electrode 70 and a drain electrode 80 were formed through the contact hole, thereby completing the TFT.

本発明による薄膜トランジスタ装置によれば、ゲート電極直下に形成されるチャネルには、キャリアが移動する方向に垂直な方向に伸びる結晶粒界が存在しなく、且つゲート絶縁膜はこれまでの低温堆積方法の膜と比べて特性が格段に向上するため、薄膜トランジスタは単結晶トランジスタ並みの高性能のスイッチング特性を有し、しかも、トランジスタの特性のばらつきがないトランジスタを製造することができる。半導体島20の表面形状が図11(b)もしくは図11(c)の場合では、TFTの移動度は360cm2/vsと、良好な特性が得られた。一方で半導体島20の表面形状が図11(d)の場合では、TFTの移動度は460cm2/vsと、更に良好な特性が得られた。According to the thin film transistor device according to the present invention, the channel formed immediately below the gate electrode does not have a crystal grain boundary extending in a direction perpendicular to the direction in which carriers move, and the gate insulating film is formed by a conventional low-temperature deposition method. Since the characteristics are remarkably improved as compared with the above film, the thin film transistor can be manufactured as a transistor having high-performance switching characteristics comparable to a single crystal transistor, and having no variation in transistor characteristics. In the case where the surface shape of the semiconductor island 20 is as shown in FIG. 11B or FIG. 11C, the mobility of the TFT was 360 cm 2 / vs, and good characteristics were obtained. On the other hand, when the surface shape of the semiconductor island 20 was as shown in FIG. 11D, the mobility of the TFT was 460 cm 2 / vs, and further excellent characteristics were obtained.

(実施例2)本発明はレジストを用いず且つ大気に暴露されずに半導体膜をパターニングする新しいパターニング方式に関するものであり、図1及び図6を用いて説明する。図1(a)〜図1(f)にトランジスタの製造過程を示した。また実施するにあたって使用したマルチチャンバー型半導体装置製造装置は図6に示した。図6に示す半導体装置製造装置には複数のチャンバー(室)が含まれており、薄膜を堆積する一つ以上の気相成膜室113または114、薄膜にレーザを照射するレーザ照射露光室112、薄膜をエッチングする気相エッチング室118、基板搬送手段121、それぞれのチャンバーの内部を真空にする排気装置119、基板の導入と取り出しとして受渡室116、から構成される。また基板の前処理として前処理室117を取り付けることも可能である。(Embodiment 2) The present invention relates to a new patterning method for patterning a semiconductor film without using a resist and without being exposed to the atmosphere, which will be described with reference to FIGS. 1A to 1F show a process of manufacturing a transistor. FIG. 6 shows a multi-chamber type semiconductor device manufacturing apparatus used in the embodiment. The semiconductor device manufacturing apparatus shown in FIG. 6 includes a plurality of chambers (chambers), one or more vapor deposition chambers 113 or 114 for depositing a thin film, and a laser irradiation exposure chamber 112 for irradiating a laser to the thin film. A gas phase etching chamber 118 for etching a thin film, a substrate transfer means 121, an exhaust device 119 for evacuating the inside of each chamber, and a delivery chamber 116 for introducing and removing a substrate. Further, a pre-processing chamber 117 can be attached as pre-processing of the substrate.

まず基板10はマルチチャンバー半導体装置製造装置の受渡室116へ導入され、ストック室115を通じて前処理室117へと移送され基板洗浄が行われる。その後PECVDで薄膜堆積ができる気相成膜室114へ搬入され、図1(a)に示すようにガラス基板10上にパッシベーション膜15として酸化シリコン膜をTEOS(テトラエトキシシラン)を原料に用いたPECVDにより300℃にて300nm堆積した。続いてシランを原料としたPECVD薄膜堆積ができる気相成膜室113へと搬入され、半導体膜20fとして非晶質シリコン膜を50nm堆積した。非晶質シリコン膜を堆積後の状態では非晶質シリコン膜表面は水素終端された状態で、酸化されにくい状態になっており、この状態は室温で数時間保つことができる。First, the substrate 10 is introduced into the delivery chamber 116 of the multi-chamber semiconductor device manufacturing apparatus, transferred to the pretreatment chamber 117 through the stock chamber 115, and subjected to substrate cleaning. Thereafter, the substrate is carried into a vapor deposition chamber 114 where a thin film can be deposited by PECVD, and a silicon oxide film is used as a passivation film 15 on a glass substrate 10 using TEOS (tetraethoxysilane) as a raw material, as shown in FIG. Deposited 300 nm at 300 ° C. by PECVD. Subsequently, the wafer was carried into a vapor-phase deposition chamber 113 where a PECVD thin film could be deposited using silane as a raw material, and an amorphous silicon film having a thickness of 50 nm was deposited as a semiconductor film 20f. After the deposition of the amorphous silicon film, the surface of the amorphous silicon film is hydrogen-terminated and hardly oxidized, and this state can be maintained at room temperature for several hours.

その後、基板10をレーザ照射露光室112へ搬入し、図4に示すように酸素雰囲気にした状態でレーザ光を光41としてフォトマスク3を通して非晶質シリコン膜20fに照射する。ここでこの光41は0.01mJ/cm2〜800mJ/cm2、望ましくは1mJ/cm2〜400mJ/cm2であり、照射回数は一回以上あればよい。光照射したあと、光41にあたった部分は非晶質シリコンが雰囲気の酸素により酸化され、表面に酸化シリコン膜22が形成される。この状態で、基板を気相エッチング室118へと搬送する。気相エッチング室118ではタングステンフィラメントが1200〜2600℃、望ましくは1800〜2100℃に保たれた状態で水素が原子状水素へと分解される。そして図4(b)に示されるように、表面に酸化膜22が形成されていないシリコン膜20fは原子状水素によってエッチングされる。これによってシリコン島20をパターニングすることができた。ここでシリコン島20の形状は図10(b),(c),(d)のいずれでもよい。次に基板10はPECVD気相成膜室114へ搬入され、パターニングされたシリコン島20の上に図1(c)に示すように絶縁性被覆膜30aとしてSiO膜をTEOS(テトラエトキシシラン)を原料に用いたPECVDを用いて100nm堆積した。そして続いてTMS(テトラメチルシラン)と酸素と窒素を原料に用いたPECVDを用いて、300℃においてSiON膜を半透明膜30bとして堆積する。この半透明膜は照射するレーザ光40に対して吸収係数が2000−20000cm−1,望ましくは4000−12000cm−1のものを用いた。12000cm−1のSiON膜であり、厚さは500nm形成した。After that, the substrate 10 is carried into the laser irradiation exposure chamber 112, and the amorphous silicon film 20f is irradiated with the laser light 41 as the light 41 through the photomask 3 in an oxygen atmosphere as shown in FIG. Here, the light 41 is 0.01 mJ / cm2 to 800 mJ / cm2, preferably 1 mJ / cm2 to 400 mJ / cm2, and the number of times of irradiation may be one or more. After light irradiation, amorphous silicon is oxidized by oxygen in the atmosphere in a portion exposed to light 41, and a silicon oxide film 22 is formed on the surface. In this state, the substrate is transported to the vapor phase etching chamber 118. In the vapor phase etching chamber 118, hydrogen is decomposed into atomic hydrogen while the tungsten filament is kept at 1200 to 2600 ° C., preferably 1800 to 2100 ° C. Then, as shown in FIG. 4B, the silicon film 20f on which the oxide film 22 is not formed on the surface is etched by atomic hydrogen. As a result, the silicon island 20 could be patterned. Here, the shape of the silicon island 20 may be any of FIGS. 10B, 10C, and 10D. Next, the substrate 10 is carried into the PECVD vapor deposition chamber 114, and an SiO 2 film is formed on the patterned silicon island 20 as an insulating coating film 30a by TEOS (tetraethoxysilane) as shown in FIG. ) Was deposited to a thickness of 100 nm by using PECVD using as a raw material. Subsequently, an SiON film is deposited as a translucent film 30b at 300 ° C. by using PECVD using TMS (tetramethylsilane), oxygen and nitrogen as raw materials. The semi-transparent film absorption coefficients for the laser beam 40 to be irradiated 2000-20000cm -1, desirably used was the 4000-12000cm -1. It was a SiON film of 12000 cm -1 and was formed to a thickness of 500 nm.

続いて基板10をレーザ照射露光室112へ導入し、図1(d)もしくは図1(f)に示す通りにレーザ光40を半導体島20に照射した。この結果図11(b)、(c)、(d)に示す通りに半導体島20は結晶化した。Subsequently, the substrate 10 was introduced into the laser irradiation exposure room 112, and the semiconductor island 20 was irradiated with the laser light 40 as shown in FIG. 1D or 1F. As a result, the semiconductor island 20 was crystallized as shown in FIGS. 11 (b), (c) and (d).

続いて薄膜トランジスタを作製するが、これ以降のプロセスは実施例1と同じプロセスで作成した。Subsequently, a thin film transistor was manufactured, and the subsequent processes were manufactured in the same process as in Example 1.

この実施例2において、少なくとも半導体膜20fを堆積する半導体膜形成工程、半導体膜をパターニングして半導体島20を形成する半導体島形成工程、絶縁性被覆膜30aを形成する絶縁性被覆膜までの一連のプロセスが大気暴露しないで一貫実施することができたので、素子の性能向上、素子性能のばらつきの低減、歩留まりの向上、更には生産性の向上につながった。この実施例2を実施した結果、n型トランジスタの移動度が560cm2/vs、S値が0.2V/dec,Vthが0.1Vと良好な特性が得られた。またこの方式では閾値電圧のばらつきは50mV以内と均一なトランジスタ特性分布が得られた。In the second embodiment, at least a semiconductor film forming step of depositing a semiconductor film 20f, a semiconductor island forming step of patterning a semiconductor film to form a semiconductor island 20, and an insulating coating film of forming an insulating coating film 30a. Can be performed without exposure to the air, which leads to improved device performance, reduced variation in device performance, improved yield, and improved productivity. As a result of carrying out Example 2, good characteristics were obtained in which the mobility of the n-type transistor was 560 cm 2 / vs, the S value was 0.2 V / dec, and Vth was 0.1 V. In addition, in this method, variation in threshold voltage was within 50 mV, and a uniform transistor characteristic distribution was obtained.

(実施例3)本発明はレジストを用いず且つ大気に暴露されずに半導体膜をパターニングする新しいパターニング方式に関するものであり、図1及び図6を用いて説明する。図1(a)〜図1(f)にトランジスタの製造過程を示した。また実施するにあたって使用したマルチチャンバー型半導体装置製造装置は図6に示した。図6に示す半導体装置製造装置には複数のチャンバー(室)が含まれており、薄膜を堆積する一つ以上の気相成膜室113または114、薄膜にレーザを照射するレーザ照射露光室112、薄膜をエッチングする気相エッチング室118、基板搬送手段121、それぞれのチャンバーの内部を真空にする排気装置119、基板の導入と取り出しとして受渡室116、から構成される。また基板の前処理として前処理室117を取り付けることも可能である。Embodiment 3 The present invention relates to a new patterning method for patterning a semiconductor film without using a resist and without being exposed to the atmosphere, which will be described with reference to FIGS. 1A to 1F show a process of manufacturing a transistor. FIG. 6 shows a multi-chamber type semiconductor device manufacturing apparatus used in the embodiment. The semiconductor device manufacturing apparatus shown in FIG. 6 includes a plurality of chambers (chambers), one or more vapor deposition chambers 113 or 114 for depositing a thin film, and a laser irradiation exposure chamber 112 for irradiating a laser to the thin film. And a gas phase etching chamber 118 for etching a thin film, a substrate transfer means 121, an exhaust device 119 for evacuating the inside of each chamber, and a delivery chamber 116 for introducing and removing a substrate. Further, a pre-processing chamber 117 can be attached as pre-processing of the substrate.

まず基板10はマルチチャンバー半導体装置製造装置の受渡室116へ導入され、ストック室115を通じて前処理室117へと移送され基板洗浄が行われる。その後PECVDで薄膜堆積ができる気相成膜室114へ搬入され、図1(a)に示すようにガラス基板10上にパッシベーション膜15として酸化シリコン膜をTEOS(テトラエトキシシラン)を原料に用いたPECVDにより300℃にて300nm堆積した。続いてシランを原料としたPECVD薄膜堆積ができる気相成膜室113へと搬入され、図1(a)の通り半導体膜20fとして非晶質シリコン膜を50nm堆積した。First, the substrate 10 is introduced into the delivery chamber 116 of the multi-chamber semiconductor device manufacturing apparatus, transferred to the pretreatment chamber 117 through the stock chamber 115, and subjected to substrate cleaning. Thereafter, the substrate is carried into a vapor deposition chamber 114 where a thin film can be deposited by PECVD, and a silicon oxide film is used as a passivation film 15 on a glass substrate 10 using TEOS (tetraethoxysilane) as a raw material, as shown in FIG. Deposited 300 nm at 300 ° C. by PECVD. Subsequently, the wafer was carried into a vapor deposition chamber 113 where PECVD thin film deposition using silane as a raw material was possible, and an amorphous silicon film was deposited to a thickness of 50 nm as a semiconductor film 20f as shown in FIG.

その後、基板10をレーザ照射露光室112へ搬入し、図5に示すようにレーザ光40をフォトマスク3を通して非晶質シリコン膜20fに照射する。ここでこのレーザ光40は10mJ/cm2〜800mJ/cm2、望ましくは100mJ/cm2〜600mJ/cm2であり、照射回数は一回以上あればよい。光照射したあと、レーザ光40にあたった部分は非晶質シリコンから結晶性シリコン20gへ相変換される。この状態で、基板10を気相エッチング室118へと搬送する。気相エッチング室118ではタングステンフィラメントが1200〜2600℃、望ましくは1800〜2100℃に保たれた状態で水素が原子状水素へと分解される。そして図5(b)に示されるように、相変換されてなかった非晶質シリコン膜20fは原子状水素によってエッチングされる。これによってシリコン島20が形成できた。ここでシリコン島20の形状は図10(b),(c),(d)のいずれでもよい。Thereafter, the substrate 10 is carried into the laser irradiation exposure chamber 112, and the amorphous silicon film 20f is irradiated with the laser light 40 through the photomask 3 as shown in FIG. Here, the laser light 40 is 10 mJ / cm2 to 800 mJ / cm2, preferably 100 mJ / cm2 to 600 mJ / cm2, and the number of times of irradiation may be one or more. After the light irradiation, the portion irradiated with the laser light 40 is phase-converted from amorphous silicon to crystalline silicon 20g. In this state, the substrate 10 is transferred to the vapor phase etching chamber 118. In the vapor phase etching chamber 118, hydrogen is decomposed into atomic hydrogen while the tungsten filament is kept at 1200 to 2600 ° C., preferably 1800 to 2100 ° C. Then, as shown in FIG. 5B, the amorphous silicon film 20f that has not undergone phase conversion is etched by atomic hydrogen. Thereby, the silicon island 20 was formed. Here, the shape of the silicon island 20 may be any of FIGS. 10B, 10C, and 10D.

次に基板10はPECVD気相成膜室114へ搬入され、パターニングされたシリコン島20の上に図1(c)に示すように絶縁性被覆膜30aとしてSiO膜をTEOS(テトラエトキシシラン)を原料に用いたPECVDを用いて100nm堆積した。そして続いてTMS(テトラメチルシラン)と酸素と窒素を原料に用いたPECVDを用いて、300℃においてSiON膜を半透明膜30bとして堆積する。この半透明膜は照射するレーザ光40に対して吸収係数が2000−20000cm−1,望ましくは4000−12000cm−1のものを用いた。12000cm−1のSiON膜であり、厚さは500nm形成した。Next, the substrate 10 is carried into the PECVD vapor deposition chamber 114, and an SiO 2 film is formed on the patterned silicon island 20 as an insulating coating film 30a by TEOS (tetraethoxysilane) as shown in FIG. ) Was deposited to a thickness of 100 nm by using PECVD using as a raw material. Subsequently, an SiON film is deposited as a translucent film 30b at 300 ° C. by using PECVD using TMS (tetramethylsilane), oxygen and nitrogen as raw materials. The semi-transparent film absorption coefficients for the laser beam 40 to be irradiated 2000-20000cm -1, desirably used was the 4000-12000cm -1. It was a SiON film of 12000 cm -1 and was formed to a thickness of 500 nm.

続いて基板10をレーザ照射露光室112へ導入し、図1(d)もしくは図1(f)に示す通りにレーザ光40を半導体島20に照射した。この結果図11(b)、(c)、(d)に示す通りに半導体島20は結晶化した。Subsequently, the substrate 10 was introduced into the laser irradiation exposure room 112, and the semiconductor island 20 was irradiated with the laser light 40 as shown in FIG. 1D or 1F. As a result, the semiconductor island 20 was crystallized as shown in FIGS. 11 (b), (c) and (d).

続いて薄膜トランジスタを作製するが、これ以降のプロセスは実施例1と同じプロセスで作成した。Subsequently, a thin film transistor was manufactured, and the subsequent processes were manufactured in the same process as in Example 1.

この実施例3において、少なくとも半導体膜20fを堆積する半導体膜形成工程、半導体膜をパターニングして半導体島20を形成する半導体島形成工程、絶縁性被覆膜30aを形成する絶縁性被覆膜までの一連のプロセスが大気暴露しないで一貫実施することができたので、素子の性能向上、素子性能のばらつきの低減、歩留まりの向上、更には生産性の向上につながった。この実施例2を実施した結果、n型トランジスタの移動度が550cm2/vs、S値が0.2V/dec,Vthが0.1Vと良好な特性が得られた。またこの方式では閾値電圧のばらつきは50mV以内と均一なトランジスタ特性分布が得られた。In the third embodiment, at least a semiconductor film forming step of depositing the semiconductor film 20f, a semiconductor island forming step of patterning the semiconductor film to form the semiconductor island 20, and an insulating coating film of forming the insulating coating film 30a. Could be performed without exposure to the air, which led to improved device performance, reduced variation in device performance, improved yield, and improved productivity. As a result of carrying out Example 2, good characteristics were obtained in which the mobility of the n-type transistor was 550 cm 2 / vs, the S value was 0.2 V / dec, and Vth was 0.1 V. In addition, in this method, variation in threshold voltage was within 50 mV, and a uniform transistor characteristic distribution was obtained.

また以上の説明では、多結晶薄膜トランジスタの構造としてnonLDD構造を例にして説明したが、LDD構造やGOLD構造など他の構造についても同様に実施可能である。Further, in the above description, the non-LDD structure is described as an example of the structure of the polycrystalline thin film transistor, but other structures such as an LDD structure and a GOLD structure can be similarly implemented.

以上の説明においてレーザ光としてエキシマレーザ光が用いられたが、その波長については、248、308、及び351nmのいづれを用いても同じ結果が得られた。In the above description, an excimer laser beam was used as the laser beam. Regarding the wavelength, the same result was obtained using any of 248, 308, and 351 nm.

なお、本発明の技術範囲は上記実施の形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲において種種の変更を加えることが可能である。例えばTFTの各部を構成する具体的な膜の種類などは適宜変更が可能である。The technical scope of the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the spirit of the present invention. For example, the type of a specific film constituting each part of the TFT can be appropriately changed.

発明の効果The invention's effect

活性領域となる半導体島を形成し、その上にゲート絶縁膜となる絶縁性被覆膜を形成する。そして半導体膜と絶縁性被覆膜を同時にレーザアニールする。この結果、半導体島は全領域において横方向結晶成長し、同時に絶縁性被覆膜は高品質化する。また半導体膜のパターニングについては、半導体膜を酸素雰囲気に維持した状態で、光をマスクに通して半導体膜に照射して部分的に表面極薄酸化膜を形成し、その後選択気相エチングを行うことで表面極薄酸化膜が形成されていない半導体膜を除去することで、レジストを用いずに半導体膜がパターニングできる。以上の工程を大気にさらすことなく連続して行えば、トランジスタ特性が優れ、且つ歩留まりのよい薄膜トランジスタの作製が可能となる。A semiconductor island serving as an active region is formed, and an insulating coating film serving as a gate insulating film is formed thereon. Then, the semiconductor film and the insulating coating film are simultaneously laser-annealed. As a result, the semiconductor island grows in the lateral direction in all regions, and at the same time, the quality of the insulating coating film is improved. As for the patterning of the semiconductor film, while the semiconductor film is maintained in an oxygen atmosphere, light is irradiated to the semiconductor film through a mask to partially form an ultrathin oxide film on the surface, and thereafter, selective vapor phase etching is performed. By removing the semiconductor film on which the surface ultrathin oxide film is not formed, the semiconductor film can be patterned without using a resist. By continuously performing the above steps without exposing to air, a thin film transistor with excellent transistor characteristics and high yield can be manufactured.

(a)〜(f)本発明の実施例による薄膜半導体装置の製造方法の一例を示す工程図の断面図である。(A)-(f) is sectional drawing of the process drawing which shows an example of the manufacturing method of the thin film semiconductor device by the Example of this invention. 横方向結晶成長距離の半透明膜厚さの依存性を示した図であるFIG. 3 is a diagram showing the dependence of the translucent film thickness on the lateral crystal growth distance 非晶質シリコン、結晶性シリコン、酸化シリコンの原子状水素に対するエッチング速度を示す図である。FIG. 3 is a diagram illustrating an etching rate of amorphous silicon, crystalline silicon, and silicon oxide with respect to atomic hydrogen. (a)(b)本発明の新しい半導体膜のパターニング方法を示す図である(A) and (b) are views showing a novel semiconductor film patterning method of the present invention. (a)(b)本発明の新しい半導体膜のパターニング方法を示す図である(A) and (b) are views showing a novel semiconductor film patterning method of the present invention. 本発明において半導体膜形成工程、半導体島形成工程、絶縁性被覆膜までの一連のプロセスを大気暴露しないで一貫実施するためのマルチチャンバー型半導体装置製造装置を示す図である。FIG. 2 is a view showing a multi-chamber type semiconductor device manufacturing apparatus for performing a series of processes up to a semiconductor film forming step, a semiconductor island forming step, and an insulating coating film without being exposed to the air in the present invention. (a)〜(f)本発明の実施例による薄膜半導体装置の製造方法の一例を示す工程図である。3A to 3F are process diagrams illustrating an example of a method for manufacturing a thin film semiconductor device according to an embodiment of the present invention. (a)〜(f)本発明の実施例による薄膜半導体装置の製造方法の一例を示す工程図である。3A to 3F are process diagrams illustrating an example of a method for manufacturing a thin film semiconductor device according to an embodiment of the present invention. (a)〜(f)本発明の実施例による薄膜半導体装置の製造方法の一例を示す工程図である。3A to 3F are process diagrams illustrating an example of a method for manufacturing a thin film semiconductor device according to an embodiment of the present invention. (a)〜(d)は図1(b)の工程において半導体島の表面形状を示す図である(A)-(d) is a figure which shows the surface shape of a semiconductor island in the process of FIG.1 (b). (a)〜(f)は図1(d)の工程において半導体島のレーザ照射後の結晶成長の様相を示す図である(A)-(f) is a figure which shows the aspect of the crystal growth after laser irradiation of a semiconductor island in the process of FIG.1 (d).

符号の説明Explanation of reference numerals

1 水素原子
2 酸素または窒素
3 フォトマスク
4 投影レンズ系
10 ガラス基板
15 パッシベーション膜
20f 半導体膜
20g 多結晶質半導体膜
20 半導体島
20a チャネル領域
20b ソース領域
20c ドレイン領域
22 酸化膜または窒化膜または酸窒化膜
30 絶縁性被覆膜
30a バッファー膜
30b 半透明膜
50a 横方向熱流出
50b 縦方向熱流出
110 レーザ光源
111 レンズ系
112 レーザ照射露光室
113 気相成膜室
114 気相成膜室
115 ストック室
116 受渡室
117 前処理室
118 気相エッチング室
119 排気装置
121 基板搬送手段
201a X字型結晶粒界
201b 半導体島中央結晶粒界
201c 半導体島のx方向の結晶粒界
205 微結晶領域
210 半導体半島
220 半導体島と半導体半島の接続部分
60 ゲート電極
70 ソース電極
80 ドレイン電極
90 層間絶縁膜
87 コンタクトホール
DESCRIPTION OF SYMBOLS 1 Hydrogen atom 2 Oxygen or nitrogen 3 Photomask 4 Projection lens system 10 Glass substrate 15 Passivation film 20f Semiconductor film 20g Polycrystalline semiconductor film 20 Semiconductor island 20a Channel region 20b Source region 20c Drain region 22 Oxide film or nitride film or oxynitride Film 30 Insulating coating film 30a Buffer film 30b Translucent film 50a Lateral heat outflow 50b Vertical heat outflow 110 Laser light source 111 Lens system 112 Laser irradiation exposure room 113 Vapor deposition chamber 114 Vapor deposition chamber 115 Stock chamber 116 Delivery room 117 Pretreatment chamber 118 Gas phase etching chamber 119 Exhaust device 121 Substrate transfer means 201a X-shaped crystal grain boundary 201b Semiconductor island center crystal grain boundary 201c Semiconductor crystal x-direction crystal grain boundary 205 Microcrystal region 210 Semiconductor peninsula 220 Connection between semiconductor island and semiconductor peninsula 0 gate electrode 70 source electrode 80 drain electrode 90 interlayer insulating film 87 contact hole

Claims (14)

基板上に半導体膜を形成し更に加工して半導体島とする半導体島形成工程と、前記半導体島の表面に絶縁性被覆膜を形成する被覆膜形成工程と、前記半導体島をレーザー照射によって結晶化させる結晶化工程と、前記半導体島から半導体トランジスタを作成する装置形成工程と、を含むことを特徴とする半導体トランジスタ製造方法A semiconductor island forming step of forming a semiconductor film on a substrate and further processing to form a semiconductor island, a coating film forming step of forming an insulating coating film on the surface of the semiconductor island, and laser irradiating the semiconductor island A method for manufacturing a semiconductor transistor, comprising: a crystallization step of crystallizing; and a device forming step of forming a semiconductor transistor from the semiconductor island. 前記装置形成工程において、前記絶縁性被覆膜のすくなくとも一部を半導体トランジスタのゲート絶縁膜として使うことを特徴とする請求項1記載の半導体トランジスタ製造方法2. The method according to claim 1, wherein at least a part of the insulating coating film is used as a gate insulating film of a semiconductor transistor in the device forming step. 前記被覆膜形成工程において前記絶縁性被覆膜とは吸収係数4000cm−1から20000cm−1の間の半透明膜を含むことを特徴とする請求項1記載または請求項2記載の半導体トランジスタ製造方法3. The semiconductor transistor according to claim 1, wherein the insulating coating film in the step of forming the coating film includes a translucent film having an absorption coefficient of 4000 cm −1 to 20,000 cm −1. 4. Method 前記被覆膜形成工程において前記絶縁性被覆膜とは酸化シリコン膜と、吸収係数4000cm−1から20000cm−1の間の半透明膜と、を含むことを特徴とする請求項1記載または請求項2記載または請求項3記載の半導体トランジスタ製造方法2. The insulating coating film in the coating film forming step, wherein the insulating coating film includes a silicon oxide film and a translucent film having an absorption coefficient of 4000 cm -1 to 20,000 cm -1. Item 4. The method for manufacturing a semiconductor transistor according to item 2 or 3. 前記半導体島形成工程とは、基板上に非晶質の半導体膜を形成する半導体膜形成工程と、前記半導体膜にフォトマスクを通したレーザを照射して結晶化させる相変換工程と、前記相変換工程で結晶化されなかった非晶質の半導体膜をエッチングして結晶化半導体膜のみを残す選択エッチング工程と、を含む請求項1、または請求項2、または請求項3、または請求項4記載の半導体トランジスタ製造方法The semiconductor island forming step includes: a semiconductor film forming step of forming an amorphous semiconductor film on a substrate; a phase conversion step of irradiating the semiconductor film with a laser through a photomask to crystallize the semiconductor film; 5. A selective etching step in which an amorphous semiconductor film that has not been crystallized in the conversion step is etched to leave only a crystallized semiconductor film. Semiconductor manufacturing method 前記半導体島形成工程とは、基板上に非晶質半導体膜を形成する半導体膜形成工程と、非晶質半導体膜を少なくとも酸素雰囲気に保った状態でフォトマスクに通した光を照射して前記非晶質半導体膜の表面をフォトマスクパターン通りに酸化する表面酸化工程と、表面が酸化されなかった非晶質半導体膜をエッチングする選択エッチング工程と、を含む請求項1、または請求項2、または請求項3、または請求項4記載の半導体トランジスタ製造方法。The semiconductor island forming step includes: a semiconductor film forming step of forming an amorphous semiconductor film on a substrate; and irradiating a light passed through a photomask with the amorphous semiconductor film kept at least in an oxygen atmosphere. 3. The method according to claim 1, further comprising: a surface oxidation step of oxidizing the surface of the amorphous semiconductor film according to the photomask pattern; and a selective etching step of etching the amorphous semiconductor film whose surface has not been oxidized. 5. The method for manufacturing a semiconductor transistor according to claim 3 or claim 4. 前記選択エッチング工程とは、摂氏1200度〜2600度にまで加熱されたタングステンフィラメントで水素分子を分解することにより発生された原子状水素を用いて露出している非晶質半導体膜を選択除去することを特徴とする請求項1、または請求項2、または請求項3、または請求項4、または請求項5、または請求項6記載の半導体トランジスタ製造方法The selective etching process is to selectively remove an exposed amorphous semiconductor film using atomic hydrogen generated by decomposing hydrogen molecules with a tungsten filament heated to 1200 to 2600 degrees Celsius. 7. The method of manufacturing a semiconductor transistor according to claim 1, wherein the semiconductor transistor is manufactured by using the method described in claim 1 or claim 2 or claim 3 or claim 4 or claim 5 or claim 6. すくなくとも前記半導体島形成工程から前記被覆膜形成工程までを、大気にさらすことなく連続実施することを特徴とする請求項1、または請求項2、または請求項3、または請求項4、または請求項5、または請求項6、または請求項7記載の半導体トランジスタ製造方法5. The method according to claim 1, wherein at least the steps from the step of forming a semiconductor island to the step of forming a coating film are continuously performed without exposure to the air. 8. The method for manufacturing a semiconductor transistor according to claim 5, 6, or 7, すくなくとも前記半導体島形成工程から前記被覆膜形成工程までを、大気にさらすことなく連続実施することを特徴とする請求項1、または請求項2、または請求項3、または請求項4、または請求項5、または請求項6、または請求項7記載の半導体トランジスタの製造装置5. The method according to claim 1, wherein at least the steps from the step of forming a semiconductor island to the step of forming a coating film are continuously performed without exposure to the air. An apparatus for manufacturing a semiconductor transistor according to claim 5, 6, or 7, 非晶質の半導体膜にフォトマスクを通したレーザを照射してフォトマスクパターン通りに結晶化させる相変換工程と、前記相変換工程で結晶化されなかった非晶質の半導体膜をエッチングして結晶化された半導体膜のみを残す選択エッチング工程と、を含むことを特徴とする半導体膜のパターニング方法。Irradiating the amorphous semiconductor film with a laser through a photomask to crystallize it according to the photomask pattern; and etching the amorphous semiconductor film that has not been crystallized in the phase conversion step. A method for patterning a semiconductor film, comprising: a selective etching step for leaving only a crystallized semiconductor film. 非晶質半導体膜を少なくとも酸素雰囲気に保った状態でフォトマスクに通した光を照射して前記非晶質半導体膜の表面をフォトマスクパターン通りに酸化する酸化工程と、表面が酸化されなかった非晶質半導体膜をエッチングする選択エッチング工程と、を含むことを特徴とする半導体膜のパターニング方法。An oxidizing step of irradiating light through a photomask with the amorphous semiconductor film kept at least in an oxygen atmosphere to oxidize the surface of the amorphous semiconductor film according to the photomask pattern; and that the surface was not oxidized. A method of patterning a semiconductor film, comprising: a selective etching step of etching an amorphous semiconductor film. 前記気相エッチング工程とは、摂氏1200度〜2600度にまで加熱されたタングステンフィラメントで水素分子を分解することにより発生された原子状水素で非晶質半導体膜を選択エッチングすることを特徴とする請求項10および請求項11記載の半導体膜のパターニング方法The vapor-phase etching process is characterized in that the amorphous semiconductor film is selectively etched with atomic hydrogen generated by decomposing hydrogen molecules with a tungsten filament heated to 1200 to 2600 degrees Celsius. A method for patterning a semiconductor film according to claim 10 or claim 11. 請求項1〜12記載の前記半導体膜とはシリコン膜、またはゲルマニュウム膜、またはシリコンとゲルマニュウム化合物であることを特徴とするものである13. The semiconductor film according to claim 1, wherein the semiconductor film is a silicon film, a germanium film, or a silicon and germanium compound. 前記絶縁性被覆膜とは酸化シリコン膜または窒化シリコン膜または酸窒化シリコン膜であることを特徴とする請求項1または請求項2または請求項3記載の半導体トランジスタ製造方法4. The method according to claim 1, wherein the insulating coating film is a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.
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JP2005317851A (en) * 2004-04-30 2005-11-10 Toshiba Matsushita Display Technology Co Ltd Thin film transistor and its manufacturing method
JP2006100809A (en) * 2004-08-31 2006-04-13 Semiconductor Energy Lab Co Ltd Semiconductor device manufacturing method
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