JP4754918B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a liquid crystal display device having an inverted staggered thin film transistor formed of a crystalline semiconductor film.

  In recent years, a flat panel display (FPD) typified by a liquid crystal display (LCD) or an EL display has attracted attention as a display device that replaces a conventional CRT. In particular, the development of large-screen liquid crystal televisions equipped with large liquid crystal panels driven by an active matrix has become an important issue for LCD panel manufacturers to focus on. In recent years, a large screen EL television has been developed following the liquid crystal television.

  In a conventional liquid crystal device, a thin film transistor (hereinafter referred to as TFT) using amorphous silicon is used as a semiconductor element for driving each pixel.

On the other hand, in the conventional liquid crystal television, the blur of the image due to the limitation of the viewing angle characteristic and the limitation of the high-speed operation due to the liquid crystal material and the like was a drawback. It has been proposed (Non-Patent Document 1).
Nagahiro Yasuaki et al., “Nikkei Microdevices separate volume flat panel display 2002”, Nikkei BP, October 2001, P102-109

  On the other hand, there is a need for a switching element that can operate at high speed in order to improve the image quality of the LCD. However, a TFT using an amorphous semiconductor film has a limit. For example, it is difficult to realize an OCB mode liquid crystal display device.

  Also, in the process of forming an inverted staggered TFT using a conventional photolithography process, a resist is applied on a film formed on the entire surface of the substrate by CVD, PVD, or the like, exposed and developed, and wiring or A semiconductor region was formed. However, in this case, most of the materials such as films and resists formed on the entire surface of the substrate by the CVD method, the PVD method, and the like are wasted, and the number of steps for forming wirings and semiconductor regions is large, and the throughput is increased. There is a problem that decreases.

  In addition, it is difficult for an exposure apparatus used in the photolithography process to perform exposure processing on a large area substrate at a time. For this reason, in a method for manufacturing a display device using a large-area substrate, a plurality of exposure times are required. For this reason, there is a problem that inconsistency between adjacent patterns occurs, and the yield decreases. This problem is significant for large liquid crystal display devices represented by large televisions.

  The present invention has been made in view of such a situation, and provides a method for manufacturing a semiconductor device having an inverted staggered TFT that is unlikely to cause a threshold shift and can operate at high speed. In addition, a method for manufacturing a liquid crystal display device which can display with high switching characteristics and high contrast is provided. Furthermore, a manufacturing method of a semiconductor device and a liquid crystal display device which can reduce cost with a small amount of raw material and has a high yield is provided.

  The present invention includes an amorphous semiconductor film, a layer having a catalytic element that promotes crystallization of the amorphous semiconductor film, and a donor-type element or a rare gas element after the gate electrode is formed using a material having high heat resistance. A layer is formed and heated to crystallize the amorphous semiconductor film and remove the catalytic element from the crystalline semiconductor film, and then form a semiconductor region using a part of the crystalline semiconductor film. The gist is to form an inverted staggered TFT by forming a source electrode and a drain electrode that are in electrical contact with each other and forming a gate wiring connected to the gate electrode.

  According to one aspect of the present invention, a gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a layer having a catalytic element is formed on the gate insulating film, and the layer having the catalytic element is formed Forming a first semiconductor region on the first semiconductor region, forming a second semiconductor region having an impurity element on the first semiconductor region, and then heating the first conductive layer in contact with the heated second semiconductor region. Is formed by a droplet discharge method, and a part of the first conductive layer and the second semiconductor region is etched to form a source electrode and a drain electrode, and a source region and a drain region, and the gate insulating film And forming an insulating film on the source electrode and the drain electrode, etching a part of the insulating film and the gate insulating film to expose a part of the gate electrode, and then connecting to the gate electrode Forming a first electrode connected to the source electrode or the drain electrode after forming a part of the insulating film by etching a part of the insulating film to expose a part of the source electrode or the drain electrode; This is a method for manufacturing a liquid crystal display device.

  According to one aspect of the present invention, a gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a layer having a catalytic element is formed on the gate insulating film, and the layer having the catalytic element is formed Forming a first semiconductor region on the first semiconductor region, forming a second semiconductor region having an impurity element on the first semiconductor region, and then heating the first conductive layer in contact with the heated second semiconductor region. Is formed by a droplet discharge method, and a part of the first conductive layer and the second semiconductor region is etched to form a source electrode and a drain electrode, and a source region and a drain region. An insulating film covering at least a part of one of the drain electrodes is formed by a droplet discharge method, and a part of the gate insulating film is etched to expose a part of the gate electrode, and then the source electrode or the drain electrode is exposed. A gate wiring connected to the gate electrode is formed on the insulating film covering at least a part of the gate electrode and the gate insulating film by a droplet discharge method, and a first electrode in contact with the other of the source electrode or the drain electrode is formed It is a manufacturing method of a liquid crystal display device.

  According to one aspect of the present invention, a gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a layer having a catalytic element is formed on the gate insulating film, and the layer having the catalytic element is formed Forming a first semiconductor region on the first semiconductor region, forming a second semiconductor region having an impurity element on the first semiconductor region, and then heating the first conductive layer in contact with the heated second semiconductor region. Is formed by a droplet discharge method, and a part of the first conductive layer and the second semiconductor region is etched to form a source electrode and a drain electrode, and a source region and a drain region. An insulating film covering at least a part of one of the drain electrodes is formed by a droplet discharge method, and a part of the gate insulating film is etched to expose a part of the gate electrode, and then the source electrode or the drain electrode is exposed. A gate wiring connected to the gate electrode is formed on the insulating film covering at least one of the gate electrode and the gate insulating film by a droplet discharge method, and a first electrode in contact with the other of the source electrode or the drain electrode is formed This is a method for manufacturing a liquid crystal display device.

  According to one aspect of the present invention, a gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a first semiconductor region is formed on the gate insulating film, and the first semiconductor region is formed on the gate insulating film. Forming a layer having a catalytic element on the first conductive layer, forming a second semiconductor region having an impurity element on the layer having the catalytic element, and then heating the first conductive layer in contact with the heated second semiconductor region Is formed by a droplet discharge method, and a part of the first conductive layer and the second semiconductor region is etched to form a source electrode and a drain electrode, and a source region and a drain region. An insulating film covering at least a part of one of the drain electrodes is formed by a droplet discharge method, and a part of the gate insulating film is etched to expose a part of the gate electrode, and then the source electrode or the drain electrode is exposed. A gate wiring connected to the gate electrode is formed on the insulating film covering at least a part of the gate electrode and the gate insulating film by a droplet discharge method, and a first electrode in contact with the other of the source electrode or the drain electrode is formed It is a manufacturing method of a liquid crystal display device.

  According to one aspect of the present invention, a gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a layer having a catalytic element is formed on the gate insulating film, and the layer having the catalytic element is formed Forming a first semiconductor region, forming a protective layer over the gate electrode, the layer having the catalytic element, and a region where the first semiconductor region overlaps, and the first semiconductor region and the protective layer A second semiconductor region having an impurity element is formed thereon and then heated, and a first conductive layer in contact with the heated second semiconductor region is formed by a droplet discharge method, and the first conductive layer and Etching a part of the second semiconductor region to form a source electrode and a drain electrode, and a source region and a drain region, forming an insulating film on the gate insulating film and the source electrode and the drain electrode, Insulation film And etching a part of the gate insulating film to expose a part of the gate electrode, then forming a gate wiring connected to the gate electrode by a droplet discharge method, and etching a part of the insulating film. Then, after a part of the source or drain electrode is exposed, a first electrode connected to the source or drain electrode is formed.

  According to one aspect of the present invention, a gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a layer having a catalytic element is formed on the gate insulating film, and the layer having the catalytic element is formed Forming a first semiconductor region, forming a protective layer on the gate electrode, the layer having the catalytic element, and a region where the first semiconductor region overlaps, and forming impurities on the semiconductor region and the protective layer After forming the second semiconductor region containing an element, heating is performed, and a first conductive layer in contact with the heated second semiconductor region is formed by a droplet discharge method, and the first conductive layer and the second conductive layer are formed. A part of the semiconductor region is etched to form a source electrode and a drain electrode, and a source region and a drain region, and an insulating film covering at least a part of one of the source electrode or the drain electrode is formed by a droplet discharge method And etching the part of the gate insulating film to expose a part of the gate electrode, and then covering the gate electrode on the insulating film covering at least a part of the source electrode or the drain electrode and the gate insulating film. A method for manufacturing a liquid crystal display device is characterized in that a gate wiring connected to an electrode is formed by a droplet discharge method, and a first electrode in contact with the other of the source electrode and the drain electrode is formed.

  According to one aspect of the present invention, a gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a first semiconductor region is formed on the gate insulating film, and the first semiconductor region is formed on the gate insulating film. A layer having a catalytic element is formed, and a protective layer is formed on a region where the gate electrode, the first semiconductor region, and the layer having the catalytic element overlap, and the protective layer and the layer having the catalytic element A second semiconductor region having an impurity element is formed thereon and then heated, and a first conductive layer in contact with the heated second semiconductor region is formed by a droplet discharge method, and the first conductive layer and Etching a part of the second semiconductor region to form a source electrode and a drain electrode, and a source region and a drain region, forming an insulating film on the gate insulating film and the source electrode and the drain electrode, Insulation film And etching a part of the gate insulating film to expose a part of the gate electrode, then forming a gate wiring connected to the gate electrode by a droplet discharge method, and etching a part of the insulating film. Then, after a part of the source or drain electrode is exposed, a first electrode connected to the source or drain electrode is formed.

  According to one aspect of the present invention, a gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a first semiconductor region is formed on the gate insulating film, and the first semiconductor region is formed on the gate insulating film. A layer having a catalytic element is formed, and a protective layer is formed on a region where the gate electrode, the first semiconductor region, and the layer having the catalytic element overlap, and the protective layer and the layer having the catalytic element A second semiconductor region having an impurity element is formed thereon and then heated, and a first conductive layer in contact with the heated second semiconductor region is formed by a droplet discharge method, and the first conductive layer and A portion of the second semiconductor region is etched to form a source electrode and a drain electrode, and a source region and a drain region, and an insulating film covering at least a portion of one of the source electrode or the drain electrode is discharged as a droplet. By law After forming and etching a part of the gate insulating film to expose a part of the gate electrode, on the insulating film covering at least a part of one of the source electrode or the drain electrode and the gate insulating film, In the method for manufacturing a liquid crystal display device, a gate wiring connected to the gate electrode is formed by a droplet discharge method, and a first electrode in contact with the other of the source electrode or the drain electrode is formed.

  According to one aspect of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a layer including a catalytic element is formed over the gate insulating film, and the layer including the catalytic element is formed A first semiconductor region is formed, a second semiconductor region having an impurity element is formed on the first semiconductor region, and then heated, and the heated second semiconductor region is etched to form a source region and a drain Forming a region, etching a part of the gate insulating film to expose a part of the gate electrode, then connecting a gate wiring to the gate electrode, and a source electrode and a drain in contact with the source region and the drain region An electrode is formed by a droplet discharge method, an insulating film is formed on the gate insulating film, the gate wiring, the source electrode, and the drain electrode, and a part of the insulating film is etched to form the gate. After exposing a part of the gate wiring, a conductive layer connected to the gate wiring is formed by a droplet discharge method, and after etching a part of the insulating film to expose a part of the source electrode or drain electrode A method for manufacturing a liquid crystal display device is characterized in that a first electrode in contact with the source electrode or the drain electrode is formed.

  According to one aspect of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a layer including a catalytic element is formed over the gate insulating film, and the layer including the catalytic element is formed A first semiconductor region is formed, a second semiconductor region having an impurity element is formed on the first semiconductor region, and then heated, and the heated second semiconductor region is etched to form a source region and a drain Forming a region, etching a part of the gate insulating film to expose a part of the gate electrode, then connecting a gate wiring to the gate electrode, and a source electrode and a drain in contact with the source region and the drain region Forming an insulating film covering at least a part of one of the source electrode or the drain electrode, and forming at least one of the source electrode or the drain electrode. A conductive layer connected to the gate wiring is formed over the insulating film covering a part and the gate electrode by a droplet discharge method, and a first electrode in contact with the other of the source electrode or the drain electrode is formed. This is a method for manufacturing a liquid crystal display device.

  In one embodiment of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region is formed over the gate insulating film, and the first semiconductor region is formed over the first semiconductor region. A layer having a catalytic element is formed, a second semiconductor region having an impurity element is formed on the layer having the catalytic element, and then heated, and the heated second semiconductor region is etched to form a source region and a drain Forming a region, etching a part of the gate insulating film to expose a part of the gate electrode, then connecting a gate wiring to the gate electrode, and a source electrode and a drain in contact with the source region and the drain region An electrode is formed by a droplet discharge method, an insulating film is formed on the gate insulating film, the gate wiring, the source electrode, and the drain electrode, and a part of the insulating film is etched to form the gate. After exposing a part of the gate wiring, a conductive layer connected to the gate wiring is formed by a droplet discharge method, and after etching a part of the insulating film to expose a part of the source electrode or drain electrode A method for manufacturing a liquid crystal display device is characterized in that a first electrode in contact with the source electrode or the drain electrode is formed.

  In one embodiment of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region is formed over the gate insulating film, and the first semiconductor region is formed over the first semiconductor region. A layer having a catalytic element is formed, a second semiconductor region having an impurity element is formed on the layer having the catalytic element, and then heated, and the heated second semiconductor region is etched to form a source region and a drain Forming a region, etching a part of the gate insulating film to expose a part of the gate electrode, then connecting a gate wiring to the gate electrode, and a source electrode and a drain in contact with the source region and the drain region Forming an insulating film covering at least a part of one of the source electrode or the drain electrode, and forming at least one of the source electrode or the drain electrode. A conductive layer connected to the gate wiring is formed over the insulating film covering a part and the gate electrode by a droplet discharge method, and a first electrode in contact with the other of the source electrode or the drain electrode is formed. This is a method for manufacturing a liquid crystal display device.

  According to one aspect of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a layer including a catalytic element is formed over the gate insulating film, and the layer including the catalytic element is formed A first semiconductor region is formed, a protective layer is formed on a region where the gate electrode, the layer having the catalytic element, and the first semiconductor region overlap, and the first semiconductor region and the protective layer are formed. A second semiconductor region having an impurity element is formed and then heated; the heated second semiconductor region is etched to form a source region and a drain region; and a part of the gate insulating film is etched. Then, after exposing a part of the gate electrode, a gate wiring connected to the gate electrode and a source electrode and a drain electrode in contact with the source region and the drain region are formed by a droplet discharge method, and the gate is formed. An insulating film is formed on the insulating film, the gate wiring, the source electrode and the drain electrode, and a part of the insulating film is etched to expose a part of the gate wiring, and then a conductive layer connected to the gate wiring Forming a first electrode in contact with the source or drain electrode after etching a part of the insulating film to expose a part of the source or drain electrode. This is a method for manufacturing a liquid crystal display device.

  According to one aspect of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a layer including a catalytic element is formed over the gate insulating film, and the layer including the catalytic element is formed A first semiconductor region is formed, a protective layer is formed on a region where the gate electrode, the layer having the catalytic element, and the first semiconductor region overlap, and the first semiconductor region and the protective layer are formed. A second semiconductor region having an impurity element is formed and then heated; the heated second semiconductor region is etched to form a source region and a drain region; and a part of the gate insulating film is etched. After exposing a part of the gate electrode, a gate wiring connected to the gate electrode, and a source electrode and a drain electrode in contact with the source region and the drain region are formed by a droplet discharge method. Forming an insulating film covering at least a part of one of the electrode and the drain electrode, and forming an insulating film covering at least a part of the one of the source electrode and the drain electrode and a conductive layer connected to the gate wiring on the gate electrode A liquid crystal display device manufacturing method is characterized in that a first electrode is formed by a droplet discharge method and is in contact with the other of the source electrode and the drain electrode.

  In one embodiment of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region is formed over the gate insulating film, and the first semiconductor region is formed over the first semiconductor region. A layer having a catalytic element is formed, a protective layer is formed on a region where the gate electrode, the first semiconductor region, and the layer having the catalytic element overlap, and the protective layer and the layer having the catalytic element are formed. A second semiconductor region having an impurity element is formed and then heated; the heated second semiconductor region is etched to form a source region and a drain region; and a part of the gate insulating film is etched. Then, after exposing a part of the gate electrode, a gate wiring connected to the gate electrode and a source electrode and a drain electrode in contact with the source region and the drain region are formed by a droplet discharge method, and the gate is formed. An insulating film is formed on the insulating film, the gate wiring, the source electrode and the drain electrode, and a part of the insulating film is etched to expose a part of the gate wiring, and then a conductive layer connected to the gate wiring Forming a first electrode in contact with the source or drain electrode after etching a part of the insulating film to expose a part of the source or drain electrode. This is a method for manufacturing a liquid crystal display device.

  In one embodiment of the present invention, a gate electrode is formed over a substrate, a gate insulating film is formed over the gate electrode, a first semiconductor region is formed over the gate insulating film, and the first semiconductor region is formed over the first semiconductor region. A layer having a catalytic element is formed, a protective layer is formed on a region where the gate electrode, the first semiconductor region, and the layer having the catalytic element overlap, and the protective layer and the layer having the catalytic element are formed. A second semiconductor region having an impurity element is formed and then heated; the heated second semiconductor region is etched to form a source region and a drain region; and a part of the gate insulating film is etched. After exposing a part of the gate electrode, a gate wiring connected to the gate electrode, and a source electrode and a drain electrode in contact with the source region and the drain region are formed by a droplet discharge method. Forming an insulating film covering at least a part of one of the electrode and the drain electrode, and forming an insulating film covering at least a part of the one of the source electrode and the drain electrode and a conductive layer connected to the gate wiring on the gate electrode A liquid crystal display device manufacturing method is characterized in that a first electrode is formed by a droplet discharge method and is in contact with the other of the source electrode and the drain electrode.

  Note that instead of the insulating film formed over the gate insulating film, the gate wiring, the source electrode, and the drain electrode, an insulating film that covers part of the source electrode or the drain electrode may be formed.

  As catalyst elements, tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), It can be formed using one or more of titanium (Ti), copper (Cu), nickel (Ni), platinum (Pt) and the like.

  Further, after forming the first electrode in contact with the source electrode or the drain electrode, a gate wiring connected to the gate electrode may be formed. In addition, after the gate wiring connected to the gate electrode is formed, the first electrode in contact with the source electrode or the drain electrode may be formed.

  Further, the gate wiring is connected to three or more gate electrodes. In this case, the gate wiring is preferably made of a low resistance material. On the other hand, the gate wiring may be connected to two gate electrodes. In this case, the material of the gate wiring is not particularly limited.

  The gate electrode is formed by forming a conductive film over an insulating surface, discharging or applying a photosensitive resin over the conductive film, irradiating a part of the photosensitive resin with laser light to form a mask, and then applying the mask. It may be formed by etching the conductive film.

  The gate electrode is formed of a heat-resistant conductive layer, and typically includes tungsten, molybdenum, zirconium, hafnium, vanadium, niobium, tantalum, chromium (Cr), cobalt, nickel, platinum, and phosphorus. It is formed of a crystalline silicon film, indium tin oxide, zinc oxide, indium zinc oxide, zinc oxide to which gallium is added, or indium tin oxide containing silicon oxide.

  The impurity element is an element selected from phosphorus, arsenic, antimony, and bismuth.

  In the above structure, the first electrode can be used as a pixel electrode.

  Note that a layer including a silicon nitride film may be formed as the gate insulating film. Further, after the silicon nitride film is formed, the layer having the catalytic element or the first semiconductor region may be formed so as to be in contact with the silicon nitride film.

  Another embodiment of the present invention is a liquid crystal television device including the above semiconductor device.

  In the present invention, examples of the semiconductor device include an integrated circuit including a semiconductor element, a display device, a wireless chip, an IC tag, and a display device. As a display device, typically, a liquid crystal display device, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Display), electrophoretic display Examples thereof include display devices such as devices (electronic paper).

  In the present invention, the liquid crystal display device refers to a device using a liquid crystal display element, that is, an image display device. In addition, a connector in which a connector such as a flexible printed circuit (FPC), a TAB (Tape Automated Bonding) tape or a TCP (Tape Carrier Package) is attached to the liquid crystal display panel, a printed wiring board at the end of the TAB tape or TCP The display device also includes a module in which an IC (integrated circuit) or a CPU is directly mounted on a display element or a display element by a COG (Chip On Glass) method.

  According to the present invention, an inverted staggered TFT formed of a crystalline semiconductor film can be formed. The inversely staggered TFT of the present invention can simultaneously perform a crystallization process of an amorphous semiconductor film and a gettering process of a catalytic element for promoting crystallization of the amorphous semiconductor film. Since the number can be reduced, the throughput can be improved. In addition, since the number of heat treatments can be reduced, energy saving can be achieved.

  The inverted staggered TFT of the present invention uses a material having high heat resistance for the gate electrode, and uses a low resistance material after heat treatment such as an activation process, a gettering process, and a crystallization process. Wiring such as signal lines and scanning lines is formed. Therefore, a TFT having crystallinity, a small amount of impurity metal elements, and low wiring resistance can be formed. In the liquid crystal display device of the present invention, a pixel electrode can be formed over the insulating film, and the aperture ratio can be increased.

  For this reason, since it is formed of a crystalline semiconductor film, the mobility is several tens to 50 times higher than that of an inverted staggered TFT formed of an amorphous semiconductor film. In addition, the source region and the drain region include a catalyst element in addition to the acceptor element or the donor element. For this reason, a source region and a drain region having low contact resistance with the semiconductor region can be formed. As a result, a semiconductor device that requires high-speed operation can be manufactured. Typically, it is possible to manufacture a liquid crystal display device that can display with a high response speed and a high viewing angle as in the OCB mode.

  In addition, a scanning line driver circuit can be formed at the periphery of the liquid crystal display device at the same time as the TFT in the pixel region. Therefore, a miniaturized liquid crystal display device can be manufactured.

  Furthermore, since the gettering process also getters the metal element mixed in the semiconductor film at the film formation stage, it is possible to reduce the off-current, and typically has an ON / OFF ratio of 6 digits or more. It is possible to form a TFT having By providing such a TFT in a switching element of a liquid crystal display device, contrast can be improved.

  In the present invention, therefore, a thin film material or a resist may be discharged to a predetermined place using a droplet discharge method without forming a thin film on the entire surface of the substrate, and a TFT can be formed without using a photomask. Can be formed. For this reason, it is possible to improve throughput and yield and to reduce costs.

  Furthermore, a semiconductor device or a liquid crystal television having a liquid crystal display device formed by the above manufacturing process can be manufactured at low cost because throughput and yield can be improved.

  The best mode for carrying out the invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the embodiment modes. In the drawings, common portions are denoted by the same reference numerals, and detailed description thereof is omitted.

(Embodiment 1)
In this embodiment mode, a manufacturing process of an inverted staggered TFT having a crystalline semiconductor film will be described with reference to FIGS.

  As shown in FIG. 1A, a first conductive layer 102 is formed over a substrate 101, photosensitive materials 103 and 104 are applied or discharged over the first conductive layer, and then dried and fired. Next, the photosensitive materials 103 and 104 are irradiated with laser beams 105 and 106 to form first masks 111 and 112 as shown in FIG.

  As the substrate 101, a glass substrate, a quartz substrate, a substrate formed of an insulating material such as ceramic such as alumina, a silicon wafer, a metal plate, or the like can be used. Further, as the substrate 101, a large area substrate such as 320 mm × 400 mm, 370 mm × 470 mm, 550 mm × 650 mm, 600 mm × 720 mm, 680 mm × 880 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, 1150 mm × 1300 mm can be used.

  The first conductive layer 102 is formed in a predetermined region by a droplet discharge method having a thickness of 500 to 1000 nm, a printing method, an electroless plating method, or the like. Alternatively, it may be formed on the entire surface of the substrate by a PVD method (Physical Vapor Deposition), a CVD method (Chemical Vapor Deposition), a vapor deposition method, or the like. Note that here, by using a droplet discharge method or a printing method, since a predetermined region is formed, there are few regions to be removed in a later etching step, and the raw materials can be reduced.

  The first conductive layer 102 is preferably formed using a high melting point material. By using the high melting point material, a heating process such as a subsequent crystallization process, gettering process, activation process or the like can be performed. High melting point materials include tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co) A metal such as nickel (Ni), titanium (Ti), platinum (Pt), an alloy thereof, or a metal nitride thereof can be used as appropriate. Further, a plurality of these layers may be stacked. Typically, a tantalum nitride film and a tungsten film formed thereon, a tantalum nitride film, a molybdenum film formed thereon, a titanium nitride film, a tungsten film formed thereon, and titanium nitride from the substrate surface side A laminated structure such as a film and a molybdenum film formed thereon may be used. In addition, a silicon film containing phosphorus (including an amorphous semiconductor film and a crystalline semiconductor film), indium tin oxide, zinc oxide, indium zinc oxide, zinc oxide added with gallium, or indium tin oxide containing silicon oxide is used. It can also be used.

  As the material of the photosensitive materials 103 and 104, a negative photosensitive material or a positive photosensitive material that is sensitive from ultraviolet light to infrared light is used. As a representative example of the photosensitive material, a resin material exhibiting photosensitivity such as an epoxy resin, a cryl resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin is used. In addition, organic materials exhibiting photosensitivity such as benzocyclobutene, parylene, flare, and polyimide can be used. Moreover, as a typical positive type photosensitive resin, there can be mentioned a novolak resin and a photosensitive resin having a naphthoquinonediazide compound as a photosensitive agent, and as a negative type photosensitive resin, a base resin, diphenylsilanediol, an acid generator and the like can be mentioned. The photosensitive resin which has. Here, a negative photosensitive material is used.

  Next, the photosensitive materials 103 and 104 are irradiated with laser beams 105 and 106 using a laser beam direct drawing apparatus.

  A laser beam drawing apparatus will be described with reference to FIG. As shown in FIG. 39, a laser beam drawing apparatus 1001 includes a personal computer (hereinafter referred to as a PC) 1002 that executes various controls when irradiating a laser beam, a laser oscillator 1003 that outputs a laser beam, and a laser. A power source 1004 of the oscillator 1003, an optical system (ND filter) 1005 for attenuating the laser beam, an acousto-optic modulator (AOM) 1006 for modulating the intensity of the laser beam, and an enlargement or reduction of the cross section of the laser beam An optical system 1007 composed of a lens for changing the optical path, a mirror for changing the optical path, etc., a substrate moving mechanism 1009 having an X stage and a Y stage, and D / Acoustic light according to the analog voltage output from the A converter 1010 and the D / A converter A driver 1011 for controlling the modulator 1006, and a driver 1012 for outputting a driving signal for driving the substrate moving mechanism 1009.

As the laser oscillator 1003, a laser oscillator that can oscillate ultraviolet light, visible light, or infrared light can be used. As the laser oscillator, excimer laser oscillators such as KrF, ArF, KrF, XeCl, and Xe, gas laser oscillators such as He, He-Cd, Ar, He-Ne, and HF, YAG, GdVO ₄ , YVO ₄ , YLF, and YAlO Cr crystal such as _{3, Nd, Er, Ho,} Ce, Co, solid-state laser oscillator using a crystal doped with Ti or Tm, can be used GaN, GaAs, GaAlAs, a semiconductor laser oscillator of InGaAsP or the like. In the solid-state laser oscillator, it is preferable to apply the first to fifth harmonics of the fundamental wave.

  Next, a method for exposing a photosensitive material using a laser beam direct drawing apparatus will be described. When the substrate 1008 is mounted on the substrate moving mechanism 1009, the PC 1002 detects the position of the marker attached to the substrate by a camera (not shown). Next, the PC 1002 generates movement data for moving the substrate movement mechanism 1009 based on the detected marker position data and drawing pattern data input in advance. Thereafter, the PC 1002 controls the output light amount of the acousto-optic modulator 1006 via the driver 1011, whereby the laser beam output from the laser oscillator 1003 is attenuated by the optical system 1005, and then the acousto-optic modulator 1006. The light amount is controlled so as to be a predetermined light amount. On the other hand, the laser beam output from the acousto-optic modulator 1006 is changed in optical path and beam shape by the optical system 1007, condensed by the lens, and then irradiated to the photosensitive material applied on the substrate. Photosensitive material is exposed. At this time, according to the movement data generated by the PC 1002, the movement of the substrate moving mechanism 1009 is controlled in the X direction and the Y direction. As a result, the laser beam is irradiated to a predetermined place, and the photosensitive material is exposed.

  As a result, as shown in FIG. 1B, first masks 111 and 112 are formed in the region irradiated with the laser beam. Here, since the negative type is used as the photosensitive material, the region irradiated with the laser beam serves as a resist mask. A part of the energy of the laser beam is converted into heat by the resist and reacts a part of the resist, so that the width of the resist mask is slightly larger than the width of the laser beam. In addition, the shorter the laser beam, the shorter the beam diameter can be focused. Therefore, it is preferable to irradiate the laser beam with a short wavelength in order to form a resist mask with a fine width.

  Further, the spot shape of the laser beam on the surface of the photosensitive material is processed by an optical system so as to be a dot shape, a circle shape, an ellipse shape, a rectangle shape, or a line shape (strictly, an elongated rectangle shape). Note that the spot shape may be circular, but a linear resist mask having a uniform width can be formed.

  The apparatus shown in FIG. 39 shows an example in which exposure is performed by irradiating a laser beam from the front side of the substrate. However, the optical system and the substrate moving mechanism are appropriately changed, and the laser beam is irradiated from the back side of the substrate. Alternatively, a laser beam drawing apparatus that performs exposure may be used.

  Note that here, the laser beam is selectively irradiated by moving the substrate; however, the present invention is not limited to this, and the laser beam can be irradiated by scanning the laser beam in the X and Y axis directions. In this case, it is preferable to use a polygon mirror or a galvanometer mirror for the optical system 1007.

  Next, as illustrated in FIG. 1C, the first conductive layer 102 is etched using the first mask to form second conductive layers 121a and 121b. The second conductive layer 121a functions as a gate electrode, and the second conductive layer 121b is a region connected to a gate wiring in the gate electrode (hereinafter referred to as a gate electrode connection portion). Note that in FIG. 1C, the second conductive layers 121a and 121b are displayed in a separated state, but in actuality, as shown in FIG. 3C, in the same connected region. is there.

  Next, after removing the first mask, a first insulating film is formed. Here, an insulating film 123a having a thickness of 50 to 100 nm, an insulating film 123b having a thickness of 50 to 100 nm, and an insulating film 123c having a thickness of 0.3 to 5 nm are stacked as the first insulating film. After that, a layer 125 having a catalytic element is formed over the first insulating film.

  The first insulating films 123a, 123b, and 123c function as gate insulating films. As the insulating films 123a and 123b, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like can be used as appropriate. Further, the second conductive layers 121a and 121b may be anodized to form an anodized film instead of the insulating films 123a and 123b. Note that in order to prevent diffusion of impurities and the like from the substrate side, the insulating film 123a in contact with the substrate side is preferably formed using silicon nitride (SiNx), silicon nitride oxide (SiNxOy) (x> y), or the like. . Further, in order to reduce the influence of the device characteristics due to the insulating properties and defects in the film, the insulating film 123b may be formed using silicon oxide (SiOx), silicon oxynitride (SiOxNy) (x> y), or the like. desirable. However, the structure is not limited, and any of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), and the like is used as appropriate. A laminated structure may be combined. Note that the silicon oxide (SiOx) film contains hydrogen.

  As the insulating film 123c in contact with the semiconductor film, a silicon nitride film or a silicon nitride oxide film with a thickness of 0.3 nm to 5 nm is preferably formed. In this embodiment mode, a metal element that promotes crystallization (nickel is used in this embodiment mode) is added to the semiconductor film, and then gettering treatment is performed for removal. Although the interface state between the silicon oxide film and the silicon film is good, a metal element in the silicon film reacts with oxygen in the silicon oxide at the interface to react with a metal oxide (in this embodiment, nickel oxide (NiOx)). In some cases, the metal element is difficult to getter. Further, the silicon nitride film may adversely affect the interface state with the semiconductor film due to the stress of the silicon nitride film and the influence of traps. Therefore, a silicon nitride film or a silicon nitride oxide film with a thickness of 0.3 to 5 nm is formed as the uppermost layer of the insulating layer in contact with the semiconductor film. In this embodiment, after a silicon nitride oxide film as the insulating film 123a and a silicon oxynitride film as the insulating film 123b are stacked over the substrate 101 and the second conductive layers 121a and 121b, the film thickness is formed over the silicon oxynitride film. A silicon nitride oxide film is formed as the insulating film 123c having a thickness of 0.1 nm to 10 nm, preferably 1 to 3 nm, so that a three-layer structure is formed. With such a structure, the gettering efficiency of the metal element in the semiconductor film is increased, and the adverse effect of the silicon nitride film on the semiconductor film can be reduced. The insulating layers to be stacked are preferably formed continuously at the same temperature without breaking the vacuum in the same chamber while switching the reaction gas. If formed continuously without breaking the vacuum, it is possible to prevent the interface between the stacked films from being contaminated.

  As a method for forming the layer 125 having a catalytic element, a method of forming a thin film of a catalytic element or a silicide of a catalytic element on the surface of the first insulating film by a PVD method, a CVD method, a vapor deposition method, or the like, There is a method of applying a solution containing a catalytic element on the surface. Catalyst elements include tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), It can be formed using one or more of copper (Cu), titanium (Ti), nickel (Ni), platinum (Pt) and the like. Further, the surface of the semiconductor film may be subjected to plasma treatment using an electrode formed of the above catalytic element. Here, a solution containing 1 to 200 ppm and 10 to 150 ppm of nickel is applied. Here, the catalytic element is an element that promotes or promotes crystallization of the semiconductor film.

  Next, as illustrated in FIG. 1D, a first semiconductor film 124 with a thickness of 50 to 250 nm is formed over the layer 125 having a catalytic element, and a donor-type element is included over the first semiconductor film 124. A second semiconductor film 132 with a thickness of 80 to 250 nm is formed.

  As the first semiconductor film 124, an amorphous semiconductor, a semi-amorphous semiconductor in which an amorphous state and a crystalline state are mixed (also referred to as SAS), and crystal grains of 0.5 nm to 20 nm are formed in the amorphous semiconductor. A film having any state selected from a microcrystalline semiconductor and a crystalline semiconductor that can be observed is formed. In particular, a microcrystalline state in which grains of 0.5 nm to 20 nm can be observed is called a so-called microcrystal (μc). In any case, a semiconductor film can be used for the film thickness mainly composed of silicon, silicon germanium (SiGe), or the like.

Note that in order to obtain a semiconductor film having a high-quality crystal structure by subsequent crystallization, the impurity concentration of oxygen, nitrogen, or the like contained in the first semiconductor film 124 is set to 5 × 10 ¹⁸ / cm ³ (hereinafter referred to as “the semiconductor film”). All concentrations are shown as atomic concentrations measured by secondary ion mass spectrometry (SIMS). These impurities are likely to react with the catalytic element, hinder subsequent crystallization, and increase the density of capture centers and recombination centers even after crystallization.

The second semiconductor film 132 is formed by a plasma CVD method in which a gas containing a donor element such as phosphorus or arsenic is added to a silicide gas. By forming the second semiconductor film by such a method, an interface between the first semiconductor film and the second semiconductor film is formed. In addition, the second semiconductor film 132 containing a donor-type element is formed by forming a semiconductor film similar to the first semiconductor film and then adding the donor-type element by an ion doping method or an ion implantation method. Can do. At this time, the second semiconductor film 132 preferably has a phosphorus concentration of 1 × 10 ^{19 to} 3 × 10 ²¹ / cm ³ .

Further, a low concentration region (hereinafter referred to as an n ⁻ region) is formed on the side in contact with the first semiconductor film 124 using the plasma CVD method, ion doping method, or ion implantation method, and a high concentration is formed thereon. A stacked structure of regions (hereinafter referred to as n ⁺ regions) may be employed. At this time, n ^- concentration of donor element ^{region, 1 × 10 17 ~3 × 10} 19 / cm 3, preferably between ^{1 × 10 18 ~1 × 10 19} / cm 3, donor element in the n ⁺ region The concentration of is 10 to 100 times that of the donor element in the n ⁻ region. The film thickness of the n ⁻ region is 50 to 200 nm, and the film thickness of the n ⁺ region is 30 to 100 nm, preferably 40 to 60 nm. Here, as the second semiconductor film 132, a region on the first semiconductor film 124 side from the broken line is an n ⁻ region, and an n ⁺ region is shown on the surface thereof.

FIG. 19 shows the impurity profile of the second semiconductor film containing the donor element at this time. FIG. 19A shows a donor-type element profile 150a when the second semiconductor film 132a containing a donor-type element is formed over the first semiconductor film 124 by a plasma CVD method. Note that in the second semiconductor film 132a, a donor-type element having a constant concentration (first concentration) is distributed in the depth direction of the film from the surface to the interface between the n ⁺ region 144a and the n ⁻ region 144b. ing. In addition, a donor-type element having a constant concentration (second concentration) is distributed from the interface between the n ⁺ region 144a and the n ⁻ region 144b to the interface with the first semiconductor film 124 in the depth direction of the film. ing. At this time, the first concentration is higher than the second concentration.

On the other hand, in FIG. 19B, a semiconductor film having a state selected from an amorphous semiconductor, a SAS, a microcrystalline semiconductor, and a crystalline semiconductor is formed over the first semiconductor film 124. A donor-type element profile 150b is shown when a second semiconductor film 132b is formed by adding a donor-type element to the semiconductor film by ion doping or ion implantation. As shown in FIG. 19B, the donor-type element concentration is relatively high near the surface of the second semiconductor film. This region is denoted as n ⁺ region 144a. On the other hand, as the first semiconductor film 124 is approached, the donor-type element concentration is relatively decreased. A region having a donor-type element concentration of 1 × 10 ^{17 to} 3 × 10 ¹⁹ / cm ³ , preferably a region of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ is referred to as an n ⁻ region 144b. The concentration of the donor-type element in the n ⁺ region 144a is 10 to 100 times that of the donor-type element in the n ⁻ region.

The n ⁺ region 144a later functions as a source region and a drain region, and the n ⁻ region 144b functions as an LDD region. Note that there is no interface between the n ⁺ region and the n ⁻ region, and the interface varies depending on the relative donor concentration. As described above, the second semiconductor film containing the donor-type element formed by the ion doping method or the ion implantation method can control the concentration profile depending on the addition conditions, and the n ⁺ region and n ⁻ region films The thickness can be appropriately controlled.

  Note that the second semiconductor film 132 containing a donor-type element is added with a rare gas element, typically argon, so that distortion of the crystal lattice is formed. It is possible to getter elements.

Note that after formation of the first semiconductor film 124, a region that becomes a channel region of the TFT is a group 3 element (group 13 element, hereinafter referred to as an acceptor element) or a group 5 element (group 15 element, hereinafter referred to as a donor). The channel doping step of adding a low-concentration element) may be performed over the entire surface or selectively. This channel doping process is a process for controlling the TFT threshold voltage. Here, boron is added by an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation. Note that an ion implantation method in which mass separation is performed may be used.

Next, the first semiconductor film and the second semiconductor film are heated to form a first crystalline semiconductor film 141 as shown in FIG. In this case, silicide is formed in the portion of the semiconductor film in contact with the metal element that promotes crystallization, and the crystallization proceeds using the silicide as a nucleus. As shown by the arrow in FIG. The catalytic element obtained by crystallizing the film is moved to the second semiconductor film 132 to perform gettering of the catalytic element. By this step, the concentration of the catalytic element can be reduced to a level that does not affect the device characteristics. That is, the first crystalline semiconductor film 141 in which the nickel concentration in the film is 1 × 10 ¹⁸ / cm ³ or less, preferably 1 × 10 ¹⁷ / cm ³ or less can be formed. In addition, since the second semiconductor film to which the catalytic element after gettering has moved is also crystallized in the same manner, it is referred to as a second crystalline semiconductor film 142.

  Here, after the heat treatment for dehydrogenation (400 to 550 ° C., 0.5 to 2 hours), the heat treatment for crystallization (550 to 650 ° C. for 1 to 24 hours) is performed. Further, crystallization may be performed by RTA or GRTA. Here, by performing crystallization without laser light irradiation, variation in crystallinity can be reduced, and variation in TFTs to be formed later can be suppressed. In addition, since a ridge (convex concave portion) that grows on the protrusion on the crystal surface is difficult to form, the surface of the semiconductor region is relatively flat, and leakage current flowing between the gate insulating film and the gate electrode is suppressed. It is possible.

  In the present embodiment, the donor-type element in the second crystalline semiconductor film 142 is activated together with the gettering step.

  Next, as illustrated in FIG. 2A, a second mask 143 is formed over the second crystalline semiconductor film 142, and the second crystalline semiconductor film 142 and the second crystalline semiconductor film 142 are formed using the second mask. One crystalline semiconductor film 141 is etched to form a first semiconductor region 152 and a second semiconductor region 151 as shown in FIG.

  The second mask 143 forms an organic resin in a predetermined region by a droplet discharge method, a printing method, or the like. Further, as in the first mask, after the photosensitive material is applied or discharged, the photosensitive material is irradiated with a laser beam, exposed, and then developed. By forming the second mask by this method, it is possible to reduce the area of a semiconductor region to be formed later, and to increase the integration of semiconductor elements and increase the aperture ratio of a transmissive liquid crystal display device. It is.

  In the mask formation process of the following embodiments and examples, before applying a photosensitive material on a film or region formed of a semiconductor material, a film thickness of about several nanometers is formed on the surface of the semiconductor film or region. It is preferable to form an insulating film. This step can avoid direct contact between the semiconductor material and the photosensitive material, and can prevent impurities from entering the semiconductor film. Note that examples of a method for forming the insulating film include a method of applying an oxidizing solution such as ozone water, a method of irradiating oxygen plasma, ozone plasma, and the like.

The second crystalline semiconductor film and the first crystalline semiconductor film are made of chlorine gas such as Cl ₂ , BCl ₃ , SiCl _4, or CCl ₄ , CF ₄ , SF ₆ , NF ₃ , CHF _3, etc. Etching can be performed using a representative fluorine-based gas or O ₂ . The second crystalline semiconductor film is etched to form a first semiconductor region 152, and the first crystalline semiconductor film is etched to form a second semiconductor region 151.

  Next, after removing the second mask, a third conductive layer 153 with a thickness of 500 to 1500 nm, preferably 500 to 1000 nm is formed as shown in FIG. Next, a photosensitive material 154 is applied or discharged onto the third conductive layer, and the photosensitive material 154 is irradiated with the laser beam 155 by using a laser beam direct drawing apparatus. A third mask 161 as shown in FIG. Here, a positive photosensitive material is used as the photosensitive material 154.

  As a material for the third conductive layer 153, a material obtained by dissolving or dispersing a conductor in a solvent is used. Examples of the conductor include Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Zr, Ba, and other metals, silver halide, and the like. Fine particles or dispersible nanoparticles can be used. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used. Furthermore, you may have multiple types of the said metal fine particles or dispersion | distribution nanoparticle. A third conductive layer can be formed by stacking conductive layers made of these materials. The third conductive layer 153 functions as a wiring. Further, it is preferable to use a low resistance material in order to reduce the wiring resistance.

  In addition, it is preferable to use what dissolved or disperse | distributed the material of either gold | metal | money, silver, and copper in the solvent considering the specific resistance value as the composition discharged from a discharge outlet. More preferably, low resistance and inexpensive silver or copper may be used. However, when copper is used, a barrier film may be provided as a countermeasure against impurities. As the solvent, esters such as butyl acetate and ethyl acetate, alcohols such as isopropyl alcohol and ethyl alcohol, organic solvents such as methyl ethyl ketone and acetone may be used.

  Here, as a barrier film in the case of using copper as a wiring, an insulating or conductive material containing nitrogen such as silicon nitride, silicon oxynitride, aluminum nitride, titanium nitride, or tantalum nitride (TaN) is used. These may be formed by a droplet discharge method.

  The viscosity of the composition used for the droplet discharge method is preferably 5 to 20 mPa · s, which is to prevent the drying from occurring and to smoothly discharge the composition from the discharge port. . The surface tension is preferably 40 mN / m or less. Note that the viscosity of the composition may be appropriately adjusted according to the solvent to be used and the application. The viscosity of the composition in which silver is dissolved or dispersed in the solvent is 5 to 20 mPa · s, and the viscosity of the composition in which gold is dissolved or dispersed in the solvent is 10 to 20 mPa · s.

  The step of discharging the composition may be performed under reduced pressure. This is because the solvent of the composition volatilizes before the composition is discharged and landed on the object to be processed, and the subsequent drying and firing steps can be omitted or shortened. After discharging the solution, one or both of drying and baking steps are performed by laser light irradiation, rapid thermal annealing, a heating furnace, or the like under normal pressure or reduced pressure depending on the material of the solution. The drying and firing steps are both heat treatment steps. For example, the drying is performed at 100 degrees for 3 minutes, and the firing is performed at 200 to 350 degrees for 15 minutes to 120 minutes. Time is different. In order to satisfactorily perform the drying and firing steps, the substrate may be heated, and the temperature at that time depends on the material of the substrate or the like, but is 100 to 800 degrees (preferably 200 to 350 degrees). And By this step, the solvent in the solution is volatilized or the dispersant is chemically removed, and the surrounding resin is cured and shrunk to accelerate fusion and fusion. The atmosphere is an oxygen atmosphere, a nitrogen atmosphere or air. However, it is preferable to perform in an oxygen atmosphere in which the solvent in which the metal element is decomposed or dispersed is easily removed.

For the laser light irradiation, a continuous wave or pulsed gas laser or solid-state laser may be used. Examples of the former gas laser include an excimer laser and a YAG laser, and examples of the latter solid-state laser include a laser using a crystal such as YAG or YVO ₄ doped with Cr, Nd, or the like. Note that it is preferable to use a continuous wave laser because of the absorption rate of the laser light. In addition, a so-called hybrid laser irradiation method combining pulse oscillation and continuous oscillation may be used. However, depending on the heat resistance of the substrate, the heat treatment by laser light irradiation may be performed instantaneously within a few microseconds to several tens of seconds. Instantaneous thermal annealing (RTA) uses an infrared lamp or a halogen lamp that emits ultraviolet light or infrared light in an inert gas atmosphere to rapidly increase the temperature from several microseconds to several minutes. This is done by applying heat instantaneously. Since this treatment is performed instantaneously, there is an advantage that only the outermost thin film can be heated substantially without affecting the lower layer film.

  Here, a composition containing Ag (hereinafter referred to as “Ag paste”) is selectively ejected, and drying and firing by laser beam irradiation or heat treatment as described above are performed as appropriate to form a third film having a thickness of 600 to 800 nm. A conductive layer 153 is formed. At this time, the conductive layer is formed by irregularly overlapping fine particles, which are conductors, three-dimensionally. That is, it is composed of three-dimensional aggregate particles. For this reason, the surface has fine unevenness. Further, since the fine particles are baked and the particle diameter of the particles is increased depending on the temperature and time for heating the conductive layer, the layer has a large surface height difference.

Incidentally, the sintering is performed in an O ₂ atmosphere, organic substances such as binders contained in the Ag paste (thermosetting resin) is decomposed, it is possible to obtain a Ag film containing little organic matter. Further, the film surface can be smoothed using a press machine or the like.

  In the conductive film forming process of the embodiment and the example, when an insulating film is formed on the surface of the semiconductor film during the photosensitive resin coating or discharging process, the conductive film is formed before the conductive film is formed in order to reduce the contact resistance. It is preferable to etch the insulating film.

  Next, the third conductive layer 153 is etched into a desired shape using the third mask 161 to form fourth conductive layers 162 and 163. The fourth conductive layers 162 and 163 function as a source electrode and a drain electrode. At this time, the third conductive layer is divided to form a source electrode and a drain electrode, and etching is performed so that the width of the source electrode functioning as the source wiring or the drain electrode functioning as the drain wiring is narrowed. Thus, the aperture ratio of a liquid crystal display device to be formed later can be increased.

  Next, the exposed portion of the first semiconductor region 152 is etched using the third mask 161 to form third semiconductor regions 164 and 165 that function as a source region and a drain region. At this time, part of the second semiconductor region 151 may be over-etched. The over-etched second semiconductor region at this time is referred to as a fourth semiconductor region 166. The fourth semiconductor region 166 functions as a channel formation region.

  Next, after removing the third mask, as shown in FIG. 2E, a film thickness of 100 to 100 which functions as a passivation film over the surfaces of the fourth conductive layers 162 and 163 and the fourth semiconductor region 166 is obtained. A second insulating film 171 with a thickness of 300 nm is preferably formed. The passivation film is formed using a thin film formation method such as plasma CVD or sputtering, and silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxynitride, or aluminum oxide, diamond-like carbon (DLC), nitrogen-containing carbon (CN) and other insulating materials can be used. Note that the passivation film may be a single layer or a laminated structure. Here, silicon oxide or silicon oxynitride is preferably formed from the interface characteristics of the fourth semiconductor region 166, and a silicon nitride film or a silicon nitride oxide film is preferably formed thereover.

  Thereafter, the fourth semiconductor region is preferably hydrogenated by heating in a hydrogen atmosphere or a nitrogen atmosphere. Note that in the case of heating in a nitrogen atmosphere, an insulating film containing hydrogen is preferably formed as the second insulating film.

  Through the above steps, an inverted staggered TFT having a crystalline semiconductor film can be formed.

  Next, a third insulating film 172 having a thickness of 500 to 1500 nm is formed over the second insulating film 171. As the third insulating film, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride and other inorganic insulating materials, acrylic acid, methacrylic acid and derivatives thereof, or polyimide (polyimide) Si—O— among compounds consisting of silicon, oxygen, and hydrogen formed from a heat-resistant polymer such as aromatic polyamide, polybenzimidazole, or a siloxane polymer-based material typified by silica glass. Inorganic siloxane polymers containing Si bonds, alkyl siloxane polymers, alkyl silsesquioxane polymers, hydrogenated silsesquioxane polymers, hydrogenated alkyl silsesquioxane polymers such as hydrogen on silicon such as methyl and phenyl Organosiloxane polymer based insulating material which is substituted by an organic group can be used. As a forming method, a known method such as a CVD method, a coating method, or a printing method is used. Note that the surface of the third insulating layer can be planarized by being formed by a coating method. Here, the third insulating film is formed by applying and baking an acrylic resin by a coating method. In the case of a reflective liquid crystal display device or a transflective liquid crystal display device, the third insulating film has unevenness, whereby light can be reflected more externally. In this case, an insulating layer having unevenness can be formed using the third insulating film by a droplet discharge method, a printing method, or the like.

  Note that in the case where the second insulating film 171 has a thickness that does not cause parasitic capacitance between the fifth conductive layer 173 and the fourth conductive layers 162 and 163 to be formed later, the third insulating film 171 The film 172 is not necessarily required.

  Next, after a fourth mask (not shown) is formed over the third insulating film 172, the third insulating film 172, the second insulating film 171, and the insulating film 123a which is the first insulating film are used. , 123b, and 123c are etched to expose the second conductive layer 122b that functions as a connection portion of the gate electrode. Next, after removing the fourth mask, a fifth conductive layer 173 having a thickness of 500 to 1500 nm, preferably 500 to 1000 nm, which functions as a gate wiring is formed. For the fourth mask, a method and a material similar to those of the second mask 143 can be used as appropriate. As a material and a formation method of the fifth conductive layer 173, a material and a formation method similar to those of the third conductive layer 153 may be selected as appropriate. In order to suppress wiring resistance, it is preferable to use a low resistance material. Alternatively, the line width may be reduced by etching the fifth conductive layer 173 with a mask formed using a laser beam direct writing apparatus like the first conductive layer. By this step, the wiring area in the pixel can be reduced, and the aperture ratio can be improved in the transmissive liquid crystal display device. Here, the fifth conductive layer 173 is formed by discharging Ag paste and drying and baking.

  Next, a fourth insulating film 174 is formed over the fifth conductive layer 173 and the third insulating film 172. As the fourth insulating film 174, a material similar to that of the third insulating film 172 can be used as appropriate. In the case of forming a reflective liquid crystal display device or a transflective liquid crystal display device, the fourth insulating film has unevenness, whereby light can be reflected more externally. In this case, an insulating layer having unevenness can be formed using the third insulating film by a droplet discharge method, a printing method, or the like.

  Next, after a fifth mask (not shown) is formed over the fourth insulating film 174, the fourth insulating film 174, the third insulating film 172, and a part of the second insulating film 171 are etched. Then, a part of the fourth conductive layer 163 is exposed. Next, after removing the fifth mask, a sixth conductive layer 175 having a thickness of 100 to 200 nm which functions as a pixel electrode is formed. As the fifth mask, a method and a material similar to those of the second mask 143 can be used as appropriate. As a typical material of the sixth conductive layer 175, a light-transmitting conductive film or a reflective conductive film can be given. As a material for the light-transmitting conductive film, indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc oxide added with gallium (GZO), indium tin oxide containing silicon oxide, or the like Is mentioned. In addition, as a material for the conductive film having reflectivity, a metal such as aluminum (Al), titanium (Ti), silver (Ag), and tantalum (Ta), or a concentration less than the stoichiometric composition ratio with the metal is used. Examples thereof include a metal material containing nitrogen, or titanium nitride (TiN), tantalum nitride (TaN) which is a nitride of the metal, or aluminum containing 1 to 20% nickel. Further, in the case of a transflective liquid crystal display device, the sixth conductive layer may be formed using a light-transmitting conductive film and a reflective conductive film.

  As a method for forming the sixth conductive layer 175, a droplet discharge method, a sputtering method, a vapor deposition method, a CVD method, a coating method, or the like is appropriately used. By using a droplet discharge method, the sixth conductive layer can be selectively formed. Further, when a sputtering method, a vapor deposition method, a CVD method, a coating method, or the like is used, after forming a mask in the same manner as the second conductive layer, the conductive film is etched using the mask to form a sixth conductive layer. Form.

  Note that although a conductive layer functioning as a gate wiring is formed as the fifth conductive layer 173 and a conductive layer functioning as a pixel electrode is formed as the sixth conductive layer 175 here, the invention is not limited to this. After forming a conductive layer functioning as a pixel electrode, a conductive layer functioning as a gate wiring may be formed.

  Through the above steps, an active matrix substrate can be formed.

  The inverted staggered TFT formed in this embodiment uses a material having high heat resistance for the gate electrode, and after performing heat treatment for simultaneously performing the activation process, the gettering process, and the crystallization process, Wirings such as signal lines and scanning lines are formed using a resistance material. Therefore, a TFT having crystallinity, a small amount of impurity metal elements, and low wiring resistance can be formed. In the liquid crystal display device of the present invention, a pixel electrode can be formed over the insulating film, and the aperture ratio can be increased.

  For this reason, since it is formed of a crystalline semiconductor film, it has higher mobility than an inverted staggered TFT formed of an amorphous semiconductor film. Further, the source region and the drain region contain a catalyst element in addition to the donor element. For this reason, a source region and a drain region having low contact resistance with the semiconductor region can be formed. As a result, a semiconductor device that requires high-speed operation can be manufactured.

  Further, as compared with a TFT formed using an amorphous semiconductor film, a threshold shift is less likely to occur, and variation in TFT characteristics can be reduced. Therefore, display unevenness can be reduced and a highly reliable semiconductor device can be manufactured as compared with a liquid crystal display device using a TFT formed of an amorphous semiconductor film as a switching element. It is.

  Further, since the metal element mixed in the semiconductor film in the film formation stage is also gettered by the gettering step, off current can be reduced. By providing such a TFT in a switching element of a liquid crystal display device, contrast can be improved.

  In the present embodiment, therefore, a thin film material or a resist may be discharged to a predetermined place using a droplet discharge method without forming a thin film on the entire surface of the substrate, and a TFT can be used without using a photomask. Can be formed. For this reason, it is possible to improve throughput and yield and to reduce costs.

(Embodiment 2)
In this embodiment mode, a stacked structure of source wirings, gate wirings, and pixel electrodes of the active matrix substrate shown in Embodiment Mode 1 will be described with reference to FIGS.

  FIG. 3A is a view showing a stacked structure of the inverted staggered TFT in this embodiment and a fifth conductive layer functioning as a gate wiring. The cross-sectional structure of FIG. 2E and FIG. This corresponds to the cross-sectional structure of A-B.

  FIG. 3B functions as a fourth conductive layer functioning as a source wiring, a fifth conductive layer functioning as a gate wiring, a second conductive layer functioning as a connection portion of the gate electrode, and a pixel electrode. It is a figure which shows the laminated structure of a 6th conductive layer, and is equivalent to the cross-section of CD of FIG.3 (C). Hereinafter, the fourth conductive layer functioning as the source wiring is the source wirings 162a and 162b, the fourth conductive layer functioning as the drain electrode is the gate wiring 173a, and the fifth conductive layer functioning as the gate wiring of the drain electrode 163a is the gate. The second conductive layer functioning as an electrode connection portion is referred to as a gate electrode connection portion 122a, 122b, and the sixth conductive layer functioning as a pixel electrode is referred to as a pixel electrode 175a.

  As shown in FIG. 3B, a first insulating film 123 is formed over the connection portion 122b of the gate electrode, and a capacitor wiring 181, a source wiring 162b, and a drain electrode 163a are formed over the first insulating film 123. Is done. Further, a second insulating film 171 and a third insulating film 172 are formed over the capacitor wiring 181, the source wiring 162 b, the drain electrode 163 a, and the first insulating film 123, and the gate wiring is formed over the third insulating film 172. 173a is formed. That is, the source wiring and the capacitor wiring intersect with the gate wiring 173a through the second insulating film 171 and the third insulating film 172. Note that in FIGS. 3A and 3B, the insulating films 123a, 123b, and 123c described in Embodiment 1 are representatively illustrated as the first insulating film 123.

  As shown in FIG. 3B, a fourth insulating film 174 is formed over all of the gate wiring 173 a and the third insulating film 172, and a pixel electrode 175 a is formed over the fourth insulating film 174. . That is, the pixel electrode 175a covers part of the gate wiring 173a with the fourth insulating film 174 interposed therebetween. Since the fourth insulating film 174 on which the pixel electrode 175a is formed is formed using a planarization layer, it is possible to suppress disorder in the alignment of a liquid crystal material that is filled between the pixel electrodes later. It is possible to improve the contrast of the device.

  Note that although the fourth insulating film 174 is formed over all of the gate wiring 173a and the third insulating film 172 here, the fourth insulating film 174 is provided so as to cover the gate wiring 173a and the third insulating film 172 around the gate wiring 173a. Also good. In this case, the fourth insulating film is partially formed by a droplet discharge method or a printing method. In the case of this structure, since the fourth insulating film is partially formed, raw materials can be reduced and the cost can be reduced.

  In this embodiment, as indicated by EF in FIG. 3C, the end portion of the pixel electrode is formed on the source wiring. For this reason, in the case of a transmissive liquid crystal display device, even if alignment disorder of the liquid crystal material occurs at the end portion of the pixel electrode, since the source wiring covers the region, display unevenness can be reduced.

(Embodiment 3)
In this embodiment, an active matrix substrate having a stacked structure of gate wiring and source wiring will be described with reference to FIG.

  FIG. 4A is a diagram illustrating a stacked structure of the inverted staggered TFT and the gate wiring in this embodiment, and corresponds to a cross-sectional structure taken along AB in FIG. Over the first insulating film 123, a fourth semiconductor region, a fourth conductive layer functioning as a drain electrode (hereinafter referred to as a drain electrode 163a) 163, a pixel electrode 1112, and a gate wiring 1113 are formed. The drain electrode 163a and the pixel electrode 1112 are connected without an insulating film interposed therebetween. The gate electrode connection portion 122 a and the gate wiring 1113 are connected to each other through the first insulating film 123. In addition, an insulating film 1114 functioning as a passivation film is formed over the source wiring 162 a, the drain electrode 163 a, the pixel electrode 1112, the first insulating film 123, and the gate wiring 1113. Note that in FIGS. 4A and 4B, the insulating films 123a, 123b, and 123c described in Embodiment 1 are representatively illustrated as the first insulating film 123.

  4B illustrates a stacked structure of the source wiring 162b, the gate wiring 1113, the gate electrode connection portion 122b, and the pixel electrode 1112, and corresponds to a cross-sectional structure taken along line CD in FIG. 4C. .

  As shown in FIG. 4B, a first insulating film 123 is formed over the connection portion 122b of the gate electrode, and a capacitor wiring 181, a source wiring 162b, a drain electrode 163a, a drain are formed over the first insulating film 123. A pixel electrode 1112 connected to the electrode 163a is formed. In addition, a second insulating film 1111 is formed over the capacitor wiring 181 and the source wiring 162b, and a gate wiring 1113 is formed over the second insulating film 1111. In other words, the source wiring and the capacitor wiring intersect with the gate wiring 1113 with the second insulating film 1111 interposed therebetween. Here, the second insulating film 1111 is formed by a droplet discharge method or a printing method.

  In this embodiment, the second insulating film 1111 is provided only in a region where the source wiring, the capacitor wiring, and the gate wiring intersect. For this reason, unlike Embodiment 2, since it forms only in a part, it can reduce a raw material and can reduce cost.

  Alternatively, the third insulating film may be formed in a region where the gate wiring 1113 and the pixel electrode 1112 overlap with a droplet discharge method or a printing method. In this case, a region formed by the pixel electrode can be enlarged, and the aperture ratio can be increased.

(Embodiment 4)
In this embodiment, an active matrix substrate having a stacked structure of gate wiring and source wiring will be described with reference to FIG.

  FIG. 5A is a diagram showing a stacked structure of an inverted staggered TFT and a gate wiring in this embodiment, and corresponds to a cross-sectional structure taken along AB in FIG.

  FIG. 5B illustrates a stacked structure of the source wiring 162b, the gate wiring 1121b, the gate electrode connection portion 122b, and the pixel electrode 1122, and corresponds to the cross-sectional structure taken along line CD in FIG. .

  As shown in FIG. 5B, a first insulating film 123 is formed over the gate electrode connection portions 122a and 122b, and a capacitor wiring 181, a source wiring 162b, and a drain electrode 163a are formed over the first insulating film 123. Is formed. A second insulating film 171 and a third insulating film 172 are formed over the capacitor wiring 181, the source wiring 162 b, the drain electrode 163 a, and the first insulating film 123, and a gate is formed over the third insulating film 172. A wiring 1121b is formed. That is, the source wiring 162 b and the capacitor wiring 181 intersect with the gate wiring 1121 b through the second insulating film 171 and the third insulating film 172. Note that in FIGS. 5A and 5B, the insulating films 123a, 123b, and 123c described in Embodiment 1 are representatively illustrated as the first insulating film 123.

  Note that here, as illustrated in FIG. 5C, the gate wiring 1121b is formed for each pixel and is connected to connection portions 122a and 122b of gate electrodes provided in adjacent pixels. For this reason, the material of the gate wiring 1121b does not need to be a particularly low resistance material, and the selection range of the material is widened.

  In addition, a fourth insulating film 174 is formed over the third insulating film 172, and a pixel electrode 1122 is formed over the fourth insulating film 174. That is, the pixel electrode 1122 may cover part of the gate wiring 1121b with the fourth insulating film 174 interposed therebetween. Since the fourth insulating film 174 in which the pixel electrode 1122 is formed is formed using a planarization layer, it is possible to suppress disorder in the alignment of a liquid crystal material that is filled between the pixel electrodes later. It is possible to improve the contrast of the device.

  Note that although the fourth insulating film 174 is formed over the gate wiring 1121b and the third insulating film 172 here, the fourth insulating film 174 may be provided so as to cover the gate wiring 1121b and the third insulating film 172 around the gate wiring 1121b. Good. In this case, the fourth insulating film is partially formed by a droplet discharge method or a printing method. In the case of this structure, since the fourth insulating film is partially formed, raw materials can be reduced and the cost can be reduced.

(Embodiment 5)
In the present embodiment, an active matrix substrate having a stacked structure of gate wiring and source wiring will be described with reference to FIG.

  FIG. 6A is a diagram showing a laminated structure of the inverted staggered TFT and the gate wiring in this embodiment, and corresponds to a cross-sectional structure taken along AB in FIG. 6C. Over the first insulating film 123, a fourth semiconductor region 166, a drain electrode 163a, a pixel electrode 1132, and a gate wiring 1133a are formed. The drain electrode 163a and the pixel electrode 1132 are connected without an insulating film interposed therebetween.

  6B illustrates a stacked structure of the source wiring 162b, the gate wiring 1133b, the gate electrode connection portion 122b, and the pixel electrode 1132, and corresponds to a cross-sectional structure taken along line CD in FIG. 6C. .

  As shown in FIG. 6B, a first insulating film 123 is formed over the gate electrode connection portion 122b, and a capacitor wiring 181, a source wiring 162b, a drain electrode 163a, a drain are formed over the first insulating film 123. A pixel electrode 1132 connected to the electrode 163a is formed. In addition, a second insulating film 1131 is formed over the capacitor wiring 181 and the source wiring 162b, and a gate wiring 1133b is formed over the second insulating film 1131. In other words, the source wiring and the capacitor wiring intersect with the gate wiring 1133b with the second insulating film 1131 interposed therebetween. Here, the second insulating film 1131 is formed by a droplet discharge method or a printing method. Note that in FIGS. 6A and 6B, the insulating films 123a, 123b, and 123c described in Embodiment 1 are representatively illustrated as the first insulating film 123.

  In this embodiment, the second insulating film 1131 is provided only in a region where the source wiring, the capacitor wiring, and the gate wiring intersect. For this reason, unlike Embodiment 4, since it forms only in a part, it can reduce a raw material and can reduce cost.

  Further, a third insulating film may be formed by a droplet discharge method or a printing method in a region where the gate wiring 1133b and the pixel electrode 1132 overlap. In this case, a region formed by the pixel electrode can be enlarged, and the aperture ratio can be increased.

(Embodiment 6)
In this embodiment, an active matrix substrate having a stacked structure of gate wiring and source wiring will be described with reference to FIG.

  FIG. 7A is a diagram illustrating a stacked structure of the inverted staggered TFT and the fifth conductive layer functioning as a gate wiring in this embodiment, and corresponds to a cross-sectional structure taken along AB in FIG. 7C. To do.

  FIG. 7B illustrates a stacked structure of the source wiring 1143b, the gate wirings 1145a and 1145b, the gate electrode connection portion 122b, and the pixel electrode 1142, which has a cross-sectional structure taken along line CD in FIG. Equivalent to.

  As shown in FIG. 7B, a first insulating film 123 is formed over the gate electrode connection portions 122a and 122b, and a capacitor wiring 1144, a source wiring 1143b, and a drain electrode 1147 are formed over the first insulating film 123. Gate wirings 1145a and 1145b are formed. Note that the gate wirings 1145a and 1145b are connected to the gate electrode connecting portions 122a and 122b through the first insulating film 123, respectively. Note that in FIGS. 7A and 7B, the insulating films 123a, 123b, and 123c described in Embodiment 1 are representatively illustrated as the first insulating film 123.

  In addition, as illustrated in FIG. 7C, the gate wirings 1145a and 1145b are provided in the respective pixels. Here, the gate wirings 1145a and 1145b, the source wiring 1143b, the drain electrode 1147, and the capacitor wiring 1144 do not intersect each other. Therefore, when these electrodes and wirings are formed by a droplet discharge method, they can be formed at the same time, so that mass productivity can be improved.

  A second insulating film 171 and a third insulating film 172 are formed over the gate wirings 1145a and 1145b, the source wiring 1143b, the drain electrode 1147, and the capacitor wiring 1144, and the conductive layer 1146a is formed over the third insulating film 172. 1146b are formed. Further, the conductive layer 1146b is connected to the gate wirings 1145a and 1145b through the second insulating film 171 and the third insulating film 172. Therefore, the gate wiring provided in each pixel is electrically connected through the conductive layers 1146a and 1146b. The source wiring intersects with the conductive layers 1146a and 1146b with the second insulating film 171 and the third insulating film 172 interposed therebetween.

  Note that here, the conductive layers 1146a and 1146b are formed for each pixel and are connected to gate electrode connecting portions 122a and 122b provided in adjacent pixels. For this reason, the range of selection of materials for the conductive layers 1146a and 1146b is widened.

  In addition, a fourth insulating film 174 is formed over the third insulating film 172, and a pixel electrode 1142 is formed over the fourth insulating film 174. That is, the pixel electrode 1142 covers part of the conductive layer 1146b with the fourth insulating film 174 interposed therebetween. Since the fourth insulating film 174 in which the pixel electrode 1142 is formed is formed using a planarization layer, it is possible to suppress disorder in the orientation of a liquid crystal material that is filled between the pixel electrodes later. It is possible to improve the contrast of the device.

  Note that although the fourth insulating film 174 is formed over the conductive layers 1146a and 1146b and the third insulating film 172 here, the conductive layers 1146a and 1146b and the third insulating film 172 around the conductive layers 1146a and 1146b are covered. It may be provided as follows.

(Embodiment 7)
In the present embodiment, an active matrix substrate having a stacked structure of gate wiring and source wiring will be described with reference to FIG.

  FIG. 8A is a diagram showing a laminated structure of the inverted staggered TFT and the gate wiring in this embodiment, and corresponds to a cross-sectional structure taken along AB in FIG. 8C. Over the first insulating film 123, a source wiring 1153a, a fourth semiconductor region 166, a drain electrode 1157, a pixel electrode 1152, and a gate wiring 1155a are formed. The drain electrode 1157 and the pixel electrode 1132 are connected without an insulating film interposed therebetween.

  FIG. 8B illustrates a stacked structure of the source wiring 1153b, the gate wirings 1155a and 1155b, the gate electrode connection portion 122b, and the pixel electrode 1152, and has a cross-sectional structure taken along line CD in FIG. Equivalent to.

  As shown in FIG. 8B, a first insulating film 123 is formed over the connection portion 122b of the gate electrode, and a capacitor wiring 1154, a source wiring 1153b, a drain electrode 1154a, a drain are formed over the first insulating film 123. A pixel electrode 1152 connected to the electrode 1157 and gate wirings 1155a and 1155b are formed. In addition, a second insulating film 1151 is formed over the capacitor wiring 1154 and the source wiring 1153b, and a conductive layer 1156b is formed over the second insulating film 1151. Gate wirings 1155a and 1155b are provided in the respective pixels. Here, the gate wirings 1155a and 1155b, the source wiring 1153b, the drain electrode 1157, and the capacitor wiring 1154 do not intersect each other. For this reason, when forming by a droplet discharge method, since it can form simultaneously, it is possible to improve mass-productivity. Note that in FIGS. 8A and 8B, the insulating films 123a, 123b, and 123c described in Embodiment 1 are representatively illustrated as the first insulating film 123.

  The conductive layer 1156b is connected to the gate wirings 1155a and 1155b through the second insulating film 1151, respectively. Therefore, the gate wiring provided in each pixel is electrically connected through the conductive layers 1156a and 1156b. In addition, the source wiring and the capacitor wiring intersect with the gate wirings 1155a and 1155b and the conductive layers 1156a and 1156b with the second insulating film 1151 interposed therebetween.

  In this embodiment, the second insulating film 1151 is provided only in a region where the source wiring, the capacitor wiring, and the gate wiring intersect. For this reason, unlike Embodiment 6, since it forms only in a part, it can reduce raw materials and can reduce cost.

  Further, a third insulating film may be formed by a droplet discharge method or a printing method in a region where the conductive layer and the pixel electrode 1152 overlap. In this case, a region formed by the pixel electrode can be enlarged, and the aperture ratio can be increased.

(Embodiment 8)
In this embodiment, an active matrix substrate having a stacked structure of gate wiring and source wiring will be described with reference to FIG.

  FIG. 36A is a diagram illustrating a stacked structure of the inverted staggered TFT and the gate wiring in this embodiment, and corresponds to a cross-sectional structure taken along line AB in FIG. On the first insulating film 123, a fourth semiconductor region 166, a drain electrode 1157, and a pixel electrode 1152 are formed. The drain electrode 1157 and the pixel electrode 1152 are connected without an insulating film interposed therebetween. The first insulating film on the gate electrode connection portion 722a is removed, and a gate wiring 1165a is formed thereover. With such a structure, the contact resistance between the gate electrode connection portion and the gate wiring can be reduced. Further, the connection structure between the gate electrode connection portion 722a and the gate wiring 1165a as in this embodiment can be applied to each of Embodiments 2 to 7.

  FIG. 36B illustrates a stacked structure of the source wiring 1163b, the gate wirings 1165a and 1165b, the conductive layer 1166b, and the pixel electrode 1152, and corresponds to the cross-sectional structure taken along the line CD in FIG.

  As shown in FIG. 36B, a conductive layer 1166b formed in the same process as the gate electrode 721a and the gate electrode connection portion 722a is formed on the substrate surface. Further, when the first insulating film on the surface of the gate electrode connection portion 722a is removed, the first insulating film on the surface of the conductive layer 1166b is removed. After that, a second insulating film 1161 is formed over the conductive layer 1166b. At this time, the second insulating film 1161 is preferably formed so that both end portions of the conductive layer 1166b are exposed.

  Next, simultaneously with the formation of the drain electrode 1157 over the first insulating film, gate wirings 1165a and 1165b are formed over the conductive layer 1166b, and simultaneously, the source wiring 1163b and the capacitor wiring 1164 are formed over the second insulating film 1161. Form. Here, these conductive layers do not intersect. For this reason, when forming by a droplet discharge method, since it can form simultaneously, it is possible to improve mass-productivity.

  In this embodiment, the gate wirings 1165a and 1165b formed for each pixel are electrically connected through the conductive layers 1166a and 1166b. In addition, the gate wiring and the source wiring intersect with each other through the second insulating film 1161 formed over the conductive layer 1166b.

  In this embodiment, the second insulating film 1161 is provided only in a region where the source wiring, the capacitor wiring, and the gate wiring intersect. For this reason, since it forms only in a part, it is possible to reduce raw materials, and cost reduction is possible.

  Further, the third insulating film may be formed by a droplet discharge method or a printing method in a region where the gate wirings 1165a and 1165b, the capacitor wiring 1164, the source wirings 1163a and 1163b, and the pixel electrode 1152 overlap. In this case, the region for forming the pixel electrode can be enlarged, and the aperture ratio can be increased.

(Embodiment 9)
In the present embodiment, a modification of the crystallization and gettering steps in Embodiment 1 will be described with reference to FIG.

  As shown in FIG. 9A, first conductive layers 221a and 222a are formed and a first insulating film 123 is formed in accordance with the same steps as in the first embodiment. Here, the first insulating film 123 has the same configuration as the first insulating film of the first embodiment, and the insulating films 123a, 123b, and 123c shown in the first embodiment are representative of the first insulating film. 123.

  Next, as shown in FIG. 9B, the first semiconductor film 124, the layer 125 having a catalytic element thereon, and the second semiconductor film 132 are formed thereon by the same process as in the first embodiment. To do.

  Note that after the first semiconductor film 124 is formed, a channel doping process may be performed on the entire surface or selectively.

  Next, as shown in FIG. 9C, the first semiconductor film and the second semiconductor film are heated by a process similar to that of Embodiment Mode 1, and the first crystalline semiconductor film 141 and the second semiconductor film are heated. A crystalline semiconductor film 142 is formed. In crystallization, silicide is formed in a portion of the semiconductor film in contact with a metal element that promotes crystallization of the semiconductor, and crystallization proceeds using the silicide as a nucleus.

  Simultaneously with the progress of crystallization, as indicated by an arrow in FIG. 9C, the catalytic element that contributes to the crystallization of the first semiconductor film is moved to the second semiconductor film 132 and gettered. The concentration of the catalytic element is reduced to form the first crystalline semiconductor film 141, and the second semiconductor film to which the catalytic element after gettering has moved is crystallized to form the second crystalline semiconductor film 142. It is formed.

In this embodiment, a layer containing a catalytic element is formed on the first semiconductor film. For this reason, unlike Embodiment 1, it is possible to reduce the oxygen concentration in the first semiconductor film by continuously forming the first insulating film and the first semiconductor film. For example, as the first insulating film, a silicon nitride film is formed by a CVD method using silane and ammonia gas as raw materials, and the silicon oxide film is then switched from the ammonia gas to nitrogen oxide (N ₂ O) by the CVD method. To form a first insulating film. Next, only silane gas is allowed to flow into the chamber without generating plasma. This makes it possible to reduce the oxygen concentration in the chamber. Thereafter, the first semiconductor film having a low oxygen concentration can be formed by forming the first semiconductor film by a CVD method using silane gas as a raw material.

  Note that the present embodiment can be applied to any one of the first to eighth embodiments.

(Embodiment 10)
In this embodiment, a process of forming a channel protection type TFT through the same gettering process as that of Embodiment 1 will be described with reference to FIG.

  As shown in FIG. 10A, the first conductive layers 221a and 222a are formed, the first insulating film 123 is formed, and the layer 125 including a catalytic element is formed by the same process as that of the first embodiment. A first semiconductor film 124 is formed. Next, after a second insulating film 128 is formed over the first semiconductor film 124, a second mask 119 is formed over the second insulating film. Note that in FIG. 10, the insulating films 123 a, 123 b, and 123 c described in Embodiment 1 are representatively illustrated as the first insulating film 123.

  Here, the second insulating film 128 is any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), and the like. This is an insulating film formed of a single layer. Alternatively, the insulating films may be combined as appropriate to form a stacked structure.

  The second mask 119 is formed by a droplet discharge method or a laser beam direct writing apparatus.

  Next, the second insulating film 128 is etched using the second mask 119 to form a first insulating region 129 as shown in FIG. The first insulating region 129 functions as a channel protective layer.

  As shown in FIG. 10C, a second semiconductor film 132 is formed over the first semiconductor film 124 and the first insulating region 129, and the first semiconductor film 124 and The second semiconductor film 132 is heated. As a result, the first crystalline semiconductor film 141 in which the concentration of the catalytic element is reduced and the second crystalline semiconductor film 142 having the catalytic element are formed. With heating, the catalytic element is gettered as shown by the arrow in FIG.

  Thereafter, a channel protection type TFT can be formed according to the same steps as those in the first embodiment. Note that the present embodiment can be applied to any one of the first to eighth embodiments.

(Embodiment 11)
In this embodiment mode, a method for forming a channel protection type TFT according to the same gettering process as that in Embodiment Mode 12 will be described with reference to FIG.

  As shown in FIG. 11A, the first conductive layers 221a and 222a are formed, the first insulating film 123 is formed, and the first semiconductor film 124 is formed according to the same steps as in the first embodiment. Then, a layer 125 containing a catalytic element is formed, a second insulating film 128 is formed, and a second mask 119 is formed by a discharge method or a laser beam direct drawing apparatus. Note that in FIG. 11, the insulating films 123 a, 123 b, and 123 c shown in Embodiment Mode 1 are representatively shown as the first insulating film 123.

  Next, the second insulating film 128 is etched using the second mask 119 to form a first insulating region 129 as shown in FIG. The first insulating region 129 functions as an etching protective film.

  Next, as illustrated in FIG. 11C, the second semiconductor film 132 is formed over the layer 125 having the catalytic element and the first insulating region 129, and the first semiconductor film is manufactured by a process similar to that in Embodiment 1. By heating the second semiconductor film, the first crystalline semiconductor film 141 in which the concentration of the catalytic element is reduced and the second crystalline semiconductor film 142 having the catalytic element are formed. With heating, the catalytic element is gettered as shown by the arrow in FIG.

  Thereafter, a channel protection type TFT can be formed by following the same process as in the tenth embodiment. Note that the present embodiment can be applied to any one of the first to eighth embodiments.

Embodiment 12
In this embodiment, a process for forming a TFT by gettering a catalytic element using a semiconductor film containing a rare gas element instead of a semiconductor film containing a donor element will be described with reference to FIGS.

  As shown in FIGS. 12A and 12B, a first conductive layer 221a is formed by a process similar to that of Embodiment Mode 1, a first insulating film 123 is formed, and a layer 125 having a catalytic element is formed. The first semiconductor film 124 is formed. Next, an oxide film with a thickness of 1 to 5 nm may be formed on the surface of the first semiconductor film. Here, ozone water is applied to the surface of the crystalline semiconductor film to form an oxide film. Note that a channel doping step may be performed after the first semiconductor film 124 is formed. In FIG. 12, the insulating films 123a, 123b, and 123c shown in Embodiment Mode 1 are representatively shown as the first insulating film 123.

  Next, a second semiconductor film 232 containing a rare gas element is formed over the first semiconductor film 124 by a known method such as a PVD method or a CVD method. The second semiconductor film 232 is preferably an amorphous semiconductor film.

Next, the first semiconductor film 124 and the second semiconductor film 232 are heated by a method similar to that in Embodiment 1 to crystallize the first semiconductor film as indicated by an arrow in FIG. The catalyst element crystallized is moved to the second crystalline semiconductor film 242, and the catalyst element is gettered. As a result, the first crystalline semiconductor film 241 in which the concentration of the catalytic element is reduced and the second crystalline semiconductor film 242 having the catalytic element are formed. By this step, as in the first embodiment, the concentration at which the catalytic element in the first crystalline semiconductor film does not affect the device characteristics, that is, the concentration of the catalytic element in the film is 1 × 10 ¹⁸ / cm ³ or less, preferably It can be 1 × 10 ¹⁷ / cm ³ or less.

  Next, as shown in FIG. 12D, after the second crystalline semiconductor film 242 is removed, a conductive third semiconductor film 243 is formed. Here, the second semiconductor film is formed by a plasma CVD method in which a gas containing a group 13 or group 15 element such as boron, phosphorus, or arsenic is added to a silicide gas. Note that the third semiconductor film may be formed using a film having any state selected from an amorphous semiconductor, a SAS, a crystalline semiconductor, and μc. Note that in the case where the third semiconductor film is any one of a conductive amorphous semiconductor film, SAS, and μc, heat treatment for activating impurities is performed thereafter. On the other hand, when the third semiconductor film is a crystalline semiconductor having conductivity, heat treatment is not necessarily performed. Here, an amorphous silicon film containing phosphorus with a thickness of 100 nm is formed by plasma CVD, and then heated at 550 ° C. for 2 hours to activate the impurities.

  Next, as illustrated in FIG. 12E, a first semiconductor region 252, a second semiconductor region 251, and a third conductive layer 153 are formed by the same process as that of Embodiment Mode 1. Next, after the photosensitive material 254 is applied or discharged, part of the photosensitive material is irradiated with laser light 255 to form a mask 260 as illustrated in FIG.

  Next, as illustrated in FIG. 12F, a source electrode 156 and a drain electrode 157 are formed. In addition, by the same process as that in Embodiment 1, the second semiconductor region and the first semiconductor region are etched to form a third semiconductor region 262 that functions as a source region and a drain region, and a fourth function that functions as a channel formation region. The semiconductor region 261 can be formed.

  Thereafter, an inverted staggered TFT and an active matrix substrate can be formed by the same process as in the first embodiment. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. Further, the present embodiment can be applied to any one of the first to eighth embodiments.

(Embodiment 13)
In this embodiment, the step of forming the n-channel TFT and the p-channel TFT on the same substrate is formed using FIG.

  As shown in FIG. 13A, the first conductive layers 301 and 302 are formed over the substrate 101 as in Embodiment 1, the first insulating film 123 is formed over the first conductive layer, and Through a process similar to that of Embodiment 1, a layer having a catalytic element, a first semiconductor film, and a second semiconductor film containing a donor-type element thereon are formed. Next, the first crystalline semiconductor film and the second semiconductor film are etched into a desired shape by using a mask formed by a droplet discharge method or a laser beam direct writing apparatus, so that the first semiconductor A region and a second semiconductor region are formed. Note that in FIG. 13, the insulating films 123 a, 123 b, and 123 c described in Embodiment 1 are representatively illustrated as the first insulating film 123.

  Next, the first semiconductor region and the second semiconductor region are heated to crystallize the second semiconductor region, and the catalyst element crystallized from the second semiconductor region is moved to the first semiconductor region. And gettering the catalytic element. Here, the first semiconductor region to which the catalytic element after gettering has moved is referred to as third semiconductor regions 313 and 134, and the second semiconductor region in which the metal element concentration is reduced is the fourth semiconductor regions 311 and 312. It shows. Note that the third semiconductor region and the fourth semiconductor region are each crystallized by heating in the gettering step.

  In this embodiment, the crystallization and gettering steps are performed after forming each semiconductor region. However, after the gettering step for each semiconductor film is performed as in the first embodiment, the semiconductor film is formed into a desired shape. Each semiconductor region may be formed by etching.

  Next, after an oxide film is formed on the surfaces of the third semiconductor regions 313 and 134 and the fourth semiconductor regions 311 and 312, a droplet discharge method or a laser beam direct writing apparatus is used, as shown in FIG. In this manner, the first mask 321 and the first mask 322 are formed. The first mask 321 covers all of the third semiconductor region 313 and the fourth semiconductor region 311 that will be n-channel TFTs later. On the other hand, the first mask 322 covers a part of the third semiconductor region 134 to be a p-channel TFT later. At this time, the first mask 322 is preferably narrower than the channel length of a p-channel TFT to be formed later.

  Next, a Group 3 element (Group 13 element, hereinafter referred to as an acceptor element 323) is added to the exposed portion of the third semiconductor region 134 to form a p-type impurity region 324. At this time, the region covered with the first mask 322 remains as the n-type impurity region 325. At this time, the p-type impurity region can be formed by adding an acceptor element so that the concentration is 2 to 10 times that of the third semiconductor region 134 to be the n-type impurity region.

  FIG. 20 shows a profile of the impurity element in the p-type impurity region.

FIG. 20A shows a profile of each element when an acceptor element is added after forming a second semiconductor film having an n ⁻ region concentration and an n ⁺ region concentration by a CVD method. The donor-type element profile 150a shows the first concentration and the second concentration, as in FIG. The acceptor-type element profile 603 has a high concentration in the vicinity of the surface of the second semiconductor film, and the concentration decreases as it approaches the fourth semiconductor region 312. A region having an acceptor type element having a concentration of 2 to 10 times that of the donor type element contained in the n ⁺ region is denoted as p ⁺ region 602a, and an acceptor type element having a concentration of 2 to 10 times that of the donor type element in the n − region is designated. A region having the same is indicated as a p-region 602b.

In FIG. 20B, a semiconductor film having a state selected from an amorphous semiconductor, a SAS, a microcrystalline semiconductor, and a crystalline semiconductor is formed, and the semiconductor is formed by an ion doping method or an ion implantation method. A profile of each element when an acceptor element is added after forming a second semiconductor film having an n ⁻ region concentration and an n ⁺ region concentration by adding a donor element to the film is shown. The donor-type element profile 150b is the same as the donor-type element profile 150a of FIG. The acceptor-type element profile 613 is similar to the acceptor-type element profile 603 in FIG. A region having an acceptor type element having a concentration of 2 to 10 times that of the donor type element contained in the n ⁺ region is indicated as p ⁺ region 612a, and an acceptor type element having a concentration of 2 to 10 times that of the donor type element in the n − region is indicated. The region having this is indicated as p-region 612b.

  Note that in the second semiconductor film containing the donor element, a rare gas element, typically argon, is added, whereby distortion of the crystal lattice is formed. Can be gettered.

  Next, after the first masks 321 and 322 are removed, the third semiconductor region 313 and the third semiconductor region 134 to which one acceptor element is added are heated to activate the impurity element. As a heating method, LRTA, GRTA, furnace annealing, or the like can be used as appropriate. Here, heating is performed at 550 degrees for 1 hour.

  Next, as shown in FIG. 13C, the second conductive layers 331 and 332 are formed as in the first embodiment. Next, a mask 333 is formed, and as illustrated in FIG. 13D, fifth semiconductor regions 343 and 344 functioning as a source region and a drain region and third conductive layers 351 and 352 are formed. Next, after the mask 333 is removed, a passivation film is preferably formed over the surfaces of the third conductive layers 351 and 352 and the fifth semiconductor regions 343 and 344.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. In addition, it is possible to form a CMOS that can be driven at a lower voltage than a drive circuit formed of a single channel TFT. Furthermore, since an acceptor element (eg, boron) has a smaller atomic radius than a donor element (eg, phosphorus), the acceptor element is added to the semiconductor film at a relatively low acceleration voltage and concentration. Is possible. In this embodiment, since only the acceptor element is added to the semiconductor film, it can be manufactured in a shorter time and with less energy compared to the conventional CMOS circuit manufacturing process, resulting in lower cost. Is possible.

  Further, the present embodiment can be applied to any one of the first to eighth embodiments.

(Embodiment 14)
In this embodiment, an n-channel TFT and a p-channel manufacturing process including a crystalline semiconductor film formed by a gettering process different from that in Embodiment 13 will be described with reference to FIGS.

  In accordance with Embodiment Mode 1, first conductive layers 301 and 302 are formed over the substrate 101, and a first insulating film 123 is formed. Next, after a layer containing a catalytic element is formed and a first semiconductor film is formed, an insulating film having a thickness of several nm is formed on the surface of the first semiconductor film. Next, a first mask is formed using a droplet discharge method or a laser beam direct writing apparatus, and the first crystalline semiconductor film is etched into a desired shape, so that the first semiconductor regions 401 and 402, One catalytic element region 125a, 125b is formed. In FIG. 14, the insulating films 123a, 123b, and 123c shown in Embodiment Mode 1 are representatively shown as the first insulating film 123.

  Next, as shown in FIG. 14B, after the second masks 403 and 404 are formed over the first semiconductor regions 401 and 402 by using a droplet discharge method or a laser beam direct writing apparatus, A donor-type element 405 is added to the exposed portion of the first semiconductor region. At this time, regions to which the donor element is added are denoted as n-type impurity regions 406 and 407. Here, phosphorus is added by an ion doping method. Note that the first semiconductor region covered with the second mask does not contain phosphorus but contains a catalytic element.

  Next, the first semiconductor region is heated to crystallize the first semiconductor regions 401 and 402, and as indicated by an arrow in FIG. 14C, the catalytic element contained in the first semiconductor region is changed. The n-type impurity regions 406 and 407 are moved to getter the catalyst element. Here, the first semiconductor region to which the catalytic element after gettering has moved is referred to as third semiconductor regions 413 and 414 serving as a source region and a drain region, and the first semiconductor region in which the metal element concentration is reduced is a channel. The formation regions 411 and 412 are shown. Note that the third semiconductor regions 413 and 414 and the fourth semiconductor regions (channel formation regions 411 and 412) are crystallized by heating in the gettering step, and are in the n-type impurity regions 406 and 407, respectively. The donor type element contained in is activated.

  Next, as shown in FIG. 14D, third masks 421 and 422 are formed using a droplet discharge method or a laser beam direct writing apparatus. The third mask 421 covers all of the channel formation region 411 to be an n-channel TFT later and the third semiconductor region 413 exhibiting n-type. On the other hand, the third mask 422 covers part or all of the channel formation region 412 to be a p-channel TFT later. At this time, the third mask 422 is preferably narrower than the channel length of a p-channel TFT to be formed later.

  Next, an acceptor element 423 is added to exposed portions of the third semiconductor region 414 and the channel formation region 412 which are n-type impurity regions, so that a p-type impurity region 424 is formed. At this time, the p-type impurity region can be formed by adding the acceptor-type element 423 so that the concentration is 2 to 10 times that of the third semiconductor region 414 that is the n-type impurity region.

  Next, after removing the third masks 421 and 422, the third semiconductor region 413 and the p-type impurity region 424, which are n-type impurity regions, are heated to activate the impurity element. As a heating method, LRTA, GRTA, furnace annealing, or the like can be used as appropriate. Here, heating is performed at 550 degrees for 1 hour.

  Next, as shown in FIG. 14E, fifth conductive layers 341 and 342 are formed as in the first embodiment. At this time, part of the channel formation regions 411 and 412 may be etched. Next, a passivation film is preferably formed over the surfaces of the fifth conductive layers 341 and 342 and the channel formation regions 411 and 412.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. Further, since the number of film formation steps can be reduced as compared with Embodiment Mode 3, throughput can be improved.

  Note that the present embodiment can be applied to any one of the first to eighth embodiments.

(Embodiment 15)
In this embodiment, a step of forming an n-channel TFT and a p-channel TFT on the same substrate using the crystalline semiconductor film subjected to the gettering step using Embodiment Mode 12 is formed using FIG.

  First conductive layers 301 and 302 are formed over the substrate 101 in accordance with the steps of Embodiment Mode 1. Next, according to the process of Embodiment 12, a first insulating film 123, a layer containing a catalytic element, a first semiconductor film, and a second semiconductor film containing a rare gas element are formed. Next, the first semiconductor film and the second semiconductor film are heated by a method similar to that in Embodiment 1, and the first semiconductor film is crystallized as indicated by an arrow in FIG. The crystalline semiconductor film 501 is formed, and the catalytic element contained in the first crystalline semiconductor film 501 is moved to the second semiconductor film to getter the catalytic element. A first crystalline semiconductor film in which the catalytic element is gettered is denoted by 501. Further, since the second semiconductor film to which the catalytic element after gettering has moved is also crystallized in the same manner, it is referred to as a second crystalline semiconductor film 502. In FIG. 15, the insulating films 123a, 123b, and 123c shown in Embodiment Mode 1 are representatively shown as the first insulating film 123.

  Next, as shown in FIG. 15B, after the second crystalline semiconductor film 502 is etched, an insulating film having a thickness of several nm is formed on the surface of the first crystalline semiconductor film 501. Next, by using a droplet discharge method or a laser beam direct writing apparatus, a first mask is formed and the second crystalline semiconductor film is etched to form first semiconductor regions 511 and 512. Next, second masks 513 and 514 are formed using a droplet discharge method or a laser beam direct writing apparatus. The second mask 513 covers a portion that later becomes a channel formation region of the n-channel TFT. On the other hand, the second mask 514 covers the entire first semiconductor region 512 that will later become a p-channel TFT. Next, a donor-type element 515 is added to the exposed portion of the first semiconductor region 511. At this time, a region to which the donor element 515 is added is referred to as an n-type impurity region 516. The region covered with the second mask 513 functions as a channel formation region 517.

  Next, after removing the second masks 513 and 514, new third masks 521 and 522 are formed. The third mask 521 covers the entire channel formation region 517 to be an n-channel TFT later and the third semiconductor region (n-type impurity region 516) exhibiting n-type. On the other hand, the third mask 522 covers a region to be a channel formation region of the p-channel TFT later.

  Next, an acceptor element 523 is added to the exposed portion of the first semiconductor region 512 to form a p-type impurity region 524. Further, the region covered with the third mask 522 functions as a channel formation region 525. Next, after removing the third masks 521 and 522, the n-type impurity region 516 and the p-type impurity region 524 are heated to activate the impurity element. As a heating method, LRTA, GRTA, furnace annealing, or the like can be used as appropriate.

  Next, as illustrated in FIG. 15D, fifth conductive layers 341 and 342 are formed as in Embodiment 1. At this time, part of the channel formation regions 517 and 525 may be etched. Next, it is preferable to form a passivation film over the surfaces of the fifth conductive layers 341 and 342 and the channel formation regions 517 and 525.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained.

  Note that the present embodiment can be applied to any one of the first to eighth embodiments.

(Embodiment 16)
In this embodiment, a process of forming an n-channel TFT and a p-channel TFT on the same substrate using a modification of Embodiment 13 is formed using FIG.

  In accordance with Embodiment 13, as shown in FIG. 16A, third semiconductor regions 313 and 314 and fourth semiconductor regions 311 and 312 having a catalytic element and a donor element are formed. Next, as shown in FIG. 16B, after forming the first mask 321, an acceptor element 323 is added to the third semiconductor region 314 to form a p-type impurity region 601. At this time, the p-type impurity region can be formed by adding the acceptor-type element 323 so that the concentration is 2 to 10 times that of the third semiconductor region 314 which is an n-type impurity region. Further, when boron is used as the acceptor element, the molecular radius is small, so that it is added deeper than the third semiconductor region. For this reason, boron is added to the upper portion of the fourth semiconductor region depending on the addition conditions. Thereafter, the third semiconductor region 313 and the p-type impurity region 601 are heated to activate the acceptor-type element and the donor-type element. Note that here, the doping conditions are controlled so that the acceptor element is not added to the fourth semiconductor region 312.

  Next, second conductive layers 331 and 332 are formed according to the fourteenth embodiment. Next, the exposed portions of the second conductive layers 331 and 332, the third semiconductor region 313, and the p-type impurity region 601 are etched using a mask so that the source region and the drain as illustrated in FIG. The fifth semiconductor regions 343 and 621 functioning as regions and the sixth semiconductor regions 345 and 622 functioning as channel formation regions can be formed. After that, a passivation film is preferably formed over the surfaces of the fifth conductive layers 341 and 342 and the sixth semiconductor regions 345 and 622.

  Through the above steps, an n-channel TFT and a p-channel TFT can be formed over the same substrate. By using the TFT formed in this embodiment, the same effect as in Embodiment 1 can be obtained. Furthermore, since only the acceptor element is added to the semiconductor film as in the thirteenth embodiment, it can be manufactured in a shorter time and with less energy compared to a conventional CMOS circuit manufacturing process. As a result, the cost can be reduced.

  Note that the present embodiment can be applied to any one of the first to eighth embodiments.

(Embodiment 17)
In this embodiment, the positional relationship between the end portions of the gate electrode, the source electrode, and the drain electrode in the above embodiment, that is, the relationship between the width of the gate electrode and the channel length is described with reference to FIGS. To do.

  In FIG. 17A, the end portions of the source electrode and the drain electrode are overlapped on the gate electrode 202 by z1. Here, a region where the gate electrode 202 overlaps with the source electrode and the drain electrode is referred to as an overlap region. That is, the width y1 of the gate electrode is larger than the channel length x1. The width z1 of the overlap region is represented by (y1-x1) / 2. An n-channel TFT having such an overlap region preferably has an n + region and an n− region as shown in FIG. 1D between the source and drain electrodes and the semiconductor region. With this structure, the effect of relaxing the electric field is increased, and hot carrier resistance can be increased.

  In FIG. 17B, the end portion of the gate electrode 202 is aligned with the end portions of the source electrode and the drain electrode. That is, the gate electrode width y2 is equal to the channel length x2.

  In FIG. 17C, the gate electrode 202 is separated from the ends of the source and drain electrodes by z3. Here, a region where the gate electrode 202 is separated from the source electrode and the drain electrode is referred to as an offset region. That is, the width y3 of the gate electrode is smaller than the channel length x3. The width z3 of the offset area is represented by (x3-y3) / 2. Since the TFT having such a structure can reduce off-state current, contrast can be improved when the TFT is used as a switching element of a display device.

  In FIG. 18A, the width y4 of the gate electrode is larger than the channel length x4. In addition, the first end of the gate electrode 202 and the one end of the source or drain electrode coincide with each other, and the second end of the gate electrode 202 and the other end of the source or drain electrode are z4. Only overlap. The width z4 of the overlap region is represented by (y4-x4).

  In FIG. 18B, the width y5 of the gate electrode is larger than the channel length x5. In addition, the first end portion of the gate electrode 202 and one end portion of the source electrode or the drain electrode coincide with each other, and the second end portion of the gate electrode 202 and the other end portion of the source electrode or the drain electrode correspond to z5. Just away. The width z5 of the offset area is represented by (x5-y5). The electrode whose gate electrode 202 matches the first end is used as the source electrode, and the electrode having the offset region is used as the drain electrode, whereby electric field relaxation in the vicinity of the drain electrode can be achieved.

  Further, a TFT having a so-called multi-gate structure in which the semiconductor region covers a plurality of gate electrodes may be used. A TFT having such a structure can also reduce off-state current.

  It should be noted that this embodiment can be applied to any one of Embodiments 1 to 16.

(Embodiment 18)
In the above embodiment, the source electrode and the drain electrode having end portions perpendicular to the surface of the channel formation region are shown; however, the structure is not limited to this. As shown in FIG. 21, it may be an end portion having an angle of more than 90 degrees and less than 180 degrees, preferably 135 to 145 degrees with respect to the surface of the channel formation region. Further, if the angle between the source electrode and the channel formation region surface is θ1, and the angle between the drain electrode and the channel formation region surface is θ2, θ1 and θ2 may be equal. It may be different. The source electrode and the drain electrode having such a shape can be formed by a dry etching method.

  Further, as shown in FIG. 22, the end portions of the source electrode and the drain electrodes 2149a and 2149b may have curved surfaces 2150a and 2150b.

  It should be noted that this embodiment can be applied to any one of Embodiments 1 to 16.

(Embodiment 19)
In this embodiment, a semiconductor film crystallization process applicable to the above embodiment will be described with reference to FIGS.

  As shown in FIG. 23A, a catalytic element layer 2805 having a catalytic element is selectively formed by a droplet discharge method without using a mask, and then a second semiconductor film 132 containing a donor element is formed. And may be crystallized. FIG. 23B is a top view of FIG. FIG. 23D is a top view of FIG. When the first semiconductor film 124 is heated, as shown by arrows in FIGS. 23C and 23D, a direction parallel to the surface of the substrate from a contact portion between the catalytic element layer 2805 and the first semiconductor film 124 is obtained. Crystal growth occurs, and a crystalline semiconductor film 2806 is formed. At the same time, the catalytic element is gettered to the semiconductor film containing the donor element according to the direction of the arrow. Note that crystallization is not performed in a portion considerably away from the catalyst element layer 2805, and an amorphous portion 2807 remains.

  Thus, crystal growth in a direction parallel to the substrate is referred to as lateral growth or lateral growth. Since large crystal grains can be formed by lateral growth, a TFT having higher mobility can be formed.

  It should be noted that this embodiment can be applied to any of Embodiments 1 to 18.

  Next, a method for manufacturing an active matrix substrate and a liquid crystal display device including the active matrix substrate will be described with reference to FIGS. 24 to 26 are longitudinal sectional views of the active matrix substrate, schematically showing the drive circuit portion A-A ′ and the pixel portion B-B ′.

  As shown in FIG. 24A, a first conductive film with a thickness of 100 to 200 nm is formed over a substrate 800. Here, a glass substrate is used as the substrate 800, and an indium oxide film containing silicon oxide with a thickness of 150 nm is formed as a first conductive film over the surface by a sputtering method. Next, a photosensitive material is discharged or applied onto the first conductive film, and the photosensitive material is exposed and developed using a laser beam direct writing apparatus to form a first mask. Next, the first conductive film is etched using the first mask to form first conductive layers 801 to 804. Here, the indium oxide film containing silicon oxide is etched by a wet etching method to form an indium oxide layer containing silicon oxide which is the first conductive layers 801 to 804. Note that the first conductive layers 801 to 803 function as a gate electrode, and the first conductive layer 804 functions as a connection portion of the gate electrode.

  Next, a first insulating film is formed over the surface of the substrate 800 and the first conductive layers 801 to 804. Here, as the first insulating films 805 and 806, a silicon nitride film with a thickness of 50 nm to 100 nm and a silicon oxynitride film (SiON (O> N) with a thickness of 50 to 100 nm are stacked by a CVD method. Note that the first insulating film functions as a gate insulating film, and at this time, it is preferable that the silicon nitride film and the silicon oxynitride film be continuously formed only by switching the source gas without being released to the atmosphere. As in the first embodiment, a three-layer structure may be used.

  Next, a layer 808 having a catalytic element is formed by a known method such as a PVD method, a CVD method, or a vapor deposition method. Here, a solution containing 100 ppm of nickel catalyst is applied by spin coating.

  Next, as illustrated in FIG. 24B, an amorphous semiconductor film 807 with a thickness of 10 to 100 nm is formed. Here, an amorphous silicon film with a thickness of 100 nm is formed by a CVD method. Next, a channel doping step of adding a p-type or n-type impurity element at a low concentration to a region to be a channel region of the subsequent TFT is performed over the entire surface or selectively. Next, a semiconductor film 812 containing a donor-type element with a thickness of 100 nm is formed. Here, an amorphous silicon film containing phosphorus is formed using silane gas and 0.5% phosphine gas (flow ratio silane / phosphine is 10/17).

  Next, the amorphous semiconductor film 807 is heated to form a crystalline semiconductor film 813 as shown in FIG. Here, using an electric furnace, the semiconductor film is dehydrogenated by heating at 500 ° C. for 1 hour, and then heated at 550 ° C. for 4 hours to form a crystalline silicon film containing nickel.

  By this heating, the catalyst element moves to the semiconductor film 812 containing the donor type element and is gettered, and the donor type element is activated. That is, the catalyst element in the crystalline semiconductor film containing the catalyst element is moved to the semiconductor film 812 containing the donor element. A crystalline semiconductor film in which the concentration of the catalytic element is reduced at this time is indicated by reference numeral 813 in FIG. Here, a crystalline silicon film is formed. In addition, the semiconductor film containing the donor element to which the catalyst element has moved also becomes a crystalline semiconductor film 814 by heating. That is, a crystalline semiconductor film containing a catalytic element and a donor element is obtained. This is indicated by 814 in FIG. Here, a crystalline silicon film containing nickel and phosphorus is formed.

  Next, as illustrated in FIG. 25A, the crystalline semiconductor film 814 and the crystalline semiconductor film 813 containing a catalyst element and a donor-type element are etched into a desired shape using second masks 815 to 817. . The second masks 815 to 817 can be formed by dropping and drying an organic resin by a droplet discharge method. Further, similarly to the first mask, the photosensitive material can be formed by exposure and development with a laser beam direct drawing apparatus. Here, the second masks 815 to 817 are formed by selectively discharging polyimide by a droplet discharge method, followed by drying and baking. The etched crystalline semiconductor film containing the catalyst element and the donor element becomes the first semiconductor regions 824 to 826 shown in FIG. 25B, and the etched crystalline semiconductor film 813 becomes the second semiconductor region 821. To 823.

  Next, in the driver circuit, a part of the first insulating films 805 and 806 is etched using a third mask in order to connect the gate electrode and the source electrode or the drain electrode of some TFTs. A contact hole 850 as shown in FIG. 29 is formed. Note that fourth conductive layers 831 to 833 formed later are indicated by broken lines. As the third mask, a formation method similar to that of the first mask or the second mask can be used as appropriate. A resistor can be formed by connecting the first conductive layer 802 functioning as a gate electrode to the fourth conductive layer 833 functioning as a source electrode or a drain electrode, which is formed later, through the contact hole. Thus, an inverter can be formed by connecting to adjacent TFTs.

  Next, as illustrated in FIG. 25B, second conductive layers 827 and 828 having a thickness of 500 to 1000 nm are formed on the surfaces of the first semiconductor regions 824 to 826 and the second semiconductor regions 821 to 823. Here, an Ag paste is discharged by a droplet discharge method and baked to form a third conductive layer.

  Next, a photosensitive material 829 is applied or ejected, the photosensitive material is exposed and developed using a laser beam direct writing apparatus to form a fourth mask, and then the third conductive layer is etched. As shown in FIG. 25C, fourth conductive layers 831 to 836 functioning as a source electrode, a source wiring, and a drain electrode are formed. In this step, the third conductive layer is divided to form a source electrode and a drain electrode, and etching is performed so that the width of the source wiring or the drain wiring is narrowed, whereby a liquid crystal display device to be formed later It is possible to increase the aperture ratio. Here, a positive photosensitive material is used as the photosensitive material 829, and the fourth mask is formed by irradiation with laser light 830.

  Next, the first semiconductor regions 824 to 826 are etched while leaving the fourth mask, so that source and drain regions 837 to 843 are formed. At this time, part of the second semiconductor regions 821 to 823 is also etched. The etched third semiconductor regions 844 to 846 function as channel formation regions.

  Next, after removing the fourth mask, a second insulating film 851 and a third insulating film 852 are formed over the surface of the fourth conductive layer and the third semiconductor region. Here, a 150-nm-thick silicon oxynitride film (SiON (O> N) containing hydrogen is formed by a CVD method as the second insulating film, and a 200-nm-thick silicon nitride film is formed as the third insulating film. The silicon nitride film functions as a protective film that blocks impurities from the outside.

  Next, the third semiconductor regions 844 to 846 are heated and hydrogenated. Here, by performing heating at 410 ° C. for 1 hour in a nitrogen atmosphere, hydrogen contained in the second insulating film 851 is added to the third semiconductor regions 844 to 846 and hydrogenated.

  Through the above steps, the pixel portion BB ′ having the n-channel TFT 863 having the driving circuit AA ′ formed by the n-channel TFTs 861 and 862 and the first conductive layer 803 functioning as a double gate electrode. And an active matrix substrate of a liquid crystal display device. In this embodiment, since the drive circuit is formed of n-channel TFTs, it is not necessary to form p-channel TFTs, and the number of processes can be reduced. Note that the driver circuit and the pixel TFT may be configured using only the p-channel TFT instead of the n-channel TFT.

  Next, as illustrated in FIG. 26A, a fourth insulating film 871 is formed over the third insulating film 852. Here, the fourth insulating film 871 is formed by applying and baking acrylic. Next, after a fifth mask is formed over the fourth insulating film 871, the fourth insulating film 871, the third insulating film 852, the second insulating film 851, and the first insulating films 805 and 806 are formed. Etching is performed to expose part of the first conductive layer 804 to be a connection portion of the gate electrode. Next, a fifth conductive layer 872 that functions as a gate wiring connected to the first conductive layer 804 to be a connection portion of the gate electrode is formed. Here, after the Ag paste is discharged and fired by a droplet discharge method, a part of the Ag paste is etched using a mask formed by a laser beam direct writing apparatus to reduce the wiring width, and the fifth conductive Layer 872 is formed.

  Next, a fifth insulating film 873 is formed. The fifth insulating film 873 can be formed using a material similar to that of the fourth insulating film as appropriate. Here, acrylic is used for the fifth insulating film 873. Next, after a sixth mask is formed over the fifth insulating film 873, the fifth insulating film 873 to the second insulating film 851 are etched to expose part of the fourth conductive layer 836. .

  Next, a sixth conductive layer 874 having a thickness of 100 to 300 nm is formed so as to be in contact with the fourth conductive layer 836. As a material for the sixth conductive layer 874, a light-transmitting conductive film or a reflective conductive film can be given. As a material for the light-transmitting conductive film, indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc oxide added with gallium (GZO), indium tin oxide containing silicon oxide, or the like Is mentioned. In addition, as a material for the conductive film having reflectivity, a metal such as aluminum (Al), titanium (Ti), silver (Ag), and tantalum (Ta), or a concentration less than the stoichiometric composition ratio with the metal is used. Examples thereof include a metal material containing nitrogen, or titanium nitride (TiN) or tantalum nitride (TaN) which are nitrides of the metal. As a method for forming the sixth conductive layer 874, a droplet discharge method, a coating method, a sputtering method, an evaporation method, a CVD method, or the like is used as appropriate. Note that when a coating method, a sputtering method, a vapor deposition method, a CVD method, or the like is used, a conductive layer is formed by etching a conductive film after forming a mask by a droplet discharge method, exposure using a laser beam direct drawing apparatus, or the like. To do. Here, indium tin oxide (ITO) containing silicon oxide with a thickness of 110 nm is formed by a sputtering method, and etched into a desired shape to form a sixth conductive layer 874 that functions as a pixel electrode.

  Next, as illustrated in FIG. 26B, an insulating film is formed by a printing method or a spin coating method so as to cover the fifth insulating film 873, and an alignment film 881 is formed by rubbing. Note that the alignment film 881 can be formed at a low temperature by forming the alignment film 881 by oblique deposition, and the alignment film 881 can be formed over a plastic having low heat resistance.

  A second pixel electrode (counter electrode) 883 and an alignment film 884 are formed over the counter substrate 882. Next, a closed loop sealing material is formed over the counter substrate 882. At this time, the sealing material is formed in a region around the pixel portion by using a droplet discharge method. Next, a liquid crystal material is dropped inside the closed loop formed of the sealing material by a dispenser type (dropping type).

  A filler may be mixed in the sealing material, and a color filter, a shielding film (black matrix), or the like may be formed on the counter substrate 882.

  Next, the counter substrate 882 provided with the alignment film 884 and the second pixel electrode (counter electrode) 883 is bonded to the active matrix substrate in a vacuum, and ultraviolet curing is performed, so that a liquid crystal filled with a liquid crystal material is obtained. Layer 885 is formed. Note that as a method for forming the liquid crystal layer 885, a dip method (pumping method) in which a liquid crystal material is injected using a capillary phenomenon after the counter substrate is attached can be used instead of the dispenser method (dropping method).

  Through the above process, a liquid crystal display panel can be manufactured. Note that a protection circuit for preventing electrostatic breakdown, typically a diode or the like, may be provided between the connection terminal and the source wiring (gate wiring) or in the pixel portion. In this case, the TFT can be manufactured in the same process as the above TFT, and can be operated as a diode by connecting the gate wiring layer of the pixel portion and the drain or source wiring layer of the diode.

  Through the above process, a liquid crystal display device can be formed. Note that any of Embodiment Modes 1 to 19 can be applied to this example.

  Next, in Example 1, a manufacturing method of an active matrix substrate having a driver circuit formed of a CMOS circuit and a liquid crystal display device having the active matrix substrate will be described with reference to FIGS. FIG. 30 is a plan view of a drive circuit for the active matrix substrate. FIG. 27 and FIG. 28 schematically show the longitudinal cross-sectional structures of the driver circuit portion A-A ′ and the pixel portion B-B ′.

  Through steps similar to those in Embodiment 1, as shown in FIG. 27A, first conductive layers 801 to 804 functioning as gate electrodes, first insulating films 805 and 806, and a first semiconductor are formed over a substrate 800. Regions 824 to 826 and second semiconductor regions 821 to 823 are formed. Next, a mask 891 is formed in a region to be a later n-channel TFT. Here, polyimide is discharged by a droplet discharge method and dried to form a mask 891 that covers the first semiconductor regions 824 and 826 and the second semiconductor regions 821 and 823 to be n-channel TFTs later. .

  Next, an acceptor element 892 is added to the first semiconductor region 825 to be a p-channel TFT later, so that a p-type semiconductor region 893 is formed as shown in FIG.

  After that, fourth conductive layers 831 to 836 functioning as a source electrode, a source wiring, and a drain electrode are formed by a process similar to that in Embodiment 1 (FIG. 27C). In addition, source and drain regions 837 to 843 and third semiconductor regions 844 to 846 functioning as channel formation regions are formed. A top view at this time is shown in FIG. In addition, after the second insulating film 851 and the third insulating film 852 are formed, the third semiconductor regions 844 to 846 are heated and hydrogenated.

  Next, as shown in FIG. 28A, after the fourth insulating film 871 is formed, a part of the first conductive layer 804 functioning as the gate electrode is exposed, connected to the gate electrode, and gate wiring A fifth conductive layer functioning as is formed. Thereafter, a fifth insulating film 873 is formed in the same manner as in Example 1, and then a sixth conductive layer 874 connected to the fourth conductive layer 836 is formed.

  Through the above steps, the driver circuit AA ′ formed with a CMOS circuit of an n-channel TFT 896 and a p-channel TFT 897 as shown in FIG. 28A and the first conductive layer 803 functioning as a double gate are formed. An active matrix substrate of a liquid crystal display device including the pixel portion BB ′ including the n-channel TFT 863 can be formed.

  Thereafter, a liquid crystal display device as shown in FIG. 28B can be formed through the same steps as in the first embodiment.

  In this embodiment, the appearance of a liquid crystal display device panel, which is one embodiment of the semiconductor device of the present invention, will be described with reference to FIG. FIG. 31A is a top view of a panel in which a space between the first substrate 1600 and the second substrate 1604 is sealed with the first sealant 1605 and the second sealant 1606. FIG. FIG. 31B corresponds to a cross-sectional view taken along lines AA ′ and BB ′ in FIG. In addition, the active matrix substrate formed in Embodiment 1 or 2 can be used for the first substrate 1600.

  In FIG. 31A, 1602 indicated by a dotted line is a pixel portion, and 1603 is a scanning line driver circuit. Reference numeral 1601 indicated by a solid line is a signal line (gate line) drive circuit. In this embodiment, the pixel portion 1602 and the scan line driver circuit 1603 are in a region sealed with a first sealant and a second sealant. Reference numeral 1601 denotes a signal line (source line) driver circuit, and a chip-like signal line driver circuit is provided over the first substrate 1600.

  Reference numeral 1600 denotes a first substrate, 1604 denotes a second substrate, and 1605 and 1606 denote a first sealing material and a second sealing material each containing a gap material for maintaining a space between the sealed spaces. is there. The first substrate 1600 and the second substrate 1604 are sealed with a first sealant 1605 and a second sealant 1606, and a liquid crystal material is filled therebetween.

  Next, a cross-sectional structure is described with reference to FIG. A driver circuit and a pixel portion are formed over the first substrate 1600 and have a plurality of semiconductor elements typified by TFTs. A color filter 1621 is provided on the surface of the second substrate 1604. A scan line driver circuit 1603 and a pixel portion 1602 are shown as driver circuits. Note that the scan line driver circuit 1603 is formed with a circuit including an n-channel TFT 1612. Note that the drive circuit may be formed of a CMOS circuit as in the second embodiment.

  In this embodiment, the scanning line driving circuit and the TFT of the pixel portion are formed on the same substrate. For this reason, the volume of the display device can be reduced.

  A plurality of pixels are formed in the pixel portion 1602, and a liquid crystal element 1615 is formed in each pixel. The liquid crystal element 1615 is a portion where the first electrode 1616, the second electrode 1618, and the liquid crystal material 1619 filled therebetween overlap. A first electrode 1616 included in the liquid crystal element 1615 is electrically connected to the pixel driving TFT 1611 through a wiring 1617. The gate electrode connection portion 1625 is connected to the gate wiring 1626 through a contact hole. Although the first electrode 1616 is formed after the gate wiring 1626 is formed here, the gate wiring 1626 may be formed after the first electrode 1616 is formed. The second electrode 1618 of the liquid crystal element 1615 is formed on the second substrate 1604 side. In addition, alignment films 1630 and 1631 are formed on the surface of each pixel electrode.

  Reference numeral 1622 denotes a columnar spacer, which is provided to control the distance (cell gap) between the first electrode 1616 and the second electrode 1618. The insulating film is formed by etching into a desired shape. A spherical spacer may be used. Various signals and potentials supplied to the signal line driver circuit 1601 or the pixel portion 1602 are supplied from the FPC 1609 through the connection wiring 1623. Note that the connection wiring 1623 and the FPC 1609 are electrically connected to each other with an anisotropic conductive film 1627 or an anisotropic conductive resin. Note that a conductive paste such as solder may be used instead of the anisotropic conductive film or the anisotropic conductive resin.

  Although not illustrated, a polarizing plate is fixed to one or both surfaces of the first substrate 1600 and the second substrate 1604 with an adhesive. Note that a retardation plate may be provided in addition to the polarizing plate.

  In this embodiment, the structure of the scanning line input terminal portion and the signal line input terminal portion provided in the peripheral portion of the substrate will be described with reference to FIG. 37 (A), (C) and (E) are plan views of the periphery of the substrate, respectively, and FIGS. 37 (B), (D) and (F) are FIGS. 37 (A) and (C), respectively. It is the longitudinal cross-sectional view of KL and MN of (E). In addition, KL shows the longitudinal cross-sectional view of a scanning line input terminal part, and MN shows the longitudinal cross-sectional view of a signal line input terminal part.

  As shown in FIG. 37A and FIG. 37B, the first substrate 11 and the second substrate 21 are sealed with a sealing material 20, and a liquid crystal material 27 is provided inside them. Is filled. In addition, a pixel portion in which the pixel electrode 19 and the pixel TFT 1 are arranged is formed inside the sealing material.

  In FIG. 37 (A) and FIG. 37 (B), the scanning line input terminal 13 and the signal line input terminal 26 are formed by the same process as the gate electrode 12 of the pixel TFT1. The scanning line input terminal 13 is connected to each gate electrode via a gate wiring 17 formed on the first interlayer insulating film 16. The signal line input terminal 26 is connected to the source line 14.

  The pixel electrode 19 is formed on the second interlayer insulating film 18 formed on the first interlayer insulating film 16. Note that the drain electrode 15 is connected via the first interlayer insulating film 16 and the second interlayer insulating film 18.

  The scanning line input terminal 13 and the signal line input terminal 26 are connected to the FPCs 24 and 25 via connection layers 22 and 23, respectively. In FIG. 37A, the connection layers 22 and 23 and the FPCs 24 and 25 are indicated by broken lines.

  In FIG. 37C and FIG. 37D, the scanning line input terminal 33 is formed in the same process as the source wiring 14, and the signal line input terminal is a part of the source wiring 14. That is, each input terminal is formed simultaneously with the source wiring 14. The scanning line input terminal 33 and the gate electrode 12 are connected by a gate wiring 17 formed on the first interlayer insulating film 16.

  Other structures are similar to those in FIGS. 37A and 37B.

  In FIGS. 37E and 37F, the scanning line input terminal is a part of the gate wiring 43, and the signal line input terminal 44 is formed at the same time as the gate wiring 43. That is, each input terminal is formed simultaneously with the gate wiring 43. The signal line input terminal 44 is formed on the exposed source wiring 14 after the first interlayer insulating film formed on the source wiring 14 is removed.

  Other structures are similar to those in FIGS. 37A and 37B.

  Note that although this example is described using the structure of the TFT shown in Embodiment Mode 1, it can be applied to Embodiment Modes 2 to 19 as appropriate.

  An example of a protection circuit included in the semiconductor device of the present invention will be described. The protection circuit is composed of one or a plurality of elements selected from a TFT, a diode, a resistance element, a capacitance element, and the like, and the configurations and operations of some protection circuits will be described below. First, a configuration of an equivalent circuit diagram of a protection circuit arranged between an external circuit and an internal circuit and corresponding to one input terminal will be described with reference to FIG. The protection circuit illustrated in FIG. 38A includes P-type TFTs 7220 and 7230, capacitor elements 7210 and 7240, and a resistance element 7250. The resistance element 7250 is a two-terminal resistor, and an input voltage Vin (hereinafter referred to as Vin) is applied to one end, and a low potential voltage VSS (hereinafter referred to as VSS) is applied to the other end.

  The protection circuit shown in FIG. 38B is an equivalent circuit diagram in which P-type TFTs 7220 and 7230 are substituted with diodes 7260 and 7270 having rectifying properties. The protection circuit shown in FIG. 38C is an equivalent circuit diagram in which P-type TFTs 7220 and 7230 are substituted with TFTs 7350, 7360, 7370, and 7380. Further, as a protection circuit having a different structure from the above, the protection circuit illustrated in FIG. 38D includes resistors 7280 and 7290 and an N-type TFT 7300. The protection circuit illustrated in FIG. 38E includes resistors 7280 and 7290, a P-type TFT 7310, and an N-type TFT 7320. Note that the element forming the protection circuit is preferably formed using an amorphous semiconductor with excellent withstand voltage. This embodiment can be freely combined with the above embodiment modes.

  In this embodiment, mounting of a driver circuit on the liquid crystal panel shown in the above embodiment will be described with reference to FIG.

  As shown in FIG. 32A, a signal line driver circuit 1402 and scan line driver circuits 1403a and 1403b are mounted around the pixel portion 1401. In FIG. 32A, as a signal line driver circuit 1402 and scanning line driver circuits 1403a and 1403b, a mounting method using a known anisotropic conductive adhesive and anisotropic conductive film, a COG method, wire bonding The IC chip 1405 is mounted on the substrate 1400 by a method, a reflow process using a solder bump, or the like. Here, the COG method is used. Then, an IC chip and an external circuit are connected via an FPC (flexible printed circuit) 1406.

  Note that a part of the signal line driver circuit 1402, for example, an analog switch may be integrally formed on the substrate, and the other part may be separately mounted using an IC chip.

  As shown in FIG. 32B, in the case where a semiconductor element typified by a TFT such as a SAS or a crystalline semiconductor is formed, the pixel portion 1401 and the scan line driver circuits 1403a and 1403b are integrally formed on the substrate. In some cases, the signal line driver circuit 1402 or the like is separately mounted as an IC chip. In FIG. 32B, an IC chip 1405 is mounted on a substrate 1400 as a signal line driver circuit 1402 by a COG method. Then, the IC chip and an external circuit are connected through the FPC 1406.

  Note that a part of the signal line driver circuit 1402, for example, an analog switch may be integrally formed on the substrate, and the other part may be separately mounted using an IC chip.

  Further, as illustrated in FIG. 32C, the signal line driver circuit 1402 and the like may be mounted by a TAB method instead of the COG method. Then, the IC chip and an external circuit are connected through the FPC 1406. In FIG. 32C, the signal line driver circuit is mounted by a TAB method; however, the scan line driver circuit may be mounted by a TAB method.

  When the IC chip is mounted by the TAB method, a pixel portion can be provided larger than the substrate, and a narrow frame can be achieved.

  Note that a part of the signal line driver circuit 1402, for example, an analog switch may be integrally formed on the substrate, and the other part may be separately mounted using an IC chip.

  The IC chip is formed using a silicon wafer, but an IC (hereinafter referred to as a driver IC) in which an integrated circuit is formed on a glass substrate may be provided instead of the IC chip. Since an IC chip is taken out from a circular silicon wafer, the shape of the base substrate is limited. On the other hand, the driver IC has a mother substrate made of glass and has no restriction in shape, so that productivity can be improved. Therefore, the shape of the driver IC can be set freely. For example, when the length of the long side of the driver IC is 15 to 80 mm, the required number can be reduced as compared with the case where the IC chip is mounted. As a result, the number of connection terminals can be reduced, and the manufacturing yield can be improved.

  The driver IC can be formed using a crystalline semiconductor formed over a substrate, and the crystalline semiconductor is preferably formed by irradiation with continuous wave laser light. A semiconductor film obtained by irradiation with continuous wave laser light has few crystal defects and large crystal grains. As a result, a transistor having such a semiconductor film has favorable mobility and response speed, can be driven at high speed, and is suitable for a driver IC.

  In this embodiment, a display module will be described. Here, a liquid crystal module is shown as an example of a display module with reference to FIG.

  FIG. 33A is a cross-sectional view of a liquid crystal module that performs color display using a white light and a color filter.

  As shown in FIG. 33A, an active matrix substrate 1201 and a counter substrate 1202 are fixed with a sealant 1200, and a pixel portion 1203 and a liquid crystal layer 1204 are provided therebetween to form a display region. Yes.

  The colored layer 1205 is necessary for color display. In the case of the RGB method, a colored layer corresponding to each color of red, green, and blue is provided corresponding to each pixel. Optical films (polarizing plates, retardation plates, etc.) 1206 and 1207 are disposed outside the active matrix substrate 1201 and the counter substrate 1202. In addition, a protective film 1216 is formed on the surface of the optical film 1206 functioning as a polarizing plate, so that an impact from the outside is reduced.

  A wiring board 1210 is connected to a connection terminal 1208 provided on the active matrix substrate 1201 through an FPC 1209. In the wiring substrate 1210, an external circuit 1212 such as a pixel driving circuit (IC chip, driver IC, etc.), a control circuit, or a power supply circuit is incorporated.

  The cold cathode tube 1213, the reflector 1214, the optical film 1215, and the inverter (not shown) are backlight units, and these serve as light sources and project light onto the liquid crystal display panel. A liquid crystal panel, a light source, a wiring board, an FPC, and the like are held and protected by a bezel 1217.

  The liquid crystal module having such a structure includes a TN (twisted nematic) mode, an IPS (in-plane-switching) mode, an MVA (multi-domain vertical alignment) mode, an ASM (axially symmetrical aligned mode), and an ASM (axially symmetrical aligned mode). An Optical Compensated Bend mode or the like can be applied as appropriate.

  FIG. 33B illustrates a liquid crystal module using a field sequential driving method capable of performing color display without using a color filter. The field-sequential driving method uses an optical shutter with a liquid crystal panel, lights up RGB three-color backlights at high speed to display colors, and uses the limits of the temporal resolution capability of the human eye, Color display is realized by continuous color additive color mixing. As the backlight, a cold cathode tube or a diode (LED) that emits R (red), G (green), and B (blue) light can be used.

  Here, it has a so-called π-cell structure, and a display mode called OCB (Optically Compensated Bend) mode is used. The π cell structure is a structure in which the pretilt angles of liquid crystal molecules are aligned in a plane-symmetric relationship with respect to the center plane between the active matrix substrate and the counter substrate. The alignment state of the π cell structure is splay alignment when no voltage is applied between the substrates, and shifts to bend alignment when a voltage is applied. When a voltage is further applied, the bend-aligned liquid crystal molecules are aligned perpendicularly to both substrates, and light is transmitted. In the OCB mode, high-speed response that is about 10 times faster than the conventional TN mode can be realized.

  As a material filled in the liquid crystal layer 1224, a nematic liquid crystal, a smectic liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or a material obtained by mixing a plurality of these materials can be used.

  Further, in the OCB mode display, a pair of optical films (polarizing plate, retardation plate, etc.) 1206 and 1207 sandwiching the liquid crystal panel are biaxially positioned to compensate for the viewing angle dependency of retardation three-dimensionally. It is preferable to use a phase difference plate.

  Here, LEDs 1221 to 1223 that emit light respectively in R (red), G (green), and B (blue) are provided in the reflector 1214. In addition, a controller (not shown) for controlling the light emission of these LEDs is provided. In the field sequential driving method, the R, G, and B LEDs are sequentially lit in the LED lighting period TR period, TG period, and TB period, respectively. During the lighting period (TR) of the red LED, a video signal (R1) corresponding to red is supplied to the liquid crystal panel, and one red image is written on the liquid crystal panel. Also, during the green LED lighting period (TG), video data (G1) corresponding to green is supplied to the liquid crystal panel, and one green image is written on the liquid crystal panel. Further, during the lighting period (TB) of the blue LED, video data (B1) corresponding to blue is supplied to the liquid crystal display device, and one screen image of blue is written on the liquid crystal display device. One frame is formed by writing these three images.

  Note that any of Embodiment Modes 1 to 19 can be applied to this example.

  As an electronic device in which the semiconductor device or the liquid crystal display device described in the above embodiments is incorporated in a housing, a television device (also simply referred to as a television or a television receiver), a digital camera, a digital video camera, a mobile phone device (simply portable) Portable information terminals such as PDAs, portable game machines, computer monitors, computers, sound reproduction devices such as car audio, image reproduction devices equipped with recording media such as home game machines, etc. Is mentioned. A specific example will be described with reference to FIG.

  A portable information terminal illustrated in FIG. 34A includes a main body 9201, a display portion 9202, and the like. As the display portion 9202, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the liquid crystal display device which is one embodiment of the present invention, a portable information terminal capable of high-quality display can be provided at low cost.

  A digital video camera shown in FIG. 34B includes a display portion 9701, a display portion 9702, and the like. As the display portion 9701, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the liquid crystal display device which is one embodiment of the present invention, a digital video camera capable of high-quality display can be provided at low cost.

  A portable terminal illustrated in FIG. 34C includes a main body 9101, a display portion 9102, and the like. As the display portion 9102, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be applied. By using the liquid crystal display device which is one embodiment of the present invention, a portable terminal capable of high-quality display can be provided at low cost.

  A portable television device shown in FIG. 34D includes a main body 9801, a display portion 9802, and the like. As the display portion 9802, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the liquid crystal display device which is one embodiment of the present invention, a portable television device capable of high-quality display can be provided at low cost. Such a television device can be widely applied from a small one mounted on a portable terminal such as a cellular phone to a medium-sized one that can be carried and a large one (for example, 40 inches or more). .

  A portable computer shown in FIG. 34E includes a main body 9401, a display portion 9402, and the like. As the display portion 9402, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the liquid crystal display device which is one embodiment of the present invention, a portable computer capable of high-quality display can be provided at low cost.

  A television device illustrated in FIG. 34F includes a main body 9501, a display portion 9502, and the like. As the display portion 9502, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the liquid crystal display device which is one embodiment of the present invention, a television device capable of high-quality display can be provided at low cost.

  Among the electronic devices listed above, those using a secondary battery can extend the usage time of the electronic device as much as power consumption is reduced, and can save the trouble of charging the secondary battery.

  A large television shown in FIG. 35 includes a main body 9601, a display portion 9602, and the like. A wall-supporting body is provided on the back or top of the main body. FIG. 35 shows a wall-mounted television as a typical example of a large television. As shown in FIG. 35, the image can be displayed over the wall 9603. In addition, the present invention can be applied to various uses as a display medium having a particularly large area, such as an information display board at a railway station or airport, or an advertisement display board in a street. As the display portion 9602, any of those shown in Embodiments 1 to 19 and Examples 1 to 7 can be used. By using the liquid crystal display device which is one embodiment of the present invention, a portable information terminal capable of high-quality display can be provided at low cost.

  According to the present invention, a semiconductor device that functions as a wireless chip (also referred to as a wireless processor, a wireless memory, or a wireless tag) can be formed. Applications of wireless chips are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 40A), packaging containers (wrapping paper, Bottle, etc., see FIG. 40 (C)), recording medium (DVD software, video tape, etc., see FIG. 40 (B)), vehicles (bicycles, etc., see FIG. 40 (D)), personal items (bags, glasses, etc.) ), Foods, plants, animals, human bodies, clothing, daily necessities, electronic devices, etc. and goods such as luggage tags (see FIGS. 40E and 40F) for use. be able to. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like.

  The wireless chip is fixed to the article by being attached to the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin. Forgery can be prevented by providing wireless chips on banknotes, coins, securities, bearer bonds, certificates, etc. In addition, by providing wireless chips in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. The wireless chip that can be formed according to the present invention is small, thin, and lightweight because it is provided on a cover material after a thin film integrated circuit formed over a substrate is peeled off by a known peeling process, and is mounted on an article. However, the design is not impaired. Furthermore, since it has flexibility, it can be used for a bottle or pipe having a curved surface.

  Further, by applying a wireless chip that can be formed according to the present invention to an object management or distribution system, it is possible to increase the functionality of the system. For example, by reading the information recorded on the wireless chip provided on the tag with a reader / writer provided on the side of the belt conveyor, information such as the distribution process and delivery destination is read, and inspection of goods and distribution of goods Can be done easily.

  A structure of a wireless chip that can be formed according to the present invention will be described with reference to FIGS. The wireless chip is formed with a thin film integrated circuit 9303 and an antenna 9304 connected thereto. The thin film integrated circuit 9303 and the antenna 9304 are sandwiched between cover materials 9301 and 9302. The thin film integrated circuit 9303 may be bonded to the cover material with an adhesive. In FIG. 41, one of thin film integrated circuits 9303 is bonded to a cover material 9301 through an antenna 9304 and an adhesive 9305.

  The thin film integrated circuit 9303 is formed using the TFT shown in any of Embodiments 1 to 19, and then peeled off by a known peeling step and provided on the cover material. The semiconductor element used for the thin film integrated circuit 9303 is not limited to this. For example, a memory element, a diode, a photoelectric conversion element, a resistance element, a coil, a capacitor element, an inductor, or the like can be used in addition to the TFT.

  As shown in FIG. 41, an interlayer insulating film 9311 is formed over the TFT of the thin film integrated circuit 9303, and an antenna 9304 connected to the TFT through the interlayer insulating film 9311 is formed. A barrier film 9312 made of a silicon nitride film or the like is formed over the interlayer insulating film 9311 and the antenna 9304.

  The antenna 9304 is formed by discharging a droplet including a conductor such as gold, silver, or copper by a droplet discharge method, followed by drying and baking. By forming the antenna by a droplet discharge method, the number of steps can be reduced, and the cost can be reduced accordingly.

  Cover materials 9301 and 9302 are laminated films (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, etc.), papers made of fibrous materials, base films (polyester, polyamide, inorganic vapor deposition films, papers, etc.) ) And an adhesive synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.). The laminate film is laminated with the object to be processed by thermocompression bonding. When performing the laminate process, the laminate film is an adhesive layer provided on the outermost surface of the laminate film or a layer provided on the outermost layer. (Not the adhesive layer) is melted by heat treatment and bonded by pressure.

  In addition, by using an incineration-free pollution material such as paper, fiber, and carbon graphite for the cover material, the used wireless chip can be incinerated or cut. Further, wireless chips using these materials are non-polluting because they do not generate toxic gas even when incinerated.

  Note that in FIG. 41, a wireless chip is provided for the cover material 9301 through the antenna 9304 and the adhesive 9305; however, instead of the cover material 9301, a wireless chip may be attached to an article for use.

FIG. 6 is a cross-sectional view illustrating a manufacturing process of a liquid crystal display device according to the present invention. FIG. 6 is a cross-sectional view illustrating a structure of a liquid crystal display device according to the invention. 4A and 4B are a plan view and a cross-sectional view illustrating a structure of a liquid crystal display device according to the invention. 4A and 4B are a plan view and a cross-sectional view illustrating a structure of a liquid crystal display device according to the invention. 4A and 4B are a plan view and a cross-sectional view illustrating a structure of a liquid crystal display device according to the invention. 4A and 4B are a plan view and a cross-sectional view illustrating a structure of a liquid crystal display device according to the invention. 4A and 4B are a plan view and a cross-sectional view illustrating a structure of a liquid crystal display device according to the invention. 4A and 4B are a plan view and a cross-sectional view illustrating a structure of a liquid crystal display device according to the invention. Sectional drawing explaining the manufacturing process of the liquid crystal display device which concerns on this invention Sectional drawing explaining the manufacturing process of the liquid crystal display device which concerns on this invention Sectional drawing explaining the manufacturing process of the liquid crystal display device which concerns on this invention FIG. 6 is a cross-sectional view illustrating a manufacturing process of a liquid crystal display device according to the present invention. FIG. 6 is a cross-sectional view illustrating a manufacturing process of a liquid crystal display device according to the present invention. FIG. 6 is a cross-sectional view illustrating a manufacturing process of a liquid crystal display device according to the present invention. FIG. 6 is a cross-sectional view illustrating a manufacturing process of a liquid crystal display device according to the present invention. FIG. 6 is a cross-sectional view illustrating a manufacturing process of a liquid crystal display device according to the present invention. FIG. 6 is a cross-sectional view illustrating a structure of a liquid crystal display device according to the invention. FIG. 6 is a cross-sectional view illustrating a structure of a liquid crystal display device according to the invention. Sectional drawing explaining the impurity concentration of the liquid crystal display device which concerns on this invention. Sectional drawing explaining the impurity concentration of the liquid crystal display device which concerns on this invention. FIG. 6 is a cross-sectional view illustrating a structure of a liquid crystal display device according to the invention. FIG. 6 is a cross-sectional view illustrating a manufacturing process of a liquid crystal display device according to the present invention. FIG. 6 is a cross-sectional view illustrating a manufacturing process of a liquid crystal display device according to the present invention. FIG. 6 is a step view illustrating a manufacturing process of a liquid crystal display device according to the present invention. FIG. 6 is a step view illustrating a manufacturing process of a liquid crystal display device according to the present invention. FIG. 6 is a step view illustrating a manufacturing process of a liquid crystal display device according to the present invention. FIG. 6 is a step view illustrating a manufacturing process of a liquid crystal display device according to the present invention. FIG. 6 is a step view illustrating a manufacturing process of a liquid crystal display device according to the present invention. The top view explaining the connection of the drive circuit of the liquid crystal display device which concerns on this invention. The top view explaining the connection of the drive circuit of the liquid crystal display device which concerns on this invention. 4A and 4B are a plan view and a cross-sectional view illustrating a structure of a liquid crystal display panel according to the invention. FIG. 6 is a plan view illustrating a method for mounting a driving circuit of a liquid crystal display device according to the present invention. FIG. 6 illustrates a structure of a liquid crystal display module according to the present invention. 10A and 10B each illustrate an example of an electronic device. 10A and 10B each illustrate an example of an electronic device. 4A and 4B are a plan view and a cross-sectional view illustrating a structure of a liquid crystal display device according to the invention. 4A and 4B are a plan view and a cross-sectional view illustrating a structure of a peripheral portion of a liquid crystal display device according to the invention. FIG. 6 is a circuit diagram illustrating a protection circuit. 1A and 1B illustrate a laser beam direct drawing apparatus applicable to the present invention. 8A and 8B illustrate an application example of a semiconductor device of the invention. 8A and 8B illustrate an application example of a semiconductor device of the invention.

Claims (7)

Forming a gate insulating film on the first gate electrode;
Forming a catalytic element layer having a catalytic element for promoting crystallization of a semiconductor on the gate insulating film;
A first semiconductor film is formed on the catalyst based on arsenide layer,
Forming a second semiconductor film to which a first impurity element imparting n-type is added on the first semiconductor film;
Heat-treating the first semiconductor film and the second semiconductor film ;
Etching the second semiconductor film to form a first semiconductor region, and etching the first semiconductor film to form a second semiconductor region overlapping the first semiconductor region;
Forming a first source electrode and a first drain electrode on the first semiconductor region;
Etching the first semiconductor region to form a first source region and a first drain region;
The heat treatment causes the catalytic element to move from the catalytic element layer to the first semiconductor film to crystallize the first semiconductor film, and from the first semiconductor film to the second semiconductor film, the catalyst. Moving the element to crystallize the second semiconductor film;
The method for manufacturing a semiconductor device, wherein the first source region and the first drain region have crystallinity and include the catalytic element. Forming a gate insulating film on the first gate electrode;
Forming a first semiconductor film on the gate insulating film;
Forming a catalytic element layer having a catalytic element for promoting crystallization of a semiconductor on the first semiconductor film;
Forming a second semiconductor film to which a first impurity element imparting n-type is added on the first semiconductor film and the catalytic element layer;
Heat-treating the first semiconductor film and the second semiconductor film;
Etching the second semiconductor film to form a first semiconductor region, and etching the first semiconductor film to form a second semiconductor region overlapping the first semiconductor region;
Forming a first source electrode and a first drain electrode on the first semiconductor region;
Etching the first semiconductor region to form a first source region and a first drain region;
The heat treatment causes the catalytic element to move from the catalytic element layer to the first semiconductor film to crystallize the first semiconductor film, and from the first semiconductor film to the second semiconductor film, the catalyst. Moving the element to crystallize the second semiconductor film;
The method for manufacturing a semiconductor device, wherein the first source region and the first drain region have crystallinity and include the catalytic element. Forming a gate insulating film on the first gate electrode and the second gate electrode;
Forming a catalytic element layer having a catalytic element for promoting crystallization of a semiconductor on the gate insulating film;
Forming a first semiconductor film on the catalyst element layer;
Forming a second semiconductor film to which a first impurity element imparting n-type is added on the first semiconductor film;
Heat-treating the first semiconductor film and the second semiconductor film;
Etching the second semiconductor film to form a first semiconductor region and a third semiconductor region, and etching the first semiconductor film to overlap the first semiconductor region; Forming a region and a fourth semiconductor region overlapping the third semiconductor region;
Forming a first mask covering the whole of the first semiconductor region and a second mask covering a part of the third semiconductor region;
In a state where the first mask and the second mask are formed, a second impurity element imparting p-type is added to the third semiconductor region,
Removing the first mask and the second mask;
Forming a first source electrode and a first drain electrode on the first semiconductor region, and forming a second source electrode and a second drain electrode on the third semiconductor region;
Etching the first semiconductor region to form a first source region and a first drain region, and etching the third semiconductor region to form a second source region and a second drain region And
The second mask is formed between the second source region and the second drain region;
The heat treatment causes the catalytic element to move from the catalytic element layer to the first semiconductor film to crystallize the first semiconductor film, and from the first semiconductor film to the second semiconductor film, the catalyst. Moving the element to crystallize the second semiconductor film;
The first source region and the first drain region have crystallinity and contain the catalytic element, and the second source region and the second drain region have crystallinity and A manufacturing method of a semiconductor device including a catalytic element. Forming a gate insulating film on the first gate electrode and the second gate electrode;
Forming a first semiconductor film on the gate insulating film;
Forming a catalytic element layer having a catalytic element for promoting crystallization of a semiconductor on the first semiconductor film;
Forming a second semiconductor film to which a first impurity element imparting n-type is added on the first semiconductor film and the catalytic element layer;
Heat-treating the first semiconductor film and the second semiconductor film;
Etching the second semiconductor film to form a first semiconductor region and a third semiconductor region, and etching the first semiconductor film to overlap the first semiconductor region; Forming a region and a fourth semiconductor region overlapping the third semiconductor region;
Forming a first mask covering the whole of the first semiconductor region and a second mask covering a part of the third semiconductor region;
In a state where the first mask and the second mask are formed, a second impurity element imparting p-type is added to the third semiconductor region,
Removing the first mask and the second mask;
Forming a first source electrode and a first drain electrode on the first semiconductor region, and forming a second source electrode and a second drain electrode on the third semiconductor region;
Etching the first semiconductor region to form a first source region and a first drain region, and etching the third semiconductor region to form a second source region and a second drain region And
The second mask is formed between the second source region and the second drain region;
The heat treatment causes the catalytic element to move from the catalytic element layer to the first semiconductor film to crystallize the first semiconductor film, and from the first semiconductor film to the second semiconductor film, the catalyst. Moving the element to crystallize the second semiconductor film;
The first source region and the first drain region have crystallinity and contain the catalytic element, and the second source region and the second drain region have crystallinity and A manufacturing method of a semiconductor device including a catalytic element. In claim 2 or claim 4,
A method for manufacturing a semiconductor device, wherein the catalyst element layer is selectively formed. In any one of Claim 2, Claim 4, or Claim 5,
The gate insulating film is composed of a stack of a silicon nitride film and a silicon oxide film provided on the silicon nitride film,
A first step of forming the silicon nitride film by a CVD method using silane gas and ammonia gas as raw materials in a chamber;
After the first step, a second step of forming the silicon oxide film by a CVD method using silane gas and nitrogen oxide as raw materials in the chamber;
After the second step, a third step of flowing only the silane gas into the chamber without generating plasma;
After the third step, a fourth step of forming the first semiconductor film by a CVD method using silane gas as a raw material,
The method for manufacturing a semiconductor device, wherein the first to fourth steps are performed continuously. In any one of Claims 1 thru | or 6,
A manufacturing method of a semiconductor device, wherein the second semiconductor film contains a rare gas.

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