JP4573921B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device characterized by a heat treatment method for improving the interface state between a semiconductor substrate and an insulating film and the film quality of the insulating film.
[0002]
[Prior art]
With the progress of high integration and miniaturization of semiconductor integrated circuit devices in recent years, miniaturization is also required for MISFETs (metal-insulator-semiconductor FETs) constituting the semiconductor integrated circuit device, and the voltage is lowered with miniaturization. Therefore, it is necessary to reduce the thickness of the gate insulating film, but the gate insulating film is made of SiO as in the conventional MISFET.₂When a film is used, SiO₂When the film thickness is reduced to about 4 nm, it becomes difficult to maintain the uniformity of the film thickness, and in addition to the increase in leakage current and the phenomenon that impurities doped into the gate electrode penetrate into the channel region, the characteristics of MISFET are serious. Has come to have an impact.
[0003]
In order to solve such a problem, as a gate insulating film, SiO₂SiO instead of film₂Silicon nitride film (SiN) having a relative dielectric constant larger than that of the film_xFilm, stoichiometrically Si_ThreeN_FourFilm) and SiON films are being studied.
That is, since the relative dielectric constant of the SiN film or SiON film is large, SiO₂This is because equivalent gate characteristics can be obtained even if a SiN film or a SiON film having a thickness greater than that of the film is used.
[0004]
As a conventional method for producing a SiON film, N₂A method using an O gas or a method of exposing a substrate in a high-temperature nitrogen atmosphere after forming a thermal oxide film is used, but these processes are both high-temperature processes at 800 ° C. or higher. When the SiON film to be the gate insulating film is formed by such a high temperature process, the threshold voltage V_thImpurities doped in the channel region for adjustment will be redistributed in the SiN film deposition process, and the short channel effect will be deteriorated, that is, punch-through between the source and drain regions will be induced.
In addition, such a high temperature process has a problem in that the wafer diameter is warped and the processing accuracy is lowered when the wafer diameter is increased in recent years.
[0005]
In view of the problems of such a high temperature process, application of a plasma CVD (PCVD) method and a JVD (Jet Vapor Deposition) method, which are low temperature processes, has been attempted. For example, see Yale University, Jet Process Corp. Alternatively, in Motorola, it has been studied to form a SiN film of 2 to 5 nm by JVD method in terms of EOT (Equivalent Oxide Thickness), and in particular, in Motorola, 0 Application studies on .35 μm devices have been conducted and have shown good results.
Note that EOT (equivalent oxide film thickness) means that the relative dielectric constant is SiO.₂It is the film thickness of the insulating film calculated from the CV characteristics assuming that it is 3.9, the same as the film.
[0006]
Matsumura et al., One of the present inventors, has proposed a silicon-based thin film deposition method using a catalytic CVD method for low temperature processing (for example, Japanese Patent Laid-Open Nos. 8-250438 and 10). No. 83988, or Applied Physics, Vol. 66, No. 10, pp. 1094-1097, 1997), and Izumi, one of the inventors of the present invention, nitrided the surface of a substrate using a catalytic CVD apparatus. A method has been proposed (see Applied Physics Letters, Vol. 71, No. 10, pp. 1371- 1372, September, 1997).
[0007]
However, the SiN film or the SiON film formed by such a PCVD method, JVD method, or catalytic CVD method is not necessarily good in quality only by being deposited, and there is a problem that a hysteresis loop is seen in the CV characteristics. is there. The presence of a hysteresis loop in this CV characteristic means that there are a large number of active dangling bonds at the Si / SiN interface or Si / SiON interface, affecting the channel characteristics.
[0008]
Therefore, in order to improve the film quality of such a low temperature growth insulating film such as a low temperature SiON film, N at a high temperature of about 800 ° C.₂It is necessary to perform annealing in an atmosphere, and as a result, the process becomes a high temperature process as a whole.
[0009]
Furthermore, in order to improve the film quality of the low-temperature SiON film, introduction of nitrogen into the SiON film using a plasma process is also being studied. However, damage to the SiON film due to plasma or damage to the silicon substrate may occur. There are concerns.
[0010]
On the other hand, as a gate insulating film, SiO₂Even when an oxide film such as a film is used, the threshold voltage V_thIn order to prevent deterioration of the short channel effect due to redistribution of impurities doped in the channel region for adjustment, that is, punch-through between the source and drain regions, SiO 2₂It is necessary to deposit an oxide film such as a film at a low temperature. Then, as described above, Si / SiO₂A large number of active dangling bonds are generated at the interface of the film, which causes a problem of affecting channel characteristics.
[0011]
Accordingly, the present inventor has proposed a low temperature annealing method for improving the film quality of a SiN film formed at a low temperature on the premise of such circumstances, and will be described below.
First, after cleaning the surface of an n-type silicon substrate having a (100) plane as a main surface by RCA cleaning, SiH as a source gas in a state where the temperature of the n-type silicon substrate is 300 ° C. in a catalytic CVD apparatus._Four1.1 sccm, NH_ThreeThe AC pressure of 680 W is supplied from the AC power source to the tungsten catalyst body arranged so that the gas pressure in the vacuum vessel is 0.01 Torr and the distance from the n-type silicon substrate is 3.7 cm. Heat to 1800 to 1900 ° C., and the heated tungsten catalyst body_ThreeAnd SiH_FourNH by contacting_ThreeAnd SiH_FourIs decomposed to generate active species, and this active species is reacted on the surface of the n-type silicon substrate to deposit a SiN film.
[0012]
Subsequently, in the same vacuum vessel (in-situ), SiH_FourThe supply of NH_ThreeThe active species are generated under the same conditions as the film forming process except that only 50-60 sccm is supplied and the gas pressure is 0.013 Torr, and the SiN film is heat-treated in an atmosphere containing the active species, for example, for 1 hour. Thus, a modified SiN film is formed.
In this case, the active species is NH._ThreeIs composed of various radicals formed by decomposition of N, among which N radicals are the most, followed by N₂There are many radicals.
[0013]
In this case, NH_ThreeThe EOT of the SiN film before performing the catalyst annealing treatment by the process is estimated to be 4.06 nm, and the interface state density D_uIs 8.63 × 10¹¹cm^-2eV^-1Whereas NH_ThreeThe EOT of the SiN film after performing the catalyst annealing treatment by using the above is estimated to be 3.80 nm, the hysteresis characteristics are improved, and the interface state density D_uIs 3.53 × 10¹¹cm^-2eV^-1It was reduced to 1/2 or less before the treatment.
[0014]
NH_ThreeCompared to the leakage current of the SiN film having an EOT of 2.97 nm before the low temperature annealing treatment in the active species generated by decomposition of the silicon, the SiN film having the EOT of 2.78 nm after the low temperature annealing has two digits. As described above, the current density is reduced, and the withstand voltage is also improved.
[0015]
On the other hand, as another method for forming such an insulating film without high temperature process and plasma damage, annealing is performed at a temperature of 400 to 700 ° C. in a gas atmosphere activated by a catalyst after forming the insulating film by a low temperature process. It has been proposed (see, for example, JP-A-8-78695).
[0016]
In this proposal, a mesh-like catalyst is arranged in a reaction chamber in which heat treatment is performed or in a reaction chamber independent of the heat treatment, and activated by allowing the raw material gas to permeate the mesh-like catalyst. The silicon-hydrogen bond (Si-H) at the crystalline Si film / silicon oxide film interface is replaced with a silicon-nitrogen bond (Si≡N) by radicals to improve the film quality of the oxide film. The whole can be performed by a low temperature process of 700 ° C. or less.
[0017]
For example, in the above proposal, after depositing a silicon oxide film having a thickness of 20 to 150 nm, for example, 100 nm as a gate insulating film on the surface of the crystalline Si film constituting the TFT by a plasma CVD method, After annealing at 350 ° C. for 2 hours, N activated by a reduced nickel network as a catalyst at a temperature of 200 to 600 ° C.₂O is introduced into the reaction chamber, and heat treatment is performed at 400 to 700 ° C. for 1 hour, thereby reducing hydrogen in the silicon oxide film and at the interface between the silicon oxide film and the crystalline Si film by oxidation or nitridation. It is disclosed to improve the film quality and interface properties of the film.
[0018]
In the above proposal, a silicon oxide film having a thickness of 20 to 150 nm, for example, 100 nm, serving as a gate insulating film is deposited on the surface of the crystalline Si film constituting the TFT by a sputtering method, and then a platinum network serving as a catalyst. N activated by₂By performing heat treatment at 500 to 650 ° C. for 1 hour using O, hydrogen in the silicon oxide film and at the interface between the silicon oxide film and the crystalline Si film is reduced by oxidation or nitridation, so that the film quality of the silicon oxide film and It is disclosed to improve the properties of the interface.
[0019]
Furthermore, in the above proposal, a 120-nm-thick silicon oxide film serving as a gate insulating film is deposited on the surface of the crystalline Si film constituting the TFT by an ECR-CVD method, and then the particulates in which Ti serving as a catalyst is adsorbed. Alternatively, NH diluted with Ar to 1-5% by powdered silica gel_ThreeAnd the silicon oxide film is nitrided by annealing for 1 hour, and then activated by the catalyst.₂It is disclosed that the characteristics of the interface between the nitrided silicon oxide film and the crystalline Si film are improved by performing a heat treatment at 500 to 650 ° C. for 1 hour using O.
[0020]
[Problems to be solved by the invention]
However, NH using the above-mentioned catalytic CVD apparatus_ThreeIn the case of low-temperature heat treatment with active species, only the improvement of the quality of the SiN film or the improvement of the interface state is disclosed.₂There is no suggestion of improving the film quality or interface state of other insulating films such as films.
[0021]
In addition, in the case of the low temperature annealing method using the gas activated by the catalyst described in JP-A-8-78695, it is basically assumed that the film quality or interface state is improved by nitriding. The silicon oxide film deposited by the PCVD method or ECR-CVD method is heat-treated at a temperature of 400 to 700 ° C. in a separate reaction chamber equipped with a mesh-like or granular catalyst. In addition, there is a problem that a temperature of 400 ° C. or higher is required even if it is a low temperature process.
[0022]
Therefore, an object of the present invention is to modify an insulating film formed at a low temperature by low-temperature annealing, and to simplify the configuration of a manufacturing apparatus system.
[0023]
[Means for Solving the Problems]
  FIG. 1 is an explanatory view of the principle configuration of the present invention, and means for solving the problems in the present invention will be described with reference to FIG.
  See Figure 1
  (1) The present invention provides a method for manufacturing a semiconductor device,Made of siliconDeposited on substrate 1GateAfter forming the gate electrode on the oxide film, a nitrogen-containing gas is blown onto the resistance heating element 3 made of a catalyst, and at least a part of the nitrogen-containing gas is decomposed by a contact reaction between the resistance heating element 3 and the nitrogen-containing gas. In the atmosphere of active species 4 produced by decompositionGateIt is characterized by exposing an oxide film.
[0027]
  (2In addition, the present invention provides the above (1), The oxide film is made of SiO.₂Film, SiON film, or CeO₂It is one of the membranes.
[0028]
  Thus, using the active species 4 activated by the resistance heating element 3 made of a catalyst, SiO 2 is used.₂Film, SiON film, or CeO₂By annealing an oxide film such as a film, N can be introduced into the interface between the substrate 1 and the oxide film only by a low-temperature process of, for example, 300 ° C. or less. Termination can improve the interface characteristics.
  Further, by configuring the catalyst with the resistance heating element 3, the catalyst can be provided in the annealing treatment apparatus, thereby simplifying the manufacturing apparatus system.
  The substrate 1 in the present invention means a silicon substrate, a silicon deposited layer formed on the substrate, or a metal.
[0029]
  In particularBy performing the low-temperature annealing treatment in the atmosphere of the active species 4 after the formation of the gate electrode, it can also serve as a PMA (post metal annealing) step, thereby reducing the number of manufacturing steps.
[0030]
  (3In addition, the present invention provides the above (1)Or (2)InAfter the side wall oxide film is formed on the side wall of the gate electrode, the side wall oxide film is exposed to the atmosphere of the active species 4 generated again by decomposition.It is characterized by that.
[0031]
  In this way, the nitriding treatment of the interface in the atmosphere of the active species 4 is performed after the sidewall oxide film, that is, the sidewall is formed on the sidewall of the gate electrode, whereby the sidewalls on both sides of the gate electrode and the silicon substrate are formed. The characteristics of the interface can be improved, whereby the breakdown voltage can be improved.
[0032]
  (4In addition, the present invention provides the above (3), The sidewall oxide film is made of SiO.₂It is one of a film, a SiON film, or a TEOS (Tetra-Ethyl-Ortho-Silicate) -NSG (Non Doped Silicate Glass) film.
[0033]
  (5In addition, the present invention provides the above (1) To (5), The nitrogen-containing gas is any one of ammonia, hydrogen azide, nitrogen, nitrogen halide, and nitrogen oxide.
[0034]
  As described above, the nitrogen-containing gas used in the catalyst annealing step for introducing nitrogen into the interface is ammonia (NH₃), Hydrogen azide (HN3), nitrogen, NHCl₂Nitrogen halides such as N or N₂O, NO, NO₂Any of nitrogen oxides such as these may be used.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Here, each embodiment of the present invention will be described. Before describing the manufacturing process of each embodiment, a catalytic CVD apparatus used in the embodiment of the present invention will be described with reference to FIG.
See Figure 2
FIG. 2 is a conceptual configuration diagram of a catalytic CVD apparatus used in each embodiment of the present invention. A diffusion pump 13 is connected to a vacuum vessel 11 serving as a reaction chamber via a valve 12. 13, the reaction product or the unreacted raw material gas 19 is exhausted.
[0037]
A substrate holder 14 is provided at the upper center of the vacuum vessel 11, and a sample 15 held by a susceptor or the like is fixed to the substrate holder 14, and a sample is held in a recess of the substrate holder 14. A heater 16 is provided to heat the sample 15, and the temperature of the sample 15 is monitored by a thermocouple 17.
[0038]
Further, a gas supply pipe 18 having a nozzle for blowing out the source gas 19 and a tungsten catalyst body 20 are arranged so as to face the sample 15, and a shutter 23 is provided between them, AC power of about 700 W, for example, 680 W, is supplied from the AC power source 21, and the resistance heating element line temperature of the tungsten catalyst body 20 becomes a high temperature of about 1800 to 1900 ° C.
Note that the resistance heating element line temperature of the tungsten catalyst body 20 is first estimated from the temperature dependence of the electrical resistance of the coiled tungsten catalyst body 20, but through a quartz window (not shown) provided in the vacuum vessel 11. It is estimated by an electronic infrared radiation thermometer 22.
[0039]
The source gas 19 is blown onto the high-temperature tungsten catalyst body 20, and the source gas 19 and the tungsten catalyst body 20 come into contact with each other, whereby the source gas 19 is decomposed to form active species such as radicals, and the shutter 23 When the sample 15 is exposed to an atmosphere containing this active species, film formation or annealing is performed.
In this case, the substrate temperature may be increased due to heat radiation from the tungsten catalyst body 20, but when the distance between the sample 15 and the tungsten catalyst body 20 is about 5 cm, the temperature increase due to heat radiation is Since it is within several tens of degrees Celsius, there is no problem from the viewpoint of lowering the temperature (see Applied Physics, Vol. 66, No. 10, pp. 1094-1097, 1997 if necessary).
[0040]
  Next, referring to FIG. 3 and FIG.Reference example 1First, referring to FIG. 3, the present invention will be described.Reference example 1The manufacturing process will be described.
  See Fig. 3 (a)
  First, after cleaning the surface of the n-type silicon substrate 31 having the (100) plane as the main surface by RCA cleaning, the temperature of the n-type silicon substrate 31 is set to 300 ° C. in the catalytic CVD apparatus shown in FIG. In the state, SiH as the source gas 19₄33 is 1.1 sccm, NH₃32 is flowed at 50 to 60 sccm, the gas pressure in the vacuum vessel 11 is set to 0.01 Torr, and the alternating current of 680 W from the AC power source 21 is applied to the tungsten catalyst body 20 arranged so that the distance from the n-type silicon substrate 31 is 3.7 cm. Electric power was applied to heat to 1800 to 1900 ° C., and NH 3 32 and SiH were added to the heated tungsten catalyst body 20.₄NH3 32 and SiH by contacting 33₄33 is decomposed to generate active species 34 and 35, and the active species 34 and 35 are reacted on the surface of the n-type silicon substrate 31, thereby depositing an N-rich SiON film 36 having a thickness of, for example, 5 nm. Is done.
  In this case, the reason why the SiON film 36 is formed instead of the SiN film is not necessarily clear, but the O gas mixed in the piping gas or the like is not clear.₂Is presumed to be the cause.
[0041]
Refer to FIG.
Subsequently, in the same vacuum vessel 11 (in-situ), NH_Three32 and SiH_FourStop the supply of 33, H₂An active species 38 is generated under the same conditions as the film forming process except that 50 sccm of 37 is supplied and the gas pressure is 0.01 Torr, and the SiON film 36 is heat-treated, for example, for 10 minutes in an atmosphere containing the active species 38. Thus, a modified SiON film 39 is formed.
In this case, the active species 38 is H₂37 is composed of radicals formed by decomposition.
[0042]
  Next, referring to FIG.Reference example 1The effect of improving the interface state by the H2 treatment will be described.
  See Fig. 4 (a)
  FIG. 4 (a) shows H₂FIG. 5 is a diagram showing the CV characteristics of the SiON film 36 before the catalyst annealing treatment by the step S is performed, and since a hysteresis loop is seen in the CV characteristics, it is active at the interface between the n-type silicon substrate 31 and the SiON film 36. It is understood that dangling bonds and the like are generated and the interface state density is high.
[0043]
Refer to FIG.
FIG. 4B shows H₂FIG. 5 is a diagram showing the CV characteristics of the SiON film 39 after performing the catalyst annealing treatment by the GaN, and since the hysteresis loop is hardly seen in the CV characteristics, the dangling bonds are terminated by the activated hydrogen. It is understood that the interface state density is greatly reduced.
When measuring these CV characteristics, only an Al electrode is formed, and no PMA treatment is performed.
[0044]
Like this, H₂The dangling bonds at the n-type silicon substrate / SiON film interface are terminated by H by the low-temperature annealing treatment in the active species generated by decomposing the catalyst with a resistance heating element comprising a catalyst, thereby greatly increasing the interface state density. As a result, the leakage current is reduced and the withstand voltage is also improved, so that a MISFET having excellent characteristics can be manufactured.
[0045]
  Also,Reference example 1In this case, since such a catalyst annealing treatment can be performed at a low temperature of less than 400 ° C., particularly at a low temperature of 300 ° C. or less, the redistribution of impurities implanted into the channel region for threshold voltage control And the deterioration of the short channel effect can be prevented.
[0046]
The reason why the interface state of the SiON film can be modified even by such an annealing process at less than 400 ° C. is not necessarily clear, but it is not a mere mesh-like catalyst as in the conventional example, but 1800 to 1900. By using the tungsten catalyst body 20 of the resistance heating element having a high temperature of ° C,₂Is considered to be efficiently decomposed.
[0047]
  Also,Reference example 1In, the SiON film to be subjected to the catalyst annealing process is formed by the catalytic CVD method, and the catalyst annealing process is subsequently performed in the same apparatus, so the film forming apparatus and the annealing apparatus are made common. Furthermore, since the resistance heating element is used as the catalyst, the catalyst can be provided in the annealing apparatus, thereby simplifying the configuration of the manufacturing apparatus system.
[0048]
  Next, referring to FIG.Reference example 2H₂The processing conditions are as described above.Reference example 1Therefore, the illustration of the manufacturing process is omitted.
  First, after cleaning the surface of an n-type silicon substrate having a (100) plane as a main surface by RCA cleaning, SiO 2 having a thickness of 10 nm is formed by sputtering with the temperature of the n-type silicon substrate being 50 ° C.₂Deposit film.
[0049]
Next, using the catalytic CVD apparatus shown in FIG. 2, the temperature of the n-type silicon substrate is set to 300 ° C., and the source gas is H.₂1800 by supplying AC power of 680 W from an AC power source to a tungsten catalyst body arranged so that the gas pressure in the vacuum vessel is 0.01 Torr and the distance from the n-type silicon substrate is 3.7 cm. It is heated to ˜1900 ° C., and the heated tungsten catalyst body is added with H₂To generate active species, and in an atmosphere containing the active species, SiO₂SiO film modified by heat treating the film, for example for 10 minutes₂A film is formed.
[0050]
Refer to FIG.
FIG. 5 (a) shows H₂SiO before catalyst annealing by₂It is a figure which shows the CV characteristic of a film | membrane, Since a hysteresis loop is seen in a CV characteristic, an n-type silicon substrate and SiO₂It is understood that active dangling bonds and the like are generated at the interface with the film, and the interface state density is high.
[0051]
Refer to FIG.
FIG. 5B shows H₂Modified SiO after catalyst annealing with₂It is a figure which shows the CV characteristic of a film | membrane, Since a hysteresis loop is hardly seen in this CV characteristic, a dangling bond is terminated by the activated hydrogen and an interface state density reduces significantly. It is understood that the film quality is also improved from the shape of the CV characteristic itself.
When measuring these CV characteristics, only an Al electrode is formed, and no PMA treatment is performed.
[0052]
Like this, H₂The effect of the treatment is SiO₂It is understood that it is also effective for the film, and therefore SiO₂Even when a membrane is used, H activated by a catalyst is used.₂Due to the low temperature treatment, the interface state density can be greatly reduced without redistributing the channel-doped impurities, thereby reducing the leakage current and improving the withstand voltage. MOSFETs can be manufactured.
[0053]
  Next, referring to FIG.Reference example 3H₂The processing conditions are as described above.Reference example 1Therefore, the illustration of the manufacturing process is omitted.
  First, after cleaning the surface of a p-type silicon substrate having a (111) plane as a main surface by RCA cleaning, CeO having a thickness of 20 nm is formed by sputtering with the temperature of the p-type silicon substrate being 600 ° C.₂Deposit film.
[0054]
Next, using the catalytic CVD apparatus shown in FIG. 2, the temperature of the p-type silicon substrate is set to 300 ° C., and the source gas is H.₂1800 by supplying AC power of 680 W from an AC power source to a tungsten catalyst body disposed so that the gas pressure in the vacuum vessel is 0.01 Torr and the distance from the p-type silicon substrate is 3.7 cm. Heated to ˜1900 ° C., and this heated tungsten catalyst body was₂To generate active species, and CeO in an atmosphere containing the active species₂CeO modified by, for example, heat treating the membrane for 10 minutes₂A film is formed.
[0055]
See Fig. 6 (a)
FIG. 6A shows H₂CeO before catalyst annealing by₂It is a figure which shows the CV characteristic of a film | membrane, Since a hysteresis loop is seen in a CV characteristic, p-type silicon substrate and CeO₂It is understood that active dangling bonds and the like are generated at the interface with the film, and the interface state density is high.
[0056]
See Fig. 6 (b)
FIG. 6B shows H₂Modified CeO after catalytic annealing with₂It is a figure which shows the CV characteristic of a film | membrane, Since a hysteresis loop is hardly seen in this CV characteristic, a dangling bond is terminated by the activated hydrogen and an interface state density reduces significantly. It is understood that the film quality is also improved from the curve shape itself of the CV characteristic.
When measuring these CV characteristics, only an Al electrode is formed, and no PMA treatment is performed.
[0057]
Like this, H₂The effect of treatment is CeO₂It is understood that the present invention is also effective for a film, and therefore, CeO having a high relative dielectric constant (≈12) as a gate oxide film.₂Even when a membrane is used, H activated by a catalyst is used.₂By the low temperature treatment, the interface state density can be significantly reduced without redistributing the channel-doped impurities, thereby reducing the leakage current and improving the withstand voltage. Therefore, the relatively thick CeO film₂By using the film as a gate insulating film, a fine MOSFET having excellent characteristics can be manufactured with good reproducibility.
[0058]
  more than,Reference Example 1 to Reference Example 3Has been explained, but H₂The catalyst annealing treatment by is applied to the improvement of the interface state between the SiN film and the silicon substrate, and H₂Instead of NH₃, HN₃, N₂Nitrogen-containing gas such as O may be used. When nitrogen-containing gas is used, SiON film, SiO₂Membrane or CeO₂The interface state of the film can be improved, and the film quality can also be improved.
[0059]
  Given the above,Next, referring to FIG. 7, the characteristic feature of the catalyst annealing time is1And the second2The embodiment of the present invention will be briefly described. First, referring to FIG. 7A, the catalyst annealing is performed after the formation of the gate electrode.1The embodiment will be described.
  See Fig. 7 (a)
  First, an element isolation oxide film 42 is formed by selectively oxidizing a p-type silicon substrate 41 with a nitride film pattern (both not shown) provided via a pad oxide film as a mask, and then the nitride film pattern and the pad oxidation are formed. The film is removed, and then a SiON film having a thickness of, for example, 5 nm, which becomes a gate insulating film using a catalytic CVD method, as in the first embodiment, and a doped polysilicon film which becomes a gate electrode Are sequentially deposited, and then a gate electrode 44 and a gate insulating film 43 are formed by patterning the doped polysilicon film and the SiON film.
[0060]
  Then aboveReference example 1Under the same conditions as₂46 is brought into contact with a tungsten catalyst body 45 heated to 1800 to 1900 ° C. by supplying AC power of 680 W from an AC power source to generate active species 47, and the gate insulating film 43 and the gate are formed in an atmosphere containing the active species 47. For example, the electrode 44 is a gate insulating film 43 made of a SiON film modified by heat treatment for 10 minutes, and the gate electrode 44 is subjected to PMA treatment.
[0061]
  In this way, the first of the present invention1In the present embodiment, H which also serves as PMA processing for the gate electrode 44₂Since the interface state density of the p-type silicon substrate 41 / gate insulating film 43 is reduced by the process, a MISFET with no deterioration of the short channel effect can be manufactured with a small number of manufacturing steps.
[0062]
  This first1In this embodiment, a SiON film is used as the gate insulating film.₂Membrane, CeO₂A film or SiN film may be used.₂Membrane, CeO₂Film or SiN film is H₂Interfacial properties can be improved by annealing the catalyst.
[0063]
Moreover, the catalyst annealing in this case is H₂It is not limited to ammonia (NH_Three), Hydrogen azide (HN_Three), Nitrogen, NHCl₂Nitrogen halides such as N or N₂O, NO, NO₂Nitrogen-containing gas such as nitrogen oxide may be used, and by using such nitrogen-containing gas, dangling bonds at the interface can be terminated with N, and the gate insulating film The dielectric constant of 43 can also be increased.
[0064]
  Next, referring to FIG. 7B, the first step of the present invention in which the catalyst annealing is performed after the sidewalls are formed.2The embodiment will be described.
  Refer to FIG.
  First, an element isolation oxide film 42 is formed by selectively oxidizing a p-type silicon substrate 41 with a nitride film pattern (both not shown) provided via a pad oxide film as a mask, and then the nitride film pattern and the pad oxidation are formed. Remove the membrane, thenReference exampleIn the same manner as in Example 1, a 5 nm thick SiON film and a doped polysilicon film serving as a gate electrode are sequentially deposited using a catalytic CVD method, and then a doped polysilicon film and an SiON film are deposited. Then, the gate electrode 44 and the gate insulating film 43 are formed.
[0065]
Next, by implanting As ions using the gate electrode 44 as a mask, shallow n^-After forming a type LDD (Lightly Doped Drain) region 48, SiO 2 is formed on the entire surface using a low temperature CVD method.₂A side wall 49 is formed on the side wall of the gate electrode 44 by depositing a film and then performing anisotropic etching.
[0066]
  Next, as ions are deeply implanted using the side wall 49 as a mask,⁺ After forming the source / drain regions 50, the NH₃51 is supplied except 50-60 sccm and the gas pressure is 0.013 Torr.Reference example 1The tungsten catalyst body 45 heated to 1800-1900 ° C. under the same conditions as in₃51 is brought into contact with each other to generate active species 52, and the side wall 49 is heat-treated in an atmosphere containing the active species 52, for example, for 1 hour, thereby dangling the interface between the side wall 49 and the p-type silicon substrate 41. The bond is terminated with N, the interface state density can be reduced, and the film quality of the sidewall 49 can be improved, whereby the leakage current can be reduced and the withstand voltage can be increased.
[0067]
  In this case, the catalyst annealing of the gate insulating film 43 is performed as described above.Reference Example 1 to Reference Example 3Or may be performed immediately after the gate insulating film 43 is deposited, or1As in the above embodiment, it may be performed immediately after the patterning of the gate electrode 44, and if not performed at any time, the catalyst annealing step for the sidewall 49 is replaced with the catalyst annealing step for the gate insulating film 43. I will also serve.
[0068]
  This second2In this embodiment, NH is used as a raw material gas for catalyst annealing.₃Is used but NH₃Is not limited to HN₃, Nitrogen, NHCl₂Nitrogen halides such as N or N₂O, NO, NO₂Nitrogen-containing gases such as nitrogen oxides may be used.
[0069]
  This second2In this embodiment, the sidewall 49 is made of SiO.₂Although it is formed by a film, SiO₂The film is not limited to a film, but a SiON film formed by catalytic CVD or the like, or O₃A TEOS-NSG (Non Doped Silicate Glass) film using a TEOS (Tetra-Ethyl-Ortho-Silicate) gas may be used.
[0070]
  This second2In this embodiment, the SiON film is used as the gate insulating film, but the SiON film is used as the gate insulating film.₂Membrane, CeO₂A film or SiN film may be used.₂Membrane, CeO₂Interfacial characteristics and film quality can be improved by subjecting the film or SiN film to catalytic annealing with a nitrogen-containing gas.
[0071]
As described above, each embodiment of the present invention has been described. However, in the present invention, since a resistance heating element heated to a high temperature is used as a catalyst, an annealing process at a lower temperature can be performed. It is possible to improve the quality of the insulating film or the interface state without causing redistribution.
Further, by using a resistance heating element as the catalyst, the catalyst can be provided in a vacuum vessel that performs the annealing treatment, so that the apparatus configuration is simplified.
[0072]
The present invention is not limited to the configurations and conditions described in the embodiments, and various modifications can be made.
For example, the main feature of the present invention resides in the catalyst annealing step, and the method for depositing the insulating film to be subjected to the catalyst annealing treatment is not limited to the method described in each of the above embodiments.
[0073]
Further, in the description of each of the above embodiments, the resistance heating element having a catalytic action is constituted by a tungsten catalyst body, but is not limited to tungsten (W), and tria-containing tungsten, Pt, Pa, Mo, Si, Ta, Ti, Va, SiC, or Ti oxide may be used.
[0074]
In the catalytic CVD apparatus shown in FIG. 2, the tungsten catalyst body 20 has a coil shape, but is not limited to the coil shape because the inductance characteristic is not used. The power is not limited to AC power, and may be DC power.
[0075]
In the description of each of the above embodiments, a bulk silicon substrate such as an n-type silicon substrate or a p-type silicon substrate is used. However, the present invention is not limited to a bulk silicon substrate. It is also applicable to a single crystal silicon film grown epitaxially, or a crystalline silicon film obtained by crystallizing a polycrystalline silicon film or an amorphous silicon film deposited on an insulating substrate by laser annealing. The present invention is applied to an insulating film forming process or the like.
[0076]
In addition, since the catalyst annealing treatment of the present invention can be performed at a temperature of 300 ° C. or lower, it contributes to low-temperature processing, but is not necessarily limited to 300 ° C. or lower. When mitigated, the catalyst annealing process may be performed at a temperature of 300 ° C. or higher. For example, when the PMA process is also performed, it may be performed at a temperature of less than 400 ° C.
[0077]
【The invention's effect】
According to the present invention, the catalyst comprising the resistance heating element heated to a high temperature can be₂Since the interface state and film quality are improved by decomposing the raw material gas, etc. and performing low-temperature annealing treatment in the atmosphere of the active species generated by the decomposition, the redistribution of impurities can be suppressed, thereby It becomes possible to manufacture excellent MISFETs without variations and greatly contributes to miniaturization and high performance of highly integrated semiconductor integrated circuit devices.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a basic configuration of the present invention.
FIG. 2 is a conceptual configuration diagram of a catalytic CVD apparatus used in each embodiment of the present invention.
FIG. 3 of the present inventionReference example 1It is explanatory drawing of this manufacturing process.
FIG. 4 of the present inventionReference example 1H₂It is explanatory drawing of the improvement effect of the interface characteristic by a process.
FIG. 5 shows the present invention.Reference example 2H₂It is explanatory drawing of the improvement effect of the interface characteristic by a process.
FIG. 6 of the present inventionReference example 3H₂It is explanatory drawing of the improvement effect of the interface characteristic by a process.
FIG. 7 shows the first of the present invention.1And the second2It is explanatory drawing of the manufacturing process of this embodiment.
[Explanation of symbols]
1 Base
2 Hydrogen gas
3 resistance heating elements
4 active species
5 Insulating film
11 Vacuum container
12 valves
13 Diffusion pump
14 Substrate holder
15 samples
16 Heater
17 Thermocouple
18 Gas supply pipe
19 Source gas
20 Tungsten catalyst body
21 AC power supply
22 Infrared radiation thermometer
23 Shutter
31 n-type silicon substrate
32 NH_Three
33 SiH_Four
34 Active species
35 active species
36 SiON film
37 H₂
38 Active species
39 SiON film
41 p-type silicon substrate
42 Device isolation oxide film
43 Gate insulation film
44 Gate electrode
45 Tungsten catalyst body
46H₂
47 Active species
48 LDD region
49 Sidewall
50 n⁺Type source / drain region
51 NH_Three
52 active species

Claims (5)

After forming the gate electrode on the gate oxide film deposited on the substrate made of silicon , the nitrogen-containing gas is blown to the resistance heating element made of the catalyst, and the nitrogen-containing gas is brought into contact with the resistance heating element by the nitrogen-containing gas. A method for manufacturing a semiconductor device, comprising: decomposing at least a part of the gate oxide film and exposing the gate oxide film to an atmosphere of active species generated by the decomposition. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide film is one of a SiO ₂ film, a SiON film, and a CeO ₂ film. 3. The semiconductor device according to claim 1, wherein after the sidewall oxide film is formed on the sidewall of the gate electrode, the sidewall oxide film is exposed again to an atmosphere of active species generated by the decomposition. Manufacturing method. 4. The method of manufacturing a semiconductor device according to claim 3 , wherein the sidewall oxide film is one of a SiO ₂ film, a SiON film, or a TEOS-NSG film. The nitrogen-containing gas is any one of ammonia, hydrogen azide, nitrogen, nitrogen halide, or nitrogen oxide, according to any one of claims 1 to 4 . A method for manufacturing a semiconductor device.

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