JP2006196713A - Semiconductor device, fabricating method thereof, and deuterium processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a formed good gate-oxide-film/semiconductor interface whose interface level density is low, a deuterium processor for forming the semiconductor device, and a fabricating method of the semiconductor device, by using an activated deuterium generated by the thermal catalyzer action of a gas containing deuterium which is performed on a thermal-catalyzer-substance surface heated to a high temperature to a semiconductor device (field effect transistor (MIS or MOSFET)) having a metal-insulating film (or oxide film)-semiconductor (MIS or MOS) structure formed on a semiconductor substrate including a silicon-carbide region, and by intending at a low temperature not higher than 600°C the deuterium termination of a dangling bond present near a gate insulating film/silicon-carbide semiconductor interface. <P>SOLUTION: The semiconductor device has a metal-insulating film-semiconductor (MIS) structure wherein the deuterium-element concentration is not smaller than 1×10<SP>19</SP>/cm<SP>-3</SP>present near such films or layers formed in a semiconductor device as a semiconductor substrate, a gate insulating film, an interlayer insulating film, a wiring layer, and a protective insulating film. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a metal-insulating film (or oxide film) -semiconductor (MIS or MOS) structure on a semiconductor substrate (field effect transistor (MIS or MOSFET)) heated to a high temperature. An interface of various films or layers formed in a good semiconductor device having a low interface state density by supplying activated deuterium generated by thermal catalysis of gas containing deuterium on the surface of the catalyst body, In particular, the present invention relates to a semiconductor device in which a gate oxide film / semiconductor interface is formed, a manufacturing method thereof, and a deuterium processing apparatus for forming the semiconductor device.

Silicon carbide has excellent physical properties compared to silicon, such as (1) a wide band gap, (2) a high dielectric breakdown strength, and (3) a high saturation drift velocity of electrons. Therefore, by using silicon carbide as a semiconductor substrate material, a power semiconductor element having a high breakdown voltage and a low resistance exceeding the limit of silicon can be produced. In addition, silicon carbide has a feature that a silicon oxide film which is an insulator can be formed by a thermal oxidation method, similarly to silicon.
For these reasons, it is considered that a high breakdown voltage and low on-resistance MOSFET using silicon carbide as a semiconductor substrate material can be realized, and many researches and developments have been conducted. However, the on-resistance of silicon carbide semiconductor power devices manufactured by the current technology is smaller than the value of silicon semiconductors, but it is much larger than the theoretical limit value to fully demonstrate the performance of silicon carbide. Not reached.

This results in a high interface state density due to the presence of high-density defects (dangling bonds) at the silicon oxide / silicon carbide semiconductor interface and the silicon carbide semiconductor surface. As a result, the electron mobility of the inversion layer channel is increased. This is due to being extremely small (˜10 cm ² / Vs).
The defects (dangling bonds) existing at the silicon oxide film / semiconductor interface and the semiconductor surface described above are not only the process of forming the gate insulating film on the semiconductor substrate, but also the process of forming the interlayer insulating film, the wiring layer This also occurs due to damage received by the semiconductor substrate in the step of forming and the step of forming the insulating film for protecting the wiring layer.

  Therefore, it is important to supply deuterium to the dangling bond existing near the interface between the silicon oxide film and the semiconductor to terminate the dangling bond with deuterium and reduce the interface state density. Deuterium treatment for reducing the density is generally performed. As described above, dangling bonds existing at the silicon oxide film / silicon semiconductor interface are also generated in various process steps after the gate insulating film is formed. Therefore, it is preferable that the hydrogen treatment is performed in the final step of the process. . Therefore, it is necessary to lower the deuterium treatment to 600 ° C. or lower, which is a temperature lower than the melting point of the gate electrode film containing aluminum.

Up to now, there have already been several disclosures regarding methods for producing a silicon oxide film / semiconductor substrate interface using deuterium treatment.
For example, it has been reported that post-annealing in a deuterium (D ₂ ) gas atmosphere at 900 ° C. for 30 minutes is effective in suppressing interface state generation with the substrate interface of the gate oxide film. (For example, see Non-Patent Document 1) As described above, an annealing temperature of 600 ° C. or higher is higher than the melting point of aluminum, which is a metal wiring material, so that it may be introduced as the final step of the semiconductor device manufacturing process. There is a problem that you can not.

The present invention also relates to a method for manufacturing a semiconductor device including an oxidation step, in which an oxide film is formed by oxidizing a semiconductor layer in an atmosphere containing deuterium for the purpose of incorporating more deuterium bonds into the oxide film than before. Is described (see Patent Document 1).
In Patent Document 1, since the gate insulating film is heated to 800 ° C. and vapor of heavy water is supplied to the surface thereof, the melting point of aluminum, which is a metal wiring material, is higher than that described above, and the semiconductor device is manufactured. There is a problem that it cannot be introduced as the final step of the process.

In addition, for the purpose of providing a structure capable of realizing a thin gate insulating film with high electrical reliability and a manufacturing method thereof, a step of forming a gate insulating film on a seed surface of a semiconductor substrate, A step of adding a deuterium atom to the gate insulating film so that the heavy water and concentration distribution at the interface with the gate electrode is higher than the intermediate region in the film thickness direction of the gate insulating film. A manufacturing method is described (see Patent Document 2).
This Patent Document 2 describes a method of performing a thermal annealing treatment at 900 ° C. in an ND ₃ atmosphere after forming a gate oxide film. In the thermal annealing at 900 ° C. as described above, a metal wiring material is used. Therefore, there is a problem that it cannot be introduced as the final step of the semiconductor device manufacturing process.
NS Saks et al. [IEEE Trans. Vol.NS-39, pp.2220-2229 (1992)] JP-A-10-223628 Japanese Patent Application Laid-Open No. 11-274489

  In view of the above problems, the present invention provides a semiconductor device (field effect transistor (MIS) having a metal-insulating film (or oxide film) -semiconductor (MIS or MOS) structure formed on a semiconductor substrate including a silicon carbide region. Alternatively, for MOSFET)), by using activated deuterium generated by thermal catalysis of a gas containing deuterium on the surface of the thermal catalyst heated to a high temperature, at a low temperature of 600 ° C. or less, Good gate oxide film / semiconductor interface with low interface state density by deuterium termination of dangling bonds existing in the vicinity of the gate insulating film / silicon carbide semiconductor interface, especially the film or layer interface formed in the semiconductor device It is an object of the present invention to obtain a semiconductor device in which is formed, a manufacturing method thereof, and a deuterium treatment apparatus for forming the semiconductor device.

In order to solve the above problems, the following inventions are provided.
Invention 1) is a semiconductor device having a metal-insulating film-semiconductor (MIS) structure, such as a semiconductor substrate, a gate insulating film, an interlayer insulating film, a wiring layer, a protective insulating film, etc. The deuterium element concentration in the vicinity of the interface is 1 × 10 ¹⁹ cm ⁻³ or more.
In this case, the effect is recognized when the deuterium element concentration is 1 × 10 ¹⁹ cm ⁻³ or more, and the effect increases as the deuterium element concentration increases. For example, the unit area of silicon element or carbon element on the silicon carbide (Si surface or C surface) semiconductor Since the number of atoms per unit is about 1.2x10 ¹⁵ cm ^-2 , when converted to the number of atoms per unit volume, the number of atoms per unit volume is about 4.2x10 ²² cm ^-3 , so the upper limit is It is desirable to be about 5x10 ²² cm ^-3 . If it is this range, said defect (dangling bond) can be suppressed effectively. However, the upper limit of the deuterium element concentration is not particularly limited.

  Invention 2) is a substrate selected from silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium aluminum arsenide, gallium phosphide, gallium nitride, aluminum nitride or diamond as the semiconductor substrate in the semiconductor device described in 1) above. It is characterized by using.

Invention 3) is a semiconductor device as described in 1) or 2) above, wherein a semiconductor substrate made of silicon or silicon carbide is heated in air, in an oxygen atmosphere, or in a water vapor atmosphere containing H ₂ O (water). A gate insulating film made of an oxide film formed by doing so is provided.

  Invention 4) is the semiconductor device described in each of 1) to 3) above, wherein the gate insulating film is one film selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or two or more composite films. It is characterized by being.

  The invention 5) is characterized in that, in the semiconductor devices described in 1) to 4) above, the semiconductor device having an MIS structure is a DMOSFET, a lateral resurf MOSFET, or a UMOSFET.

  Invention 6) relates to a method for manufacturing a semiconductor device, and in a method for manufacturing a semiconductor device including a step of forming a gate insulating film on a semiconductor substrate, after forming the gate insulating film on the semiconductor substrate, the semiconductor device is formed in the vicinity of the semiconductor substrate. A thermal catalyst is arranged, and a gas containing deuterium is allowed to pass through the vicinity of the thermal catalyst to generate deuterium activated by thermal catalysis on the surface of the heated thermal catalyst, and the activity The hydrogenated deuterium is supplied to the semiconductor substrate.

  Invention 7) relates to a method for manufacturing a semiconductor device, and in a method for manufacturing a semiconductor device including a step of forming a gate insulating film on a semiconductor substrate, the step of forming a gate insulating film on the semiconductor substrate and a gate made of a material containing aluminum. After the step of forming the electrode film, a thermal catalyst is disposed in the vicinity of the semiconductor substrate, and a gas containing deuterium is allowed to pass through the vicinity of the thermal catalyst so that the surface of the heated thermal catalyst is heated. Deuterium activated by thermal catalysis is generated, and the activated deuterium is supplied to the semiconductor substrate.

Invention 8) is characterized in that, in the method for manufacturing a semiconductor device according to 6) or 7) above, the deuterium element concentration in the vicinity of the interface between the gate insulating film and the semiconductor substrate is 1 × 10 ¹⁹ cm ⁻³ or more. The upper limit is not particularly limited, but the number of atoms per unit area of silicon element or carbon element on the silicon carbide (Si surface or C surface) semiconductor is about 1.2 × 10 ¹⁵ cm ^−2. if this was converted into the number of atoms per unit volume, the number of atoms per unit volume from the fact that about 4.2 x 10 ²² cm ^-3, it can be said that to be about 5x10 ²² cm ^-3 desirable.

  Invention 9) is the method for manufacturing a semiconductor device according to any one of 6) to 8) above, wherein the semiconductor substrate is silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium aluminum arsenide, gallium phosphide, gallium nitride. A substrate selected from aluminum nitride or diamond.

Invention 10) is a method for manufacturing a semiconductor device according to any one of 6) to 9) above, wherein the semiconductor substrate made of silicon or silicon carbide contains air, oxygen atmosphere, or H ₂ O (water). A gate insulating film made of an oxide film is formed by heating in a steam atmosphere.

  Invention 11) is a method of manufacturing a semiconductor device according to any one of 6) to 9) above, wherein one film or two or more films selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film by a chemical vapor deposition method are used. A gate insulating film made of the composite film is formed.

  Invention 12) is characterized in that, in the method for manufacturing a semiconductor device according to any one of 6) to 10), the semiconductor device having a gate insulating film is a DMOSFET, a Lateral Resurf MOSFET, or a UMOSFET.

  Invention 13) is the method for manufacturing a semiconductor device according to any one of 6) to 12) above, wherein the thermal catalyst is one metal selected from tungsten, molybdenum, tantalum, titanium, and vanadium, or a main component thereof. It is characterized by being an alloy. These thermal catalyst bodies can generate deuterium effectively.

  Invention 14) is a method for manufacturing a semiconductor device according to any one of 6) to 13) above, wherein the temperature of the semiconductor substrate is maintained at 600 ° C. or lower. If the temperature exceeds 600 ° C., the gate electrode metal film such as aluminum is melted, which leads to disconnection / short circuit of the wiring or deterioration of the gate insulating film.

Invention 15) is a method of manufacturing a semiconductor device as described in 14) above, wherein the thermal catalyst is heated to a predetermined temperature of 1000 ° C. to 1800 ° C. Activated deuterium is generated from a gas containing hydrogen. A temperature of 1000 ° C. to 1800 ° C. is an effective temperature for generating activated deuterium from a gas containing deuterium.
However, depending on manufacturing conditions, it may be outside this range. Since the optimum conditions can vary depending on the structure of the manufacturing apparatus or the film forming material, it is a matter of course that it can be changed according to the situation of the equipment. Examples of the gas containing deuterium include deuterium compound gases such as ND ₃ and SiD _{4 in} addition to D ₂ gas.

  Invention 16) is characterized in that in the method for manufacturing a semiconductor device described in 15) above, the gas pressure containing deuterium is 1 Pa to 100 Pa. The gas pressure including deuterium is set to 1 Pa to 100 Pa is a gas pressure for effectively introducing deuterium into the gate oxide / semiconductor interface. However, depending on manufacturing conditions, it may be outside this range. Since the optimum conditions can vary depending on the structure of the manufacturing apparatus or the film forming material, it is a matter of course that it can be changed according to the situation of the equipment.

Invention 17 is a method for producing a semiconductor device as described in 16) above, wherein activated deuterium generated from a gas containing deuterium by thermal catalysis on the surface of a thermal catalyst heated to high temperature is added for 1 minute to A predetermined time of 3 hours is supplied.
One minute to three hours is a gas supply time for effectively introducing deuterium into the gate oxide film / semiconductor interface or the like. However, depending on manufacturing conditions, it may be outside this range. Since the optimum conditions can vary depending on the structure of the manufacturing apparatus or the film forming material, it is a matter of course that it can be changed according to the situation of the equipment.

The invention 18) is characterized in that in the method for manufacturing a semiconductor device according to the above 17), the distance between the semiconductor substrate having the gate insulating film and the thermal catalyst is disposed at a predetermined distance of 10 mm to 120 mm. And
This distance is an optimum distance for effectively introducing deuterium into the gate oxide / semiconductor interface. However, depending on manufacturing conditions, it may be outside this range. Since the optimum conditions can vary depending on the structure of the manufacturing apparatus or the film forming material, it is a matter of course that it can be changed according to the situation of the equipment.

Invention 19) is a method of manufacturing a semiconductor device as described in 6) to 18) above, wherein a step of forming a gate oxide film and deuterium treatment by supplying deuterium activated by a thermal catalyst to a semiconductor substrate. Between the steps, a heat treatment in an oxygen atmosphere or a heat treatment in an inert gas atmosphere is included.
This step is effective in improving the insulating properties of the gate insulating film and reducing the interface state density. However, this is not a necessary process. That is, it should be understood that this is a more preferred process and a recommended embodiment.

Invention 20) is a method of manufacturing a semiconductor device as described in 19) above, in which a heat treatment in an oxygen atmosphere or an inert gas atmosphere, and deuterium activated by a thermal catalyst is supplied to the semiconductor substrate and deuterated. A method for manufacturing a semiconductor device, including a step of performing a heat treatment in a water vapor atmosphere containing H ₂ O (water) between the step of hydrogen treatment.
This step is effective in reducing the interface state density. However, this is not a necessary process. That is, it should be understood that this is a more preferred process and a recommended embodiment.

Invention 21) is a method of manufacturing a semiconductor device as described in 19) above, in which a heat treatment in an oxygen atmosphere or an inert gas atmosphere, and deuterium activated by a thermal catalyst is supplied to the semiconductor substrate and deuterated. Between the step of hydrogen treatment, a step of heat treatment in an atmosphere containing NO, N ₂ O, or NO ₂ is included. This step is effective in improving the insulating properties of the gate insulating film and reducing the interface state density. However, this is not a necessary process. That is, it should be understood that this is a more preferred process and a recommended embodiment.

  The invention 22) is characterized in that in the method for manufacturing a semiconductor device described in the above 6) to 20), a step of cleaning the surface of the semiconductor substrate is included. Surface cleaning is effective for introducing deuterium into the gate oxide / semiconductor interface.

  Invention 23) is characterized in that in the method for manufacturing a semiconductor device according to 22) above, the cleaning process of the surface of the semiconductor substrate includes an oxidation treatment. This is performed for the purpose of removing impurities existing in the surface layer of the semiconductor substrate and flattening the surface of the semiconductor substrate. This is not a necessary process. That is, it should be understood that this is a more preferred process and a recommended embodiment.

  The invention 24) is characterized in that in the method for manufacturing a semiconductor device according to the above 22) or 23), the cleaning process of the surface of the semiconductor substrate includes an ozone exposure treatment accompanied by irradiation with ultraviolet light. This is performed for the purpose of removing impurities present in the surface layer of the semiconductor substrate. This is not a necessary process. That is, it should be understood that this is a more preferred process and a recommended embodiment.

  The invention 25) includes a step of forming an interlayer insulating film, a step of forming a wiring layer, and a protection of the wiring layer in addition to the steps included in the method for manufacturing a semiconductor device described in 6) to 24) above. And an activated deuterium is applied to an interface between these films or layers.

  The invention 26) relates to a deuterium treatment apparatus, wherein a chamber in which a semiconductor substrate having a gate insulating film can be arranged at a predetermined position and a semiconductor substrate arranged at the predetermined position can be adjusted to a predetermined temperature. Heating means capable of heating, a thermal catalyst provided near the surface of the semiconductor substrate disposed at a predetermined position, a heating means for heating the thermal catalyst to a predetermined temperature, a vacuum exhaust system capable of reducing the pressure in the chamber, A gas introduction system for introducing a gas containing deuterium into the chamber and a pressure adjusting mechanism for the gas containing deuterium in the chamber were heated by passing the gas containing deuterium near the surface of the thermal catalyst. Activated deuterium generated by thermal catalysis on the surface of the thermal catalyst is supplied to the surface of the semiconductor substrate.

  Invention 27) is the deuterium treatment apparatus as described in 26) above, wherein the semiconductor substrate is selected from silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium aluminum arsenide, gallium phosphide, gallium nitride, aluminum nitride or diamond. It is characterized by being a substrate.

  Invention 28) is the deuterium treatment apparatus as described in 26) or 27) above, wherein the thermal catalyst is one metal selected from tungsten, molybdenum, tantalum, titanium, and vanadium, or an alloy containing these as a main component. It is characterized by that.

  The invention 29) is characterized in that in the deuterium treatment apparatus according to any one of the above 26) to 28), an apparatus for maintaining the temperature of the semiconductor substrate at 600 ° C. or lower is provided.

  Invention 30) comprises the apparatus for heating the thermal catalyst to a predetermined temperature of 1000 ° C. to 1800 ° C. in the deuterium treatment apparatus according to any of the above 26) to 29), Deuterium activated by the thermal catalysis on the surface of the thermal catalyst is generated.

  Invention 31) is characterized in that in the deuterium treatment apparatus according to any one of the above 26) to 30), a pressure adjusting mechanism for adjusting a gas pressure containing deuterium to 1 Pa to 100 Pa is provided.

  Invention 32) is the deuterium treatment apparatus according to any one of the above 26) to 31), wherein the deuterium treatment apparatus is activated from a gas containing deuterium by thermal catalysis on the surface of the thermal catalyst heated to a high temperature. A device is provided that supplies deuterium for a predetermined time of 1 minute to 3 hours.

  Invention 33) is the deuterium treatment apparatus according to any one of 26) to 32), wherein the distance between the semiconductor substrate having the gate insulating film and the thermal catalyst is 10 mm to 120 mm. It is characterized by.

According to the present invention, a semiconductor device (field effect transistor (MIS or MOSFET)) having a metal-insulating film (or oxide film) -semiconductor (MIS or MOS) structure formed on a semiconductor substrate particularly including a silicon carbide region. On the other hand, by using activated deuterium generated by the thermal catalysis of the gas containing deuterium on the surface of the thermal catalyst heated to a high temperature, the gate insulating film can be formed at a low temperature of 600 ° C. or lower. / Deuterium termination of dangling bonds existing in the vicinity of the silicon carbide semiconductor interface can be achieved, and a favorable gate oxide film / semiconductor interface having a low interface state density can be formed.
That is, since deuterium treatment is performed using activated deuterium generated by thermal catalysis on the surface of the heated catalyst body, an excellent interface state with reduced interface state density can be formed at a low temperature. It has the effect. Further, since the deuterium treatment with the activated deuterium is effective even at a substrate heating temperature of 600 ° C. or lower, after the step of forming the gate electrode film containing aluminum, the silicon carbide semiconductor device is manufactured. As a final step of the process, there is a remarkable effect that the deuterium treatment can be introduced.

The features of the present invention will be specifically described below with reference to the drawings. In addition, the following description is for making an understanding of this invention easy, and is not restrict | limited to this. That is, modifications, embodiments, and other examples based on the technical idea of the present invention are included in the present invention.
FIG. 1 shows a semiconductor device (field effect transistor (MIS or MOSFET)) having a metal-insulating film (or oxide film) -semiconductor (MIS or MOS) structure on a semiconductor substrate including a silicon carbide region according to the present invention. A good gate insulating film / silicon having a low interface state density by supplying activated deuterium generated from a gas containing deuterium by thermal catalysis on the surface of the thermal catalyst heated to a high temperature It is a figure which shows one Embodiment of the deuterium processing apparatus which forms a carbide semiconductor interface.

  Reference numeral 1 is a chamber, reference numeral 2 is an evacuation system capable of depressurizing the chamber 1, reference numeral 3 is a gas introduction system for introducing a gas containing deuterium into the chamber 1, and reference numeral 4 is a semiconductor disposed at a predetermined position. Reference numeral 5 denotes a heating means for heating the substrate 7, reference numeral 5 denotes a heating means for heating the thermal catalyst 16 to a predetermined temperature, and reference numeral 6 denotes a load lock chamber for vacuum-transporting the semiconductor substrate 7 into the chamber 1.

The chamber 1 is a highly airtight vacuum vessel provided with a vacuum exhaust system 2. The evacuation system 2 is a multi-stage type equipped with a plurality of vacuum pumps such as a turbo molecular pump and a dry pump, and evacuates the chamber 1 to a pressure of 10 ⁻⁴ Pa or less.
In addition, the load lock chamber 6 for vacuum transporting the semiconductor substrate 7 into the chamber 1 is also evacuated to a pressure of 10 ⁻¹ Pa or less by the evacuation system 2.
The semiconductor substrate 7 is disposed on the upper surface of the substrate holder 8, is vacuum-transferred into the chamber 1 through the load lock chamber 6, and is disposed on the upper surface of the quartz substrate holder base 10.

The semiconductor substrate 7 is performed using the heating means 4 installed in the lower part of the chamber 1 and adopts an infrared heating method. Infrared rays radiated from the infrared lamp 14 serving as a heat source are reflected by the gold reflecting mirror inside the infrared condensing unit 12 and reflected through the transparent quartz window 13 attached to the lower part of the chamber 1 to the substrate holder 8 disposed inside the chamber 1. Irradiated.
The substrate holder 8 absorbs infrared rays and can be heated to 800 ° C. under a reduced pressure deuterium atmosphere. The substrate holder 8 is formed of a silicon semiconductor wafer, a silicon carbide sintered body, graphite, or the like.

The deuterium treatment gas introduction system 7 is formed by a pipe 17 for introducing a gas containing deuterium into the chamber 1, a valve 18 provided in the pipe 17, a flow rate regulator 19, and the like.
Further, as shown in FIG. 1, a ring-shaped gas introduction ring 11 is disposed at the position of the outer surface of the quartz substrate holder base 10 on which the substrate holder 8 is disposed on the upper surface. The gas introduction ring 11 is hollow inside and has a number of gas ejection holes on the upper surface.

A distal end of a pipe 17 for introducing a gas containing deuterium is connected to a gas introduction ring 11 so that a gas containing deuterium is ejected from a gas ejection hole and introduced into the chamber 1. The pressure in the chamber 1 is monitored by a miniature gauge and a baratron gauge (not shown) and automatically adjusted by a conductance valve 15.
Activated deuterium is generated from the gas containing deuterium introduced by the deuterium treatment gas introduction system 3 by the thermal catalysis on the surface of the thermal catalyst 16 heated to a high temperature.

The thermal catalyst 16 is made of tungsten, molybdenum, tantalum, titanium, vanadium or an alloy containing these as a main component. The thermal catalyst 16 can move up and down within a range of 90 mm. The thermal catalyst 16 is provided with a heating means 20.
As an example, the heating means 20 described in the figure is configured by an energization heating power source that energizes and heats the thermal catalyst body 16. By such a heating means 20, the thermal catalyst 16 is heated to a temperature of 1000 ° C to 1800 ° C. The heating means 20 may have another structure as long as it can decompose the gas containing deuterium and release the activated deuterium. In particular, the structure is not limited.

  The quartz cylinder 9 is disposed so as to cover the inner wall of the chamber 1, and activated deuterium generated by thermal catalysis on the surface of the thermal catalyst 16 heated to a high temperature collides with the inner wall of the chamber 1 and is lost. This is to prevent it from being alive.

Next, embodiments of the invention relating to the semiconductor device and the manufacturing method thereof will be described.
In order to fabricate a SiC MOS capacitor having a cross-sectional structure as shown in FIG. 2, first, an 8 ° off 4H-SiC epitaxial substrate ((0001) Si surface, n-type, N _d −N _a = 1 × 10 ¹⁵ cm ⁻³ ) is used. After RCA cleaning, a 50 nm thick gate oxide film was formed on the silicon carbide substrate, and the sample was continuously heat-treated at 1200 ° C. for 30 minutes in nitrogen gas at a flow rate of 1 liter / min.
Next, the sample was introduced into the deuterium treatment apparatus, and the treatment in the activated deuterium atmosphere generated by the thermal catalysis on the surface of the thermal catalyst heated to a high temperature was performed. The treatment time was 30 minutes, the pressure in the chamber during treatment was 20 Pa, and the heating temperature of the thermal catalyst was 1800 ° C.
Finally, an aluminum film was formed as a gate electrode and an ohmic contact electrode by resistance wire heating vacuum deposition. For comparison, a sample not subjected to deuterium treatment was prepared.

FIG. 3 shows a high frequency CV characteristic (measurement frequency f = 100 kHz) and a quasi-static CV characteristic (steps) measured from a sample subjected to deuterium (D-rad) treatment after forming a gate oxide film in an oxygen atmosphere. Voltage V _s = 50 mV, delay time t _d = 10 _sec ).
A solid line is a high frequency CV characteristic, and a broken line is a quasi-static CV characteristic. The smaller the capacitance difference between the two CV characteristics, the smaller the interface state density (D _it ). For comparison, the high-frequency and quasi-static CV characteristics from a thermal oxidation-only sample (DRY) without deuterium irradiation are also shown in the figure.
FIG. 4 shows the distribution in the energy band of silicon carbide of the interface state density (D _it ) calculated from the data of FIG. 3 using the following [Equation 1]. Here, Ch is a high frequency capacity, Cq is a quasi-static capacity, C _ox is a gate oxide film capacity, and q is an elementary charge of electrons.

  FIG. 4 shows interface state density distributions of a sample (D-rad) subjected to deuterium treatment and a sample not subjected to deuterium treatment (DRY) after forming a gate oxide film in an oxygen atmosphere. This result shows that the interface state density at the SiC MOS interface is decreased by deuterium treatment.

  The above-described decrease in interface state density is an effect of deuterium treatment, and is a result of deuterium termination of dangling bonds existing in the vicinity of the gate insulating film / silicon carbide semiconductor interface. Therefore, the deuterium element concentration existing near the interface is important. Table 1 shows the concentration of deuterium elements present at the gate oxide / silicon carbide semiconductor interface measured by secondary ion mass spectrometry (SIMS).

The deuterium-treated sample (DRY) has an interface deuterium element concentration of 1 × 10 ¹⁷ cm ⁻³ , while the deuterium-treated sample (D-rad) has 2.8 × 10 ¹⁹ cm ^−3. And a deuterium content concentration of 280 times. The interface state density decreases when the deuterium element concentration is 2.8 x 10 ¹⁹ cm ^-3 , and from this result, the deuterium element concentration near the interface must be at least 1 x 10 ¹⁹ cm ^-3 or more. I understand.

  As described above, according to the present invention, since deuterium treatment is performed using activated deuterium generated by thermal catalysis on the surface of the heated catalyst body, a good interface state with a reduced interface state density can be obtained at a low temperature. Since the deuterium treatment with the activated deuterium is effective even at a substrate heating temperature of 600 ° C. or lower, after the step of forming the gate electrode film containing aluminum, the silicon carbide semiconductor is further formed. As a final step of the device manufacturing process, the deuterium treatment can be introduced, and a semiconductor device having a metal-insulating film (or oxide film) -semiconductor (MIS or MOS) structure (field effect transistor (MIS or MOSFET)).

It is a schematic explanatory drawing which shows an example of the deuterium processing apparatus of this invention. It is a cross-sectional schematic diagram of a MOS structure used for evaluation of capacitance-voltage characteristics. It is a figure which shows the CV curve of the sample which performed the deuterium process after forming the gate oxide film in oxygen atmosphere, and the sample which has not performed the deuterium process. In the figure, a solid line indicates a high-frequency CV curve, and a broken line indicates a quasi-static CV curve. It is a figure which shows distribution within the energy gap of the interface state density derived | led-out from the CV curve of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Chamber 2 Vacuum exhaust system 3 Gas introduction system for deuterium treatment 4 Substrate heating means 5 Thermal catalyst heating means 6 Load lock chamber 7 Semiconductor substrate 8 Substrate holder 9 Quartz cylinder 10 Quartz substrate holder stand 11 Gas introduction ring 12 Infrared collector Optical part 13 Transparent quartz window 14 Infrared lamp 15 Conductance valve 16 Thermal catalyst 17 Piping 18 Valve 19 Flow controller 20 Thermal catalyst heating means

Claims (33)

Deuterium element concentration in the vicinity of the interface between a semiconductor substrate and a film or layer formed on a semiconductor device such as a gate insulating film, an interlayer insulating film, a wiring layer, a protective insulating film, etc. is 1 × 10 ¹⁹ cm ⁻³ or more A semiconductor device having a metal-insulating film-semiconductor (MIS) structure.   2. The semiconductor device according to claim 1, wherein the semiconductor substrate is a substrate selected from silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium aluminum arsenide, gallium phosphide, gallium nitride, aluminum nitride, or diamond. 3. The semiconductor device according to claim 1, wherein the semiconductor substrate made of silicon or silicon carbide is heated by heating in air, in an oxygen atmosphere, or in a water vapor atmosphere containing H ₂ O (water). A semiconductor device comprising a gate insulating film made of a film.   4. The semiconductor device according to claim 1, wherein the gate insulating film is one film selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or two or more composite films. Semiconductor device.   5. The semiconductor device according to claim 1, wherein the semiconductor device having an MIS structure is a DMOSFET, a lateral resurf MOSFET, or a UMOSFET.   In a method for manufacturing a semiconductor device including a step of forming a gate insulating film on a semiconductor substrate, after forming the gate insulating film on the semiconductor substrate, a thermal catalyst is disposed in the vicinity of the semiconductor substrate, and a gas containing deuterium To pass through the vicinity of the thermal catalyst body, to generate deuterium activated by thermal catalysis on the surface of the heated thermal catalyst body, and to supply the activated deuterium to the semiconductor substrate A method for manufacturing a semiconductor device.   In a method for manufacturing a semiconductor device including a step of forming a gate insulating film on a semiconductor substrate, the semiconductor substrate is formed after the step of forming a gate insulating film on the semiconductor substrate and the step of forming a gate electrode film with a material containing aluminum. A thermal catalyst body is disposed in the vicinity of the thermal catalyst body so that a gas containing deuterium passes through the vicinity of the thermal catalyst body to generate deuterium activated by thermal catalytic action on the surface of the heated thermal catalyst body. A method for manufacturing a semiconductor device, comprising supplying the activated deuterium to the semiconductor substrate. 8. The method for manufacturing a semiconductor device according to claim 6, wherein the deuterium element concentration in the vicinity of the interface between the gate insulating film and the semiconductor substrate is 1 × 10 ¹⁹ cm ⁻³ or more.   9. The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor substrate is made of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium aluminum arsenide, gallium phosphorus, gallium nitride, aluminum nitride, or diamond. A method for manufacturing a semiconductor device, which is a selected substrate. 10. The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor substrate made of silicon or silicon carbide is heated in the air, in an oxygen atmosphere, or in a water vapor atmosphere containing H ₂ O (water). And forming a gate insulating film made of an oxide film.   10. The method for manufacturing a semiconductor device according to claim 6, wherein the gate is formed of one film or two or more composite films selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film by a chemical vapor deposition method. A method for manufacturing a semiconductor device, comprising forming an insulating film.   11. The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor device having a gate insulating film is a DMOSFET, a lateral resurf MOSFET, or a UMOSFET.   13. The method for manufacturing a semiconductor device according to claim 6, wherein the thermal catalyst is one metal selected from tungsten, molybdenum, tantalum, titanium, and vanadium or an alloy containing these as a main component. A method for manufacturing a semiconductor device.   14. The method for manufacturing a semiconductor device according to claim 6, wherein the temperature of the semiconductor substrate is maintained at 600 [deg.] C. or lower.   15. The method for manufacturing a semiconductor device according to claim 14, wherein the thermal catalyst is heated to a predetermined temperature of 1000 ° C. to 1800 ° C., and deuterium-containing gas is generated by thermal catalytic action on the surface of the thermal catalyst. A method for manufacturing a semiconductor device, characterized in that activated deuterium is generated.   The method for manufacturing a semiconductor device according to claim 15, wherein the gas pressure including deuterium is 1 Pa to 100 Pa.   17. The method for manufacturing a semiconductor device according to claim 16, wherein activated deuterium generated from a gas containing deuterium by thermal catalysis on a surface of a thermal catalyst heated to a high temperature is preliminarily maintained for 1 minute to 3 hours. A method for manufacturing a semiconductor device, wherein the semiconductor device is supplied for a predetermined time.   18. The method for manufacturing a semiconductor device according to claim 17, wherein the semiconductor substrate having the gate insulating film and the thermal catalyst are disposed at a predetermined distance of 10 mm to 120 mm. Manufacturing method.   19. The method for manufacturing a semiconductor device according to claim 6, wherein between the step of forming a gate oxide film and the step of supplying deuterium activated by a thermal catalyst to a semiconductor substrate to perform deuterium treatment, A method for manufacturing a semiconductor device, comprising a step of heat-treating in an oxygen atmosphere or a step of heat-treating in an inert gas atmosphere. 20. A method of manufacturing a semiconductor device according to claim 19, wherein a heat treatment in an oxygen atmosphere or an inert gas atmosphere, a deuterium treatment by supplying deuterium activated by a thermal catalyst to a semiconductor substrate, A method for manufacturing a semiconductor device, comprising a step of performing a heat treatment in a water vapor atmosphere containing H ₂ O (water). 20. A method of manufacturing a semiconductor device according to claim 19, wherein a heat treatment in an oxygen atmosphere or an inert gas atmosphere, a deuterium treatment by supplying deuterium activated by a thermal catalyst to a semiconductor substrate, A method for manufacturing a semiconductor device including a step of performing a heat treatment in an atmosphere containing NO, N ₂ O, or NO ₂ between the steps.   21. The method for manufacturing a semiconductor device according to claim 6, further comprising a step of cleaning the surface of the semiconductor substrate.   23. The method for manufacturing a semiconductor device according to claim 22, wherein the cleaning process of the surface of the semiconductor substrate includes an oxidation treatment.   24. The method for manufacturing a semiconductor device according to claim 22 or 23, wherein the step of cleaning the surface of the semiconductor substrate includes an ozone exposure process involving irradiation with ultraviolet light.   In addition to the steps included in the method for manufacturing a semiconductor device according to claims 6 to 24, a step of forming an interlayer insulating film, a step of forming a wiring layer, and an insulating film for protecting the wiring layer are formed. A method for manufacturing a semiconductor device, which includes a step of applying activated deuterium to an interface between these films or layers.   A chamber in which a semiconductor substrate having a gate insulating film can be disposed at a predetermined position, a heating unit capable of adjusting the semiconductor substrate disposed at the predetermined position to a predetermined temperature, and a semiconductor substrate having the gate insulating film disposed at the predetermined position A thermal catalyst provided near the surface of the semiconductor substrate, a heating means for heating the thermal catalyst to a predetermined temperature, a vacuum exhaust system capable of reducing the pressure in the chamber, and a gas containing deuterium are introduced into the chamber. Equipped with a gas introduction system and a pressure adjustment mechanism for the gas containing deuterium in the chamber, the gas containing deuterium passes through the vicinity of the surface of the thermal catalyst and is generated by thermal catalysis on the surface of the heated thermal catalyst An activated deuterium is supplied to the surface of a semiconductor substrate.   27. The deuterium treatment apparatus according to claim 26, wherein the semiconductor substrate is a substrate selected from silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium aluminum arsenide, gallium phosphide, gallium nitride, aluminum nitride or diamond. A deuterium treatment apparatus, characterized in that there is.   28. The deuterium treatment apparatus according to claim 26 or 27, wherein the thermal catalyst is one metal selected from tungsten, molybdenum, tantalum, titanium, and vanadium, or an alloy containing these as a main component. Hydrogen treatment equipment.   29. The deuterium treatment apparatus according to claim 26, further comprising an apparatus for maintaining the temperature of the semiconductor substrate at 600 [deg.] C. or lower.   30. The deuterium treatment apparatus according to claim 26, further comprising an apparatus for heating the thermal catalyst body to a predetermined temperature of 1000 ° C. to 1800 ° C., wherein the gas containing deuterium is converted into the thermal catalyst body. A deuterium treatment apparatus that generates deuterium activated by thermal catalysis on a surface.   31. The deuterium treatment apparatus according to claim 26, further comprising a pressure adjusting mechanism for adjusting a gas pressure containing deuterium to 1 Pa to 100 Pa.   The deuterium treatment apparatus according to any one of claims 26 to 31, wherein activated deuterium generated from a gas containing deuterium by thermal catalysis on the surface of the thermal catalyst heated to high temperature is used for 1 minute ~ A deuterium treatment apparatus comprising a device for supplying a predetermined time of 3 hours. 33. The deuterium treatment apparatus according to claim 26, wherein the semiconductor substrate having the gate insulating film and the thermal catalyst are disposed at a predetermined distance of 10 mm to 120 mm. Deuterium treatment equipment.