JP2012038919A - Method for manufacturing silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a silicon carbide semiconductor device, which can improve a threshold voltage lowered by nitriding treatment.SOLUTION: A method for manufacturing a silicon carbide semiconductor device comprises: a nitriding treatment step for applying nitriding treatment to a silicon carbide substrate 2 with a gate insulating film 11 mainly composed of silicon dioxide formed on a silicon carbide drift layer 6 including a base region 7 and a source region 8; and a heat treatment step for heat-treating the silicon carbide substrate 2 in an atmosphere containing dinitrogen monoxide in a temperature from 600°C to 1000°C after the nitriding treatment step.

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device.

  Silicon carbide has excellent physical properties and enables the realization of a power device with high breakdown voltage and low loss. However, in the case of manufacturing a MOSFET (Metal Oxide Field Effect Transistor) using silicon carbide, when a gate insulating film made of silicon dioxide is formed on the silicon carbide layer, many interface states exist at the silicon carbide / silicon dioxide interface. It is formed. Due to the presence of such an interface state close to the conduction band, the channel mobility of the MOSFET becomes extremely smaller than the electron mobility in the bulk, and the on-resistance value becomes higher than an ideal value. In a conventional method for manufacturing a silicon carbide semiconductor device, nitriding is performed by heat treatment in a nitrogen monoxide atmosphere in order to reduce the interface state at the silicon carbide / silicon dioxide interface as described above. (For example, see Non-Patent Document 1)

G.Y.Chung et al., “Interface state density and channel mobility for 4H-SiC MOSFETs with nitrogen passivation”, Applied Surface Science 184 (2001) 399-403.

  In such a method for manufacturing a silicon carbide semiconductor device, the channel mobility can be increased by nitriding, but at the same time the threshold voltage decreases. Although lowering the threshold voltage itself is preferable from the viewpoint of low-voltage driving, when a silicon carbide semiconductor device is used as a power device, it is necessary to ensure high withstand voltage characteristics. Threshold voltage is required. For example, when the above nitridation process is performed in a semiconductor device having a relatively complicated structure such as a storage channel MOSFET, there is a problem in that the threshold voltage becomes too low and the withstand voltage may not be secured.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a method for manufacturing a silicon carbide semiconductor device capable of improving the threshold voltage reduced by nitriding.

  A method for manufacturing a silicon carbide semiconductor device according to the present invention includes a nitriding treatment step of nitriding a substrate on which a gate insulating film mainly composed of silicon dioxide is formed on a silicon carbide layer, and after the nitriding treatment step, And a heat treatment step in which heat treatment is performed at a temperature of 600 ° C. to 1000 ° C. in an atmosphere containing dinitrogen monoxide.

  According to the method for manufacturing a silicon carbide semiconductor device according to the present invention, the threshold voltage reduced by the nitriding treatment can be improved.

It is sectional drawing which shows the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is a figure which shows the temperature profile of the nitriding treatment process and heat treatment process in Embodiment 1 of this invention. It is a graph which shows the relationship between the processing time in the heat treatment process in Embodiment 1 of this invention, and the increase amount of a threshold voltage. It is a graph which shows the relationship between the process temperature in the heat treatment process in Embodiment 1 of this invention, and the increase amount of a threshold voltage. It is a graph which shows the relationship between a gate voltage when a nitriding process only is performed, and when a nitriding process and a heat treatment process in Embodiment 1 of the present invention are performed. It is a graph which shows the relationship between the gate voltage and the drain current when the threshold voltage is controlled by the doping concentration of the channel layer and when the threshold voltage is controlled by the heat treatment process in the first embodiment of the present invention. It is sectional drawing which shows the silicon carbide semiconductor device in Embodiment 2 of this invention.

Embodiment 1 FIG.
First, the structure of silicon carbide semiconductor device 1a manufactured by the method for manufacturing a silicon carbide semiconductor device in the first embodiment of the present invention will be described. 1 is a cross sectional view showing a silicon carbide semiconductor device 1a according to the first embodiment of the present invention. Here, an n-channel silicon carbide MOSFET will be described as an example of silicon carbide semiconductor device 1a.

  In FIG. 1, an n-type (first conductivity type) silicon carbide drift layer 6 is formed on one surface 3 of an n-type (first conductivity type) and low resistance silicon carbide substrate 2. On the surface side of silicon carbide drift layer 6, p-type (second conductivity type) base regions 7 are formed at predetermined intervals from each other. An n-type (first conductivity type) source region 8 is formed shallower than the base region 7 in the surface layer portion in each base region 7.

  A gate insulating film 11 is formed on the surface of silicon carbide drift layer 6 including base region 7 and source region 8 except for part of source region 8. Furthermore, a gate electrode 12 is formed on the gate insulating film 11 at a portion facing the region between the pair of source regions 8. A source electrode 13 is formed on the surface of the source region 8 where the gate insulating film 11 is not formed, and a drain electrode 17 is formed on the other surface 16 of the silicon carbide substrate 2.

  Next, a method for manufacturing silicon carbide semiconductor device 1a in the first embodiment of the present invention will be described. 2 to 7 are cross sectional views showing a part of a method for manufacturing silicon carbide semiconductor device 1a in the first embodiment of the present invention.

First, the plane orientation of one surface 3 is the (0001) plane, has a 4H polytype, and is n-type (first conductivity type) doped with an impurity of, for example, about 1 × 10 ¹⁹ cm ⁻³ and low resistance. The silicon carbide substrate 2 is prepared. Then, as shown in FIG. 2, an n-type (first conductivity type) of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ is formed on one surface 3 of the silicon carbide substrate 2 by a CVD (Chemical Vapor Deposition) method. The silicon carbide drift layer 6 having a thickness of 5 to 50 μm is epitaxially grown at an impurity concentration of By forming the silicon carbide drift layer 6 under such conditions, a vertical type high breakdown voltage MOSFET having a breakdown voltage of several hundred V to 3 kV or more can be realized.

  Next, a mask is formed on the surface of silicon carbide drift layer 6 with a resist, and p-type (second conductivity type) impurities are ion-implanted from the surface side of silicon carbide drift layer 6. As a result, a pair of p-type (second conductivity type) base regions 7 spaced apart from each other by a predetermined distance are formed in silicon carbide drift layer 6. A cross-sectional view after removing the resist is shown in FIG.

At this time, the p-type (second conductivity type) impurity to be ion-implanted is, for example, aluminum or boron, and the impurity concentration to be ion-implanted is in the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ^−3. The n-type (first conductivity type) impurity concentration of 6 is exceeded. The depth of ion implantation of the p-type (second conductivity type) impurity is set to about 0.5 to 3 μm so as not to exceed the thickness of the silicon carbide drift layer 6.

  Next, a mask is formed with a resist on the surface of silicon carbide drift layer 6, and n-type (first conductivity type) impurities are ion-implanted from the surface side of silicon carbide drift layer 6. As a result, n-type (first conductivity type) source regions 8 are formed in the surface layer portion in each base region 7. A cross-sectional view after removing the resist is shown in FIG.

At this time, the n-type (first conductivity type) impurity to be ion-implanted is, for example, nitrogen or phosphorus, and the impurity concentration to be ion-implanted is in the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ in the base region 7. The impurity concentration exceeds the p-type (second conductivity type) impurity concentration. In addition, the depth of ion implantation of n-type (first conductivity type) impurity is shallower than the thickness of the base region 7.

  Next, silicon carbide substrate 2 on which silicon carbide drift layer 6, base region 7 and source region 8 are formed is subjected to a heat treatment apparatus in an inert gas atmosphere such as argon, for example, in the range of 1300 to 1900 ° C. for 30 seconds. Perform high temperature annealing for ~ 1 hour. By this high temperature annealing, ion-implanted aluminum, nitrogen, and the like are electrically activated.

  Next, as shown in FIG. 5, the surface of silicon carbide drift layer 6 including base region 7 and source region 8 is thermally oxidized to form gate insulating film 11 of silicon dioxide having a desired thickness. The thickness of the gate insulating film 11 is 100 nm or less.

  Next, the silicon carbide substrate 2 on which the gate insulating film 11 has been formed is nitrided using a vertical heat treatment furnace, and then heat treated. These nitriding treatment step and heat treatment step will be described in detail later.

  Next, a polycrystalline silicon film having conductivity is formed on the gate insulating film 11 by a CVD method, and the gate electrode 12 is formed by patterning. As shown in FIG. 6, gate electrode 12 is patterned in such a shape that a pair of base region 7 and source region 8 are located at both ends, and silicon carbide drift layer 6 between base regions 7 is located in the center. . At this time, the gate electrode 12 desirably overlaps with the pair of source regions 8 in a range of, for example, 10 nm to 5 μm.

  Next, as shown in FIG. 7, the gate insulating film 11 in other portions is removed leaving the portion where the gate electrode 12 is formed and the periphery thereof.

  Next, as shown in FIG. 8, by partially removing the gate insulating film 11 in the previous step, the source electrode 13 is formed in a portion where the source region 13 is exposed on the surface. As the source electrode 13, an aluminum alloy or the like is used.

  Finally, drain electrode 17 is formed on the other surface 16 of silicon carbide substrate 2 to complete n-channel MOSFET which is silicon carbide semiconductor device 1a in the first embodiment of the present invention shown in FIG. As the drain electrode 17, an aluminum alloy or the like is used.

  Next, the above-described nitridation process of silicon carbide substrate 2 after gate insulating film 11 is formed and the subsequent heat treatment process will be described in detail. FIG. 9 is a diagram showing temperature profiles of the nitriding process and the heat treatment process in the first embodiment of the present invention. In FIG. 9, the horizontal axis represents time, and the vertical axis represents the temperature in the furnace.

  First, the silicon carbide substrate 2 on which the gate insulating film 11 is formed is introduced into a vertical heat treatment furnace, and the inside of the furnace is evacuated to 1.3 Pa or less to remove the oxidizing gas in the furnace. Subsequently, an inert gas such as argon is supplied into the furnace so that the inside of the furnace is at atmospheric pressure. Next, the furnace is heated while supplying an inert gas into the furnace.

  When the furnace reaches a predetermined temperature at which nitriding is performed, nitrogen monoxide (NO) is supplied into the furnace and the nitriding process is started. The gas atmosphere in the furnace at the time of nitriding may be an atmosphere in which NO is almost 100%, or an atmosphere in which an inert gas such as argon and NO are mixed. The treatment temperature of the nitriding treatment is preferably 1100 ° C. or higher, and more preferably 1200 to 1300 ° C. The processing time may be adjusted according to the film thickness of the gate insulating film 11. For example, when the gate insulating film 11 has a film thickness of about 50 nm, it is sufficiently nitrided by processing at 1200 ° C. for 2 hours. The inside of the furnace is held at a predetermined temperature, and the nitriding process is finished when a predetermined time has elapsed.

  When the nitriding process is completed, the output of the furnace heater is reduced, and a first temperature lowering process is started to lower the temperature to a temperature at which the subsequent heat treatment process is performed. The gas atmosphere in the furnace during the first temperature lowering step may be an atmosphere in which NO is almost 100%, or an atmosphere in which an inert gas such as argon and NO are mixed. Moreover, inert gas atmosphere, such as argon, may be sufficient. When the temperature in the furnace decreases to the temperature at which the heat treatment process is performed, the first temperature lowering process is completed.

When the first temperature lowering step is completed, the gas supplied into the furnace is switched to dinitrogen monoxide (N ₂ O), and the heat treatment step is started. The gas atmosphere in the furnace during the heat treatment step may be an atmosphere containing almost 100% N ₂ O, or an atmosphere in which an inert gas such as argon and N ₂ O are mixed in order to improve controllability. Then, the temperature in the furnace is kept at a predetermined temperature for a certain time to perform heat treatment, and the heat treatment step is completed. The temperature at which the heat treatment step is performed is in the range of 600 to 1000 ° C., and the treatment time is appropriately determined so that a desired threshold voltage is obtained. The processing temperature and processing time will be described in detail later. After the first temperature lowering step, before the gas supplied to the furnace is switched to N ₂ O, the gas atmosphere in the furnace is replaced with an inert gas, or after being evacuated once and replaced with an inert gas. Thereafter, the gas to be supplied may be switched to N ₂ O to start the heat treatment step.

After the heat treatment process, a second temperature lowering process for lowering the temperature in the furnace to a predetermined standby temperature is started. The gas atmosphere in the furnace during the second temperature lowering step may be an atmosphere in which N ₂ O is almost 100%, or an atmosphere in which an inert gas such as argon and N ₂ O are mixed. When the temperature in the furnace falls to a predetermined standby temperature, the second temperature lowering process is terminated.

  Thereafter, after replacing the inside of the furnace with an inert gas, silicon carbide substrate 2 is taken out from the furnace. And it progresses to the process of forming the gate electrode 12 mentioned above.

Here, the processing temperature and processing time in the heat treatment step will be described. First, the processing temperature will be described. In the heat treatment step, N ₂ O causes the following reaction.

N ₂ O → N ₂ + O (1)
N ₂ O + O → N ₂ + O ₂ (2)
N ₂ O + O → 2NO (3)

The reaction of the above formula (1) is a slowly proceeding decomposition reaction of N ₂ O, and a large amount of atomic oxygen is generated. The reactions of the above formulas (2) and (3) are fast progressing reactions, and finally N ₂ , O ₂ and NO are generated. Since the reaction of the formula (3) is promoted as the temperature increases, the generated NO increases as the temperature increases. Below 1000 ° C., the ratio of NO to the total amount of N ₂ , O _2, and NO produced is 10% or less. EP Gusev et al., “Growth and characterization of ultrathin nitrided silicon oxide films”, IBM J. RES. DEVELOP. Vol. 43 No. 3 MAY 1999. (hereinafter referred to as “Non-Patent Document 2”).

That is, at a temperature higher than 1000 ° C., the generation ratio of NO increases, and the rate at which NO diffuses to the silicon carbide / silicon dioxide interface increases, so that nitriding is efficiently performed and the threshold voltage decreases. On the other hand, at a temperature of 1000 ° C. or lower, the rate of NO generation is low and the temperature is low, so the rate at which NO diffuses to the silicon carbide / silicon dioxide interface is reduced and nitriding is difficult. At this time, the reforming effect by the generated atomic oxygen is increased, and the threshold voltage can be increased. Since N ₂ O undergoes a decomposition reaction from about 600 ° C., the temperature at which the heat treatment step is performed is in the range of 600 to 1000 ° C.

  Next, experimental results obtained by performing the heat treatment step by changing the treatment time from 0 to 90 minutes in the treatment temperature range of 600 to 1000 ° C. will be described. FIG. 10 is a graph showing the relationship between the processing time and the increase amount of the threshold voltage in the heat treatment step according to Embodiment 1 of the present invention. In FIG. 10, the horizontal axis represents the processing time of the heat treatment step, and the vertical axis represents the amount of increase in threshold voltage due to the heat treatment step.

  As can be seen from FIG. 10, the increase amount of the threshold voltage is proportional to the processing time at any processing temperature. For this reason, the threshold voltage can be finely controlled by appropriately setting the processing temperature and the processing time.

At 600 ° C. at which the thermal decomposition reaction of N ₂ O begins to occur, the increase amount of the threshold voltage with respect to the processing time is small. Even at 1000 ° C. where the NO generation ratio starts to increase, the increase amount of the threshold voltage with respect to the processing time is small. Accordingly, from FIG. 10, temperatures of about 600 ° C. and about 1000 ° C. are suitable for controlling the threshold voltage in units of 0.1 to 0.2V.

  Further, at 700 ° C. or more and 800 ° C. or less, the increase amount of the threshold voltage with respect to the processing time is large as compared with the case of 600 ° C. or 1000 ° C. Therefore, from FIG. 10, the range of 700 to 800 ° C. is suitable for controlling the threshold voltage in units of 1V.

  FIG. 11 is a graph showing the relationship between the processing temperature and the increase amount of the threshold voltage in the heat treatment step according to Embodiment 1 of the present invention. In FIG. 11, the horizontal axis represents the processing temperature of the heat treatment step, and the vertical axis represents the amount of increase in the threshold voltage due to the heat treatment step. In FIG. 11, the processing time is 90 minutes. Also from FIG. 11, it can be seen that the effect of increasing the threshold voltage by the heat treatment step can be obtained efficiently in the processing temperature range of 600 to 1000 ° C.

  From FIG. 11, at a temperature of 600 ° C. or higher and lower than 700 ° C. and a temperature of 900 ° C. and lower than 1000 ° C., the increase amount of the threshold voltage is small and suitable for fine control of the threshold voltage. Further, about 600 ° C. and about 1000 ° C. are more suitable for fine control of the threshold voltage. Further, at a temperature of 700 ° C. or higher and 900 ° C. or lower, the increase amount of the threshold voltage is large, which is suitable when the threshold voltage is changed greatly. Furthermore, a temperature of 700 ° C. or higher and 800 ° C. or lower is more preferable when the threshold voltage is greatly changed.

  Next, when the MOSFET is manufactured by performing only the nitriding process, and when the MOSFET is manufactured by performing the nitriding process and the heat treatment process according to the method for manufacturing silicon carbide semiconductor device 1a in the first embodiment of the present invention. The experimental results comparing the above will be described. FIG. 12 is a graph showing the relationship between the gate voltage and the drain current when only the nitriding process is performed and when the nitriding process and the heat treatment process in the first embodiment of the present invention are performed. In FIG. 12, the horizontal axis represents the gate voltage, and the vertical axis represents the drain current. Here, the heat treatment step was performed at 800 ° C. for 1 hour.

  From FIG. 12, it can be seen that the threshold voltage is increased by about 4 V by the heat treatment process. In addition, it was confirmed that there was no abnormality such as an insulating film leak and the operation was normal.

  In general, the threshold voltage is controlled by adjusting the doping concentration of the layer in which the channel is formed. However, in this method, the influence of scattering due to impurities, interface defects and the like increases, and the channel mobility greatly decreases. That is, in the control of the threshold voltage by the doping concentration of the channel layer, the threshold voltage and the channel mobility are in a trade-off relationship.

  Next, experimental results comparing the above-described control of the threshold voltage by the channel layer doping concentration and the control of the threshold voltage by the heat treatment process in Embodiment 1 of the present invention will be described. FIG. 13 shows the relationship between the gate voltage and the drain current when the threshold voltage is controlled by the doping concentration of the channel layer and when the threshold voltage is controlled by the heat treatment process in the first embodiment of the present invention. It is a graph. In FIG. 13, the horizontal axis represents the gate voltage, and the vertical axis represents the drain current. Here, the case where the threshold voltage is set to 9 V in the above two methods is shown.

  From FIG. 13, when the threshold voltage is controlled by the heat treatment process according to the first embodiment of the present invention, the drain current with respect to the same gate voltage is compared with the case where the threshold voltage is controlled by the doping concentration of the channel layer. It can be seen that the channel mobility is large. Therefore, it can be seen that the method using the heat treatment process in the first embodiment of the present invention is superior to the conventional method using the channel layer doping concentration.

  In the first embodiment of the present invention, as described above, the threshold voltage reduced by the nitriding process can be improved by the heat treatment process. Compared with the conventional method of controlling the threshold voltage according to the doping concentration of the channel layer, a larger channel mobility can be ensured. It is also possible to finely control the threshold voltage by adjusting the processing temperature and processing time in the heat treatment process.

  Furthermore, the controllability of the threshold voltage can be improved by performing the heat treatment step at a predetermined temperature for a predetermined time.

  In addition, by performing the nitriding treatment step at a temperature of 1100 ° C. or higher in an atmosphere containing NO, the nitriding treatment can be performed efficiently and the channel mobility can be improved efficiently.

  After the nitriding step, the first temperature drop step is performed to lower the temperature in an atmosphere containing NO to the temperature at which the heat treatment step is performed, so that nitrogen is desorbed from the portion nitrided in the nitridation step during the first temperature drop step. It is possible to suppress the decrease in channel mobility due to nitrogen desorption.

In addition, by providing the second temperature lowering step for lowering the temperature in an atmosphere containing N ₂ O to a predetermined standby temperature after the heat treatment step, the threshold voltage improved by the heat treatment step is reduced during the second temperature lowering step. Can be suppressed.

By performing the heat treatment step in an N ₂ O atmosphere, the time required for the heat treatment step can be shortened as compared with the case where the heat treatment step is performed in an atmosphere in which an inert gas such as argon and N ₂ O are mixed.

  In addition, since the gate insulating film 11 is formed of silicon dioxide, the gate insulating film 11 can be formed by thermal oxidation, and the gate insulating film 11 can be easily formed.

  In the first embodiment of the present invention, the heat treatment step is performed at a predetermined temperature for a predetermined time. However, the heat treatment step may be performed while lowering the temperature, raising the temperature, or giving the temperature a change over time. For example, when the temperature is lowered, the time required for the second temperature lowering step can be shortened. The heat treatment process while lowering the temperature is not suitable for increasing the threshold voltage by a value smaller than 1V, but there is no problem when increasing the voltage by 1V or more.

  Moreover, in Embodiment 1 of this invention, the nitriding process was performed at 1100 degreeC or more. However, the temperature is not necessarily 1100 ° C. or higher, and a temperature lower than 1100 ° C. is possible.

  Furthermore, in the first embodiment of the present invention, the nitriding process is carried out at a predetermined temperature for a predetermined time. However, the nitriding process may be performed while lowering the temperature, raising the temperature, or changing the temperature over time.

In Embodiment 1 of the present invention, the nitriding process is performed in an atmosphere containing NO. However, it may be performed in an atmosphere containing N ₂ O or in an atmosphere containing ammonia (NH ₃ ), or nitriding may be performed by nitrogen atoms activated by plasma or ultraviolet rays. However, when the nitriding process is performed in an atmosphere containing N ₂ O, from the above-mentioned Non-Patent Document 2, the ratio of NO generated at 1000 ° C. or lower is low, and nitriding cannot be performed efficiently. It is preferable to perform the nitriding step at 1100 ° C. or higher where the generation ratio of is increased.

  In the first embodiment of the present invention, the gate insulating film 11 is formed by thermal oxidation. However, it may be formed by CVD method, vapor deposition method, sputtering method, ion cluster beam method, molecular beam epitaxy method or the like.

  Further, although the gate insulating film 11 is formed of silicon dioxide, a laminated structure in which silicon nitride and silicon dioxide are combined may be used, for example, as long as silicon dioxide is the main component.

  In the first embodiment of the present invention, the gate electrode 12 is formed of polycrystalline silicon. However, the conductivity type of the polycrystalline silicon may be n-type or p-type, and may be n-type or p-type polycrystalline silicon carbide. Furthermore, aluminum, titanium, molybdenum, tantalum, niobium, tungsten, and nitrides thereof may be used. Further, although the source electrode 13 and the drain electrode 17 are made of aluminum, the material used for the gate electrode 12 may be used.

  In Embodiment 1 of the present invention, silicon carbide substrate 2 having a plane orientation of one surface 3 of (0001) and having a 4H polytype is used. However, the plane orientation may be a (000-1) plane, a (11-20) plane, etc., or may be inclined from these plane orientations. Further, the polytype may be 6H or 3C.

  In the first embodiment of the present invention, as an example of silicon carbide semiconductor device 1a, an n-channel silicon carbide MOSFET has been described in which n-type is the first conductivity type and p-type is the second conductivity type. However, the same applies to a p-channel silicon carbide MOSFET in which the p-type is the first conductivity type and the n-type is the second conductivity type.

Embodiment 2. FIG.
FIG. 14 is a cross sectional view showing a silicon carbide semiconductor device 1b according to the second embodiment of the present invention. In FIG. 14, the same reference numerals as those in FIG. 1 denote the same or corresponding components, and the description thereof is omitted. This embodiment is different from the first embodiment in that it is a MOSFET having a trench structure.

  In FIG. 14, an n-type (first conductivity type) silicon carbide drift layer 6 is formed on one surface 3 of n-type (first conductivity type) and low resistance silicon carbide substrate 2. A p-type (second conductivity type) base region 7 is formed by ion implantation on the surface side of the silicon carbide drift layer 6, and an n-type (first conductivity type) source region 8 is formed on the surface layer in the base region 7. Is formed shallower than the base region 7 by ion implantation.

  Silicon carbide drift layer 6 has a trench that penetrates source region 8 and base region 7 from the surface of silicon carbide drift layer 6 to reach silicon carbide drift layer 6 in which source region 8 and base region 7 are not formed. 18 is formed. A gate insulating film 11 is formed on part of the surface of the source region 8 and the surface of the trench 18. A source electrode 13 is formed on the surface of the source region 8 where the gate insulating film 11 is not formed, and a drain electrode 17 is formed on the other surface 16 of the silicon carbide substrate 2.

  Next, a method for manufacturing silicon carbide semiconductor device 1b in the first embodiment of the present invention will be described.

  First, an n-type (first conductivity type) low-resistance silicon carbide substrate 2 is prepared, and an n-type (first conductivity type) silicon carbide drift layer 6 is epitaxially grown on one surface 3. Next, p-type (second conductivity type) impurities are ion-implanted from the surface side of silicon carbide drift layer 6 to form p-type (second conductivity type) base region 7. Next, an n-type (first conductivity type) impurity is ion-implanted from the surface side of the silicon carbide drift layer 6, and an n-type (first conductivity type) source region 8 is formed in the surface layer portion in the base region 7. It is formed. Next, in order to electrically activate the ion-implanted aluminum or nitrogen, the silicon carbide substrate 2 on which the silicon carbide drift layer 6, the base region 7 and the source region 8 are formed is placed in an inert gas atmosphere. Perform high-temperature annealing.

  Next, a trench that penetrates silicon carbide drift layer 6 from the surface of silicon carbide drift layer 6 to source region 8 and base region 7 and reaches silicon carbide drift layer 6 in which source region 8 and base region 7 are not formed. 18 is formed. Then, the gate insulating film 11 is formed on the surface of the source region 8 and the surface of the trench 18 by thermal oxidation.

  Next, a nitriding treatment process and a heat treatment process are performed on silicon carbide substrate 2 after gate insulating film 11 is formed. The conditions of the nitriding process and the heat treatment process are the same as in the first embodiment of the present invention.

  Next, a gate electrode is formed on the gate insulating film 11 formed on the surface of the trench 18. Next, the gate insulating film 11 at other portions is removed while leaving the gate insulating film 11 formed on a part of the surface of the source region 8 and the surface of the trench 18. Next, by partially removing the gate insulating film 11 in the previous step, the source electrode 13 is formed in a portion where the source region 13 is exposed on the surface. Finally, drain electrode 17 is formed on the other surface 16 of silicon carbide substrate 2 to complete silicon carbide semiconductor device 1b in the second embodiment of the present invention shown in FIG.

  Also in the trench structure silicon carbide MOSFET as the silicon carbide semiconductor device 1b in the second embodiment of the present invention as described above, the nitriding treatment process and the heat treatment process are performed after the gate insulating film 11 is formed. The same effect as in the first embodiment can be obtained.

  In the second embodiment of the present invention, a silicon carbide MOSFET having a trench structure in which n-type is the first conductivity type and p-type is the second conductivity type has been described as an example of silicon carbide semiconductor device 1b. However, the same applies to a silicon carbide MOSFET having a trench structure in which the p-type is the first conductivity type and the n-type is the second conductivity type.

  In the second embodiment of the present invention, a silicon carbide MOSFET having a trench structure has been described as an example of silicon carbide semiconductor device 1b. However, the present invention is not limited to this, and a similar effect can be obtained by performing a nitriding treatment process and a heat treatment process after forming the gate insulating film 11 in a silicon carbide IGBT (Insulated Gate Bipolar Transistor).

  In the second embodiment of the present invention, portions different from the first embodiment of the present invention are described, and descriptions of the same or corresponding portions are omitted.

  The first and second embodiments of the present invention have been described above. These configurations described in the first and second embodiments of the present invention can be combined with each other.

1a, 1b Silicon carbide semiconductor device 2 Silicon carbide substrate 6 Silicon carbide drift layer 7 Base region 8 Source region 11 Gate insulating film

Claims (10)

A nitriding treatment step of nitriding a substrate on which a gate insulating film mainly composed of silicon dioxide is formed on a silicon carbide layer;
A heat treatment step of heat-treating the substrate at a temperature of 600 ° C. or higher and 1000 ° C. or lower in an atmosphere containing dinitrogen monoxide after the nitriding step;
A method for manufacturing a silicon carbide semiconductor device comprising:   The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the heat treatment step is performed by holding at a first predetermined temperature for a predetermined time.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the nitriding step is performed in an atmosphere containing nitrogen monoxide, dinitrogen monoxide, or ammonia.   The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein the nitriding step is performed at a temperature of 1100 ° C. or higher.   5. The silicon carbide semiconductor device according to claim 4, further comprising a first temperature lowering step of lowering the temperature in an atmosphere containing nitrogen monoxide, dinitrogen monoxide, or ammonia to a temperature at which the heat treatment step is performed after the nitriding step. Manufacturing method.   The carbonization according to any one of claims 1 to 5, further comprising a second temperature lowering step of lowering the temperature in an atmosphere containing dinitrogen monoxide to a second predetermined temperature after the heat treatment step. A method for manufacturing a silicon semiconductor device.   The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the heat treatment step is performed in a dinitrogen monoxide atmosphere.   8. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the gate insulating film is made of silicon dioxide.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the heat treatment step is performed at a temperature of 700 ° C. or higher and 900 ° C. or lower.   9. The silicon carbide semiconductor device according to claim 1, wherein the heat treatment step is performed at a temperature of 600 ° C. or higher and lower than 700 ° C. or higher than 900 ° C. and 1000 ° C. or lower. Production method.

Images