CN110783411A - Gallium nitride based MOSFET device based on trench gate vertical shallow super junction and manufacturing method - Google Patents
Gallium nitride based MOSFET device based on trench gate vertical shallow super junction and manufacturing method Download PDFInfo
- Publication number
- CN110783411A CN110783411A CN201911060261.1A CN201911060261A CN110783411A CN 110783411 A CN110783411 A CN 110783411A CN 201911060261 A CN201911060261 A CN 201911060261A CN 110783411 A CN110783411 A CN 110783411A
- Authority
- CN
- China
- Prior art keywords
- layer
- thickness
- drift
- grid
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 51
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 42
- 238000000034 method Methods 0.000 claims abstract description 42
- 230000008569 process Effects 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000002161 passivation Methods 0.000 claims abstract description 26
- 230000015556 catabolic process Effects 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- 238000000151 deposition Methods 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 31
- 238000006243 chemical reaction Methods 0.000 claims description 28
- 239000010936 titanium Substances 0.000 claims description 26
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 25
- 239000010931 gold Substances 0.000 claims description 20
- 238000005229 chemical vapour deposition Methods 0.000 claims description 17
- 229910052719 titanium Inorganic materials 0.000 claims description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 15
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 13
- 239000001257 hydrogen Substances 0.000 claims description 13
- 229910052739 hydrogen Inorganic materials 0.000 claims description 13
- 229910052737 gold Inorganic materials 0.000 claims description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 239000013077 target material Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000003344 environmental pollutant Substances 0.000 claims description 3
- 231100000719 pollutant Toxicity 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000011133 lead Substances 0.000 claims 1
- 150000002739 metals Chemical class 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 229910000889 permalloy Inorganic materials 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 1
- 239000010937 tungsten Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 3
- 230000005669 field effect Effects 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 229910021529 ammonia Inorganic materials 0.000 description 12
- 238000000137 annealing Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 238000007781 pre-processing Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000013590 bulk material Substances 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 241000282414 Homo sapiens Species 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
Abstract
The invention discloses a gallium nitride-based MOSFET (metal oxide semiconductor field effect transistor) device based on a vertical shallow super junction of a trench gate, which mainly solves the problems of low breakdown voltage and concentrated electric field of a drift region in the prior art. The device comprises a substrate, a drift layer, a P-column layer, a P + layer, an n + layer, a gate dielectric layer, a source electrode, a drain electrode, a grid electrode and a passivation layer. The drift layer is positioned at the upper part of the substrate, the P-column layer is positioned in the drift layer, the P + layer and the n + layer are sequentially arranged above two sides of the P-column layer, the gate dielectric layer is positioned at the upper part of the n + layer, the source electrode is positioned at two sides of the gate dielectric layer, and the drain electrode is positioned at the lower part of the substrate; the grid electrode is positioned on the upper part of the grid dielectric layer and adopts a groove structure, the groove is positioned among the drift layer, the P + layer and the n + layer, and the passivation layer is positioned between the grid electrode and the source electrode. The invention expands PN junction depletion region, reduces process complexity and leakage current, improves breakdown voltage and reliability of the device, and can be used as high power system and power electronic switch.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a gallium nitride-based MOSFET device which can be used for electric energy conversion of power electronic equipment and circuit control under high-voltage and high-current density.
Background
The high-power semiconductor device is applied to electric energy conversion of power electronic equipment and circuit control under high voltage and high current density, and with the increasingly reduced available environmental resources of human beings, the development of a novel power device with excellent performance and high conversion efficiency is one of effective schemes for effectively solving energy and environmental conflicts. For a high-power semiconductor device, the power quality factor of the high-power semiconductor device mainly depends on the breakdown voltage and the specific on-resistance of the device, but both of the devices often need to be optimized and designed comprehensively to effectively improve the performance of the power device. With the continuous development of the field of semiconductor power devices, the performance of the power devices is fundamentally changed from the first generation of Si materials to the second generation of GaAs materials. However, so far, the performance of semiconductor power devices made of traditional two-generation materials has approached the theoretical limit determined by the material properties. The third generation semiconductor broadband materials represented by GaN have the characteristics of high frequency, high power, radiation resistance, high saturated electron mobility and the like, and have excellent potential in the aspect of power electronics. Compared with the traditional transverse device, the vertical power device of the trench gate vertical MOSFETs device can improve the breakdown characteristic of the device only by increasing the thickness of the drift region of the device without sacrificing the transverse size of a chip, so that the vertical power device has high power density and is suitable for power electronic switching devices. The vertical devices with mature technical development at present mainly comprise a CAVET device and a trench gate MOSFET device, and the trench gate MOSFET device is developed more rapidly along with the improvement of a P-type GaN doping technology. Compared with a CAVET device, the trench gate MOSFET device is easier to realize an enhancement device, a current blocking layer in the CAVET device is not needed, an electric field is mainly concentrated in a body and is not easily influenced by an interface state, and the width of a current channel can reach a micron level. However, the activation rate of the P-type GaN hole of the trench gate MOSFET device is still low at present, so that a depletion region between a P + layer and a drift layer is limited by doping, the breakdown voltage of the device is low, the power quality factor of the device is influenced, and the high power performance of the trench gate MOSFET device is reduced.
Disclosure of Invention
The invention aims to provide a gallium nitride based MOSFET device based on a vertical shallow super junction of a trench gate and a manufacturing method thereof aiming at the defects of the prior device technology, so as to improve the breakdown characteristic of the device and improve the high output power performance of the device.
In order to achieve the purpose, the technical scheme of the invention is as follows:
1. a gallium nitride-based MOSFET device based on a vertical shallow super junction of a trench gate comprises a substrate, a drift layer, a P-column layer, a P + layer, an n + layer, a gate dielectric layer, a source electrode, a drain electrode, a grid electrode and a passivation layer. The drift layer is positioned at the upper part of the substrate, the P-column layer is positioned in the drift layer, the P + layer and the n + layer are sequentially arranged above two sides of the P-column layer, the gate dielectric layer is positioned at the upper part of the n + layer, the source electrode is positioned at two sides of the gate dielectric layer, and the drain electrode is positioned at the lower part of the substrate; the grid is positioned on the upper part of the grid dielectric layer, a groove structure is adopted, the groove is positioned among the drift layer, the P + layer and the n + layer, and the passivation layer is positioned between the grid and the source. The drift layer is provided with a P-column layer for expanding a PN junction depletion region and improving the breakdown voltage of the device.
Further, the gate electrode is characterized by adopting a groove structure.
Further, the substrate is made of a GaN bulk material.
Further characterized in that the P-pillar layer has a doping concentration of 10
16cm
-3～10
18cm
-3And a thickness not exceeding 1/2 a of the thickness of the drift region.
Further, it is characterized in that: the gate dielectric layer adopts SiN or SiO
2Or Al
2O
3Or HfO
2A medium.
Further, the passivation layer is made of SiN or SiO
2Or Al
2O
3Or HfO
2A medium.
2. A method for manufacturing a gallium nitride-based MOSFET device based on a trench gate vertical shallow super junction is characterized by comprising the following steps:
1) cleaning and pretreating the surface of the substrate to eliminate surface dangling bonds, and removing the dangling bonds at H
2Removing surface pollutants by heat treatment in an atmosphere reaction chamber at the temperature of 900-1200 ℃;
2) depositing GaN with the thickness of 5-20 mu m on the substrate after the heat treatment by adopting an MOCVD (metal organic chemical vapor deposition) process to be used as a drift layer of the device;
3) selectively etching the drift region, selecting a region to be etched and etching a window exposing the P-column layer, wherein the thickness of the etched window is not more than 1/2 of the thickness of the drift region;
4) epitaxial doping concentration at exposed window is 10
16cm
-3～10
18cm
-3A P-column layer of (a);
5) depositing a P + layer with the thickness of 100 nm-1000 nm on the drift region and the P-column layer by adopting an MOCVD (metal organic chemical vapor deposition) process, wherein the doping concentration of the P + layer is 10
18cm
-3～10
19cm
-3；
6) Depositing an n + layer with the thickness of 100 nm-1000 nm on the P + layer by adopting an MOCVD process, wherein the doping concentration of the n + layer is 10
18cm
-3～10
19cm
-3；
7) Manufacturing a mask, exposing a source electrode window by adopting an etching process, wherein the thickness of the source electrode window extends into 10-50 nm of the P + layer, depositing source electrode metal on the window to be deposited by adopting a magnetron sputtering process, and depositing drain electrode metal which is the same as that of the source electrode on the back side of the device;
8) manufacturing a mask, exposing a grid window by adopting an etching process, wherein the thickness of the grid window extends into 10-50 nm of a drift layer, depositing a grid dielectric layer on a grid window to be deposited, and then depositing grid metal on the grid dielectric layer;
9) placing the epitaxial wafer subjected to the steps into a PECVD reaction chamber, and carrying out passivation layer deposition;
10) and photoetching and etching the passivation layer of the gate electrode and the passivation layer of the source electrode to form a gate contact hole and a source contact hole, thereby finishing the manufacture of the device.
Compared with the prior art, the invention has the following advantages:
firstly, the P-column layer is deposited in the drift layer, so that the P-column layer and the drift layer have interaction, and PN junction depletion regions can be increased in the length direction and the width direction of the P-column layer, so that the phenomenon of electric field peak concentration in the drift layer is weakened, the breakdown voltage of the device is improved, and high output power is realized;
secondly, the thickness of the P-column layer deposited in the drift layer is not more than half of the thickness of the drift layer, so that the drift layers on two sides do not need to be completely etched, and the process cost is optimized and reduced;
thirdly, because the newly deposited P-column layer replaces the original part of the drift layer, the leakage current between the grid and the drain is reduced when the device is conducted, and the static power consumption of the vertical power device is further reduced.
Drawings
Fig. 1 is a structural diagram of a gallium nitride-based MOSFET device based on a trench-gate vertical shallow super junction according to the present invention.
Fig. 2 is a flow chart illustrating the fabrication of the device of fig. 1 according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and examples.
Referring to fig. 1, the gallium nitride-based MOSFET device with a trench gate vertical shallow super junction of the present invention includes a substrate 1, a drift layer 2, a P-column layer 3, a P + layer 4, an n + layer 5, a gate dielectric layer 6, a source 7, a drain 8, a gate 9, and a passivation layer 10. The drift layer 2 is positioned at the upper part of the substrate 1, the P-column layer 3 is positioned in the drift layer 2, a P + layer 4 and an n + layer 5 are sequentially arranged above two sides of the P-column layer 3, the gate dielectric layer 6 is positioned at the upper part of the n + layer, the source electrode 7 is positioned at two sides of the gate dielectric layer 6, and the drain electrode 8 is positioned at the lower part of the substrate 1; the grid electrode 9 is positioned on the upper part of the grid dielectric layer 6 and adopts a groove structure, the groove is positioned among the drift layer 2, the P + layer 4 and the n + layer 5, and the passivation layer 10 is positioned between the grid electrode 9 and the source electrode 7.
The substrate 1 is made of a GaN bulk material;
the drift layer 2 is made of GaN, and the thickness of the drift layer is 5-20 microns;
the P-column layer 3 is made of GaN, and the thickness of the P-column layer is 0.1-10 mu m;
the P + layer 4 is made of GaN, and the thickness of the GaN is 50-1000 nm;
the n + layer 5 is made of GaN, and the thickness of the n + layer is 50-500 nm;
the passivation layer 6 adopts SiN or SiO
2Or Al
2O
3Or HfO
2And the like;
the source electrode metal and the drain electrode metal are combined by adopting metal layers of Ti/Al or Ti/Al/Ni/Au or Ti/Al/Mo/Au, and the grid electrode metal is combined by adopting metal layers of Ni/Au/Ni or Ni/Au or W/Au or Mo/Au.
Referring to fig. 2, the invention manufactures a gallium nitride-based MOSFET device based on a trench gate vertical shallow super junction, and three embodiments are given as follows:
in example 1, a trench-gate vertical shallow super junction gallium nitride-based MOSFET with a gallium nitride substrate and a P-pillar layer having a thickness of 0.5 μm was fabricated.
Step 1, preprocessing for eliminating dangling bonds is carried out on the surface of the gallium nitride substrate.
1.1) putting the gallium nitride substrate into HF acid solution for soaking for 1min, then sequentially putting the gallium nitride substrate into acetone solution, absolute ethyl alcohol solution and deionized water for ultrasonic cleaning for 10min respectively, and drying the cleaned gallium nitride substrate by using nitrogen;
1.2) in H
2And (3) performing heat treatment at the temperature of 1000 ℃ in the atmosphere reaction chamber to remove surface pollutants.
And 2, manufacturing a drift layer.
And putting the pretreated gallium nitride substrate into a Metal Organic Chemical Vapor Deposition (MOCVD) system, and introducing a Ga source with the flow rate of 40 mu mol/min, hydrogen with the flow rate of 1200sccm and ammonia with the flow rate of 3000sccm into the chamber at the same time under the conditions that the pressure of the chamber is 20Torr and the temperature of the chamber is 900 ℃ to grow a GaN drift layer with the thickness of 5 mu m.
And 3, manufacturing the P-column layer.
Putting the sample after the above process into an RIE etching chamber, and simultaneously introducing CF with the flow rate of 20sccm
4And O at a flow rate of 2sccm
2Setting the process conditions of 5mT chamber pressure and 100W power, and etching a 0.5 mu m thick P-column layer window on the GaN drift layer;
putting the sample after the process into a metal organic chemical vapor deposition MOCVD system, controlling the pressure of a cavity at 20Torr and the temperature at 900 ℃, simultaneously introducing a Ga source with the flow of 10 mu mol/min, hydrogen with the flow of 1000sccm and ammonia with the flow of 3000sccm, and growing the doping concentration at 10 in a P-column layer window region
16cm
-3And a P-pillar layer with a thickness of 0.5 μm.
And 4, manufacturing a P + layer.
Simultaneously introducing Ga source with the flow rate of 10 mu mol/min, hydrogen with the flow rate of 1000sccm and ammonia with the flow rate of 2000sccm into the chamber, and growing GaN on the P-column layer and the drift layer with the thickness of 400nm and the doping concentration of 10nm
18cm
-3A thick P + layer.
And 5, manufacturing an n + layer.
Simultaneously introducing Ga source with the flow rate of 10 mu mol/min, hydrogen with the flow rate of 1000sccm and ammonia with the flow rate of 1000sccm into the chamber, and growing GaN on the P + layer with the thickness of 200nm and the doping concentration of 10
18cm
-3N + layer of (2).
And 6, manufacturing a source electrode and a drain electrode.
Putting the sample after the above process into an RIE etching chamber, and simultaneously introducing CF with the flow rate of 20sccm
4And O at a flow rate of 2sccm
2Setting the process conditions of 5mT pressure and 100W power, etching 0.61 μm thick source window on the n + layer and P + layer, placing in the magnetron sputtering reaction chamber, and maintaining the pressure of the reaction chamber at 8.8 × 10
-2Pa, depositing Ti/Al metal with the thickness of 30nm/100nm on a source electrode window by using aluminum and titanium target materials with the purity of 99.999 percent as a source electrode, and annealing for 30S at the high temperature of 830 ℃; then, using aluminum and titanium target materials with the purity of 99.999 percent at the lower part of the substrate, depositing metal Ti/Al with the thickness of 30nm/100nm respectively as a drain electrode, and annealing at the high temperature of 830 DEG CThe fire was 30S.
And 7, manufacturing a gate dielectric layer.
Putting the sample subjected to the process into the RIE etching chamber again, and introducing CF with the flow rate of 20sccm
4And O at a flow rate of 2sccm
2Controlling the process conditions of 5mT pressure and 100W power of the chamber, and etching a gate groove window with the thickness of 0.7 mu m on the n + layer, the P + layer and the drift layer;
putting the sample subjected to the process into a plasma chemical vapor deposition PECVD reaction chamber, and depositing Al with the thickness of 20nm on a grid groove window at the high temperature of 400 DEG C
2O
3And a gate dielectric layer.
And 8, manufacturing a grid electrode.
Placing the sample in a magnetron sputtering reaction chamber, and controlling the pressure in the reaction chamber to be 8.8 × 10
- 2Pa, depositing metal Ni/Au/Ni with the thickness of 45nm/200nm/200nm in a grid window by using nickel and gold target materials with the purity of 99.999 percent as a grid, and annealing for 30S at the high temperature of 830 ℃.
And 9, manufacturing a passivation layer.
And putting the sample subjected to the steps into a plasma chemical vapor deposition PECVD reaction chamber, and depositing a SiN passivation layer with the thickness of 20nm at the high temperature of 400 ℃.
And step 10, manufacturing source electrode contact holes and grid electrode contact holes.
And photoetching and etching the passivation layers on the source electrode and the grid electrode to form a source electrode contact hole and a grid electrode contact hole, and finishing the manufacture of the whole device.
Step 1, preprocessing for eliminating dangling bonds is carried out on the surface of the gallium nitride substrate.
The specific implementation of this step is the same as step 1 of example 1.
And 2, manufacturing a drift layer.
And putting the pretreated gallium nitride substrate into a Metal Organic Chemical Vapor Deposition (MOCVD) system, and introducing a Ga source with the flow rate of 40 mu mol/min, hydrogen with the flow rate of 1500sccm and ammonia with the flow rate of 3000sccm into the chamber at the same time under the conditions that the pressure of the chamber is 20Torr and the temperature is 900 ℃ to grow a GaN drift layer with the thickness of 6 mu m.
And 3, manufacturing the P-column layer.
Putting the sample after the above process into an RIE etching chamber, and simultaneously introducing CF with the flow rate of 20sccm
4And O at a flow rate of 2sccm
2Setting the process conditions of 5mT chamber pressure and 100W power, and etching a 1-micron thick P-column layer window on the GaN drift layer; placing the metal organic chemical vapor deposition MOCVD system into a metal organic chemical vapor deposition MOCVD system, controlling the pressure of a chamber to be 20Torr and the temperature to be 900 ℃, simultaneously introducing a Ga source with the flow rate of 10 mu mol/min, hydrogen with the flow rate of 2000sccm and ammonia with the flow rate of 3000sccm, and growing the doped concentration to be 5 multiplied by 10 in a P-column layer window area
16cm
-3And a P-pillar layer 1 μm thick.
And 4, manufacturing a P + layer.
Ga source with the flow rate of 20 mu mol/min, hydrogen with the flow rate of 1000sccm and ammonia with the flow rate of 2000sccm are simultaneously introduced into the chamber, and GaN with the thickness of 500nm and the doping concentration of 5 multiplied by 10 is grown on the P-column layer and the drift layer
18cm
-3P + layer of (2).
And 5, manufacturing an n + layer.
Ga source with the flow rate of 10 mu mol/min, hydrogen with the flow rate of 800sccm and ammonia with the flow rate of 1000sccm are simultaneously introduced into the chamber, and GaN grows on the P + layer with the thickness of 100nm and the doping concentration of 5 multiplied by 10
18cm
-3N + layer of
And 6, manufacturing a source electrode and a drain electrode.
Putting the sample after the above process into an RIE etching chamber, and simultaneously introducing CF with the flow rate of 20sccm
4And O at a flow rate of 2sccm
2Setting the process conditions of 5mT pressure and 100W power, etching 0.61 μm thick source window on the n + layer and P + layer, placing in the magnetron sputtering reaction chamber, and maintaining the pressure of the reaction chamber at 9.0 × 10
-2Pa, depositing Ti/Al metal with the thickness of 40nm/150nm on a source electrode window by using aluminum and titanium target materials with the purity of 99.999 percent as a source electrode, and then performing high-temperature treatment at 830 DEG CPerforming down annealing for 30S; and then, depositing metal Ti/Al with the thickness of 40nm/150nm as a drain electrode by using aluminum and titanium targets with the purity of 99.999 percent at the lower part of the substrate, and annealing for 30 seconds at the high temperature of 830 ℃.
And 7, manufacturing a gate dielectric layer.
Putting the sample subjected to the process into the RIE etching chamber again, and introducing CF with the flow rate of 20sccm
4And O at a flow rate of 2sccm
2Controlling the process conditions of 5mT pressure and 100W power of the chamber, and etching a gate groove window with the thickness of 0.7 mu m on the n + layer, the P + layer and the drift layer; then placing the silicon wafer into a plasma chemical vapor deposition PECVD reaction chamber, and depositing 10nm thick Al on a grid groove window at the high temperature of 400 DEG C
2O
3And a gate dielectric layer.
And 8, manufacturing a grid electrode.
Placing the sample in a magnetron sputtering reaction chamber, and controlling the pressure in the reaction chamber to be 8.8 × 10
- 2Pa, depositing metal Ti/Au with the thickness of 50nm/100nm in a grid window by using titanium and gold targets with the purity of 99.999 percent as a grid, and annealing for 30S at the high temperature of 830 ℃.
And 9, manufacturing a passivation layer.
And putting the sample subjected to the steps into a plasma chemical vapor deposition PECVD reaction chamber, and depositing a 25 nm-thick SiN passivation layer at the high temperature of 400 ℃.
And step 10, manufacturing source electrode contact holes and grid electrode contact holes.
And photoetching and etching the passivation layers on the source electrode and the grid electrode to form a source electrode contact hole and a grid electrode contact hole, and finishing the manufacture of the whole device.
Step 1, preprocessing for eliminating dangling bonds is carried out on the surface of the gallium nitride substrate.
The specific implementation of this step is the same as step 1 of example 1.
And 2, manufacturing a drift layer.
And putting the pretreated gallium nitride substrate into a Metal Organic Chemical Vapor Deposition (MOCVD) system, and introducing a Ga source with the flow rate of 60 mu mol/min, hydrogen with the flow rate of 2000sccm and ammonia with the flow rate of 4000sccm into the chamber at the same time under the conditions that the pressure of the chamber is 20Torr and the temperature of the chamber is 900 ℃ to grow a 10 mu m thick GaN drift layer.
And 3, manufacturing the P-column layer.
Putting the sample after the above process into an RIE etching chamber, and simultaneously introducing CF with the flow rate of 20sccm
4And O at a flow rate of 2sccm
2Setting the process conditions of 5mT chamber pressure and 100W power, and etching a 1.2 μm thick P-column layer window on the GaN drift layer;
putting the sample after the process into a metal organic chemical vapor deposition MOCVD system, controlling the pressure of a chamber to be 20Torr and the temperature to be 900 ℃, simultaneously introducing a Ga source with the flow rate of 20 mu mol/min, hydrogen with the flow rate of 3000sccm and ammonia with the flow rate of 3000sccm, and growing the doping concentration of 10 in a P-column layer window region
17cm
-3And a P-pillar layer 1.2 μm thick.
And 4, manufacturing a P + layer.
Ga source with the flow rate of 20 mu mol/min, hydrogen with the flow rate of 1400sccm and ammonia with the flow rate of 2000sccm are simultaneously introduced into the chamber, and a P + layer of GaN with the thickness of 550nm is grown on the P-column layer and the drift layer, and the doping concentration is 10
19cm
-3。
And 5, manufacturing an n + layer.
Simultaneously introducing a Ga source with the flow rate of 10 mu mol/min, hydrogen with the flow rate of 900sccm and ammonia with the flow rate of 1000sccm into the chamber, growing a n + layer of GaN with the thickness of 150nm on the P + layer, wherein the doping concentration is 10 mu mol/min
19cm
-3。
And 6, manufacturing a source electrode and a drain electrode.
Putting the sample after the above process into an RIE etching chamber, and simultaneously introducing CF with the flow rate of 20sccm
4And O at a flow rate of 2sccm
2Setting the process conditions of 5mT pressure and 100W power, etching 0.61 micron thick source window on the n + layer and the P + layer, placing the window in the magnetron sputtering reaction chamber, and keeping the pressure of the reaction chamber at 9.210
-2Pa, depositing Ti/Al metal with the thickness of 50nm/200nm on a source electrode window by using aluminum and titanium target materials with the purity of 99.999 percent as a source electrode, and annealing for 30S at the high temperature of 830 ℃;
and depositing metal Ti/Al with the thickness of 50nm/200nm as a drain electrode on the lower part of the substrate by using aluminum and titanium targets with the purity of 99.999 percent respectively, and annealing for 30 seconds at the high temperature of 830 ℃.
And 7, manufacturing a gate dielectric layer.
Putting the sample subjected to the process into the RIE etching chamber again, and introducing CF with the flow rate of 20sccm
4And O at a flow rate of 2sccm
2Controlling the process conditions of 5mT pressure and 100W power of the chamber, and etching a gate groove window with the thickness of 0.7 mu m on the n + layer, the P + layer and the drift layer; then placing the silicon substrate into a plasma chemical vapor deposition PECVD reaction chamber, and depositing Al with the thickness of 15nm on a grid groove window at the high temperature of 400 DEG C
2O
3And a gate dielectric layer.
And 8, manufacturing a grid electrode.
Placing the sample in a magnetron sputtering reaction chamber, and controlling the pressure in the reaction chamber to be 8.8 × 10
- 2Pa, depositing metal Ti/Pt/Au with the thickness of 60nm/100nm/200nm in a grid window by using titanium, platinum and gold targets with the purity of 99.999 percent as a grid, and annealing for 30S at the high temperature of 830 ℃.
And 9, manufacturing a passivation layer.
And putting the sample subjected to the steps into a plasma chemical vapor deposition PECVD reaction chamber, and depositing a 30 nm-thick SiN passivation layer at the high temperature of 400 ℃.
And step 10, manufacturing source electrode contact holes and grid electrode contact holes.
And photoetching and etching the passivation layers on the source electrode and the grid electrode to form a source electrode contact hole and a grid electrode contact hole, and finishing the manufacture of the whole device.
The above description is only three specific examples of the present invention, however, the present invention is not limited to the specific details in the above embodiments, and many simple modifications may be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications all fall within the protection scope of the present invention.
Claims (9)
1. A gallium nitride-based MOSFET device based on a vertical shallow super junction of a trench gate comprises a substrate (1), a drift layer (2), a P-column layer (3), a P + layer (4), an n + layer (5), a gate dielectric layer (6), a source electrode (7), a drain electrode (8), a grid electrode (9) and a passivation layer (10). The drift layer (2) is positioned at the upper part of the substrate (1), the P-column layer (3) is positioned in the drift layer (2), the P + layer (4) and the n + layer (5) are sequentially arranged above two sides of the P-column layer (3), the gate dielectric layer (6) is positioned at the upper part of the n + layer (5), the source electrode (7) is positioned at two sides of the gate dielectric layer (6), and the drain electrode (8) is positioned at the lower part of the substrate (1); the grid electrode (9) is positioned on the upper portion of the grid dielectric layer (6), a groove structure is adopted, the groove is positioned among the drift layer (2), the P + layer (4) and the n + layer (5), the passivation layer (10) is positioned between the grid electrode (9) and the source electrode (7), and the grid electrode structure is characterized in that the P-column layer (3) is arranged in the drift layer (2) and used for expanding a PN junction depletion region and improving the breakdown voltage of a device.
2. The device is characterized in that a P-column layer (3) is arranged in the drift layer (2) and used for expanding a PN junction depletion region and improving the breakdown voltage of the device.
3. The device of claim 1, wherein the gate electrode has a recessed structure.
4. Device according to claim 1, characterized in that the P-pillar layer (3) has a doping concentration of 10
16cm
-3～10
18cm
-3And a thickness not exceeding 1/2 the thickness of the drift region (2).
5. The device according to claim 1, characterized in that the gate dielectric layer (6) and the passivation layer (10) are made of SiN or SiO
2Or Al
2O
3Or HfO
2A medium.
6. A method for manufacturing a gallium nitride-based MOSFET device based on a trench gate vertical shallow super junction is characterized by comprising the following steps:
1) cleaning and pretreating the surface of the substrate to eliminate surface dangling bonds, and removing the dangling bonds at H
2Removing surface pollutants by heat treatment in an atmosphere reaction chamber at the temperature of 900-1200 ℃;
2) depositing GaN with the thickness of 5-20 mu m on the substrate after the heat treatment by adopting an MOCVD (metal organic chemical vapor deposition) process to be used as a drift layer of the device;
3) selectively etching the drift region, selecting a region to be etched and etching a window exposing the P-column layer, wherein the thickness of the etched window is not more than 1/2 of the thickness of the drift region;
4) epitaxial doping concentration at exposed window is 10
16cm
-3～10
18cm
-3A P-column layer of (a);
5) depositing a P + layer with the thickness of 100 nm-1000 nm on the drift region and the P-column layer by adopting an MOCVD (metal organic chemical vapor deposition) process, wherein the doping concentration of the P + layer is 10
18cm
-3～10
19cm
-3；
6) Depositing an n + layer with the thickness of 100 nm-1000 nm on the P + layer by adopting an MOCVD process, wherein the doping concentration of the n + layer is 10
18cm
-3～10
19cm
-3；
7) Manufacturing a mask, exposing a source electrode window by adopting an etching process, wherein the thickness of the source electrode window extends into 10-50 nm of the P + layer, depositing source electrode metal on the window to be deposited by adopting a magnetron sputtering process, and depositing drain electrode metal which is the same as that of the source electrode on the back side of the device;
8) manufacturing a mask, exposing a grid window by adopting an etching process, wherein the thickness of the grid window extends into 10-50 nm of a drift layer, depositing a grid dielectric layer on a grid window to be deposited, and then depositing grid metal on the grid dielectric layer;
9) placing the epitaxial wafer subjected to the steps into a PECVD reaction chamber, and carrying out passivation layer deposition;
10) and photoetching and etching the passivation layer of the gate electrode and the passivation layer of the source electrode to form a gate contact hole and a source contact hole, thereby finishing the manufacture of the device.
7. The method of claim 6, wherein: the MOCVD process parameters of the step 2), the step 4), the step 5) and the step 6) are as follows:
the pressure in the reaction chamber was: the temperature of the molten metal is 10 to 100Torr,
the Ga source flow is: 10-100 mu mol/min of the mixture,
the flow of ammonia gas is as follows: 800-6000sccm,
the hydrogen flow rate was: 1000-.
8. The method as claimed in claim 6, wherein the magnetron sputtering process in step 7) is performed under the condition that aluminum, titanium, nickel, permalloy, tungsten, lead and gold with a purity of 99.999% are used as the target material, and the pressure in the reaction chamber is kept within a range of 8.6 to 9.4 x 10
- 2Pa. And the source electrode metal deposited on the window to be deposited and the drain electrode metal on the back side adopt metal combination of Ti/Al or Ti/Al/Ni/Au or Ti/Al/Mo/Au.
9. The method of claim 7, wherein the gate metal deposited on the gate dielectric layer in step 8) is a combination of metals of Ni/Au/Ni or Ti/Au or Ti/Pt/Au, wherein the thickness of the first layer of metal Ni or Ti is 20to 80nm, the thickness of the second layer of metal Au or Pt is 50 to 300nm, and the thickness of the third layer of metal Ni or Au is 20to 300 nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911060261.1A CN110783411A (en) | 2019-11-01 | 2019-11-01 | Gallium nitride based MOSFET device based on trench gate vertical shallow super junction and manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911060261.1A CN110783411A (en) | 2019-11-01 | 2019-11-01 | Gallium nitride based MOSFET device based on trench gate vertical shallow super junction and manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110783411A true CN110783411A (en) | 2020-02-11 |
Family
ID=69388429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911060261.1A Pending CN110783411A (en) | 2019-11-01 | 2019-11-01 | Gallium nitride based MOSFET device based on trench gate vertical shallow super junction and manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110783411A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN205428936U (en) * | 2015-12-08 | 2016-08-03 | 北京华进创威电子有限公司 | Nitride -based insulated gate bipolar transistor |
| CN106486379A (en) * | 2015-09-02 | 2017-03-08 | 株式会社东芝 | The manufacture method of semiconductor device |
| US20190096991A1 (en) * | 2017-09-28 | 2019-03-28 | Toyoda Gosei Co., Ltd. | Method for manufacturing semiconductor device |
-
2019
- 2019-11-01 CN CN201911060261.1A patent/CN110783411A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106486379A (en) * | 2015-09-02 | 2017-03-08 | 株式会社东芝 | The manufacture method of semiconductor device |
| CN205428936U (en) * | 2015-12-08 | 2016-08-03 | 北京华进创威电子有限公司 | Nitride -based insulated gate bipolar transistor |
| US20190096991A1 (en) * | 2017-09-28 | 2019-03-28 | Toyoda Gosei Co., Ltd. | Method for manufacturing semiconductor device |
Non-Patent Citations (1)
| Title |
|---|
| QI ZHOU等: "A Novel Kilovolts GaN Vertical Superjunction MOSFET With Trench Gate: Approach for Device Design and Optimization", 《IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101252088B (en) | Realizing method of novel enhancement type AlGaN/GaN HEMT device | |
| CN102227000B (en) | Silicon carbide MOSFET device based on super junction and preparation method | |
| CN111916351A (en) | Semiconductor device and method for manufacturing the same | |
| CN102130160A (en) | Groove-shaped channel AlGaN/GaN-reinforced high electron mobility transistor (HEMT) component and manufacturing method thereof | |
| CN112038408B (en) | Vertical aluminum nitride metal oxide semiconductor field effect transistor based on silicon carbide substrate and preparation method | |
| CN110581068A (en) | Method for realizing low-on-resistance enhanced gallium nitride transistor by using gate dielectric | |
| CN103928344A (en) | Method for improving N-typed DiMOSFET channel mobility based on N-typed nanometer thin layer | |
| CN108258043A (en) | A kind of enhanced MOS HEMT devices of GaN base and preparation method thereof | |
| CN109494154A (en) | Improve the method and gallium nitride based electronic device of gallium nitride based electronic device reliability | |
| CN115472689A (en) | High-electron-mobility transistor with super junction structure and preparation method thereof | |
| CN110164976B (en) | Strain gallium oxide MOSFET device structure and preparation method | |
| CN109728087B (en) | Method for preparing low-ohmic contact GaN-based HEMT based on nanosphere mask | |
| CN106158960A (en) | GaN enhancement mode MOSFET and preparation method is formed based on digitized wet method grid lithographic technique | |
| CN112599603A (en) | Quasi-vertical field effect transistor based on longitudinal Schottky source tunneling junction and method | |
| CN110676172B (en) | Method for realizing low on-resistance enhanced gallium nitride transistor | |
| CN110911485A (en) | Enhanced bidirectional blocking power GaN-based device based on P-type layer and manufacturing method | |
| CN114121655B (en) | Self-termination etching method and device based on enhanced device | |
| CN112614889A (en) | All-vertical field effect transistor based on longitudinal Schottky source tunneling junction and method | |
| CN112614888A (en) | Quasi-vertical field effect transistor based on transverse Schottky source tunneling junction and method | |
| CN110783411A (en) | Gallium nitride based MOSFET device based on trench gate vertical shallow super junction and manufacturing method | |
| CN112614890A (en) | All-vertical field effect transistor based on transverse Schottky source tunneling junction and method | |
| CN114725214A (en) | Multilayer passivation groove gate MIS-HEMT device and preparation method thereof | |
| CN114156339A (en) | Bidirectional blocking HEMT based on composite channel structure and preparation method thereof | |
| CN111063739A (en) | Based on SiO2Aluminum nitride CAVET device of current blocking layer and manufacturing method | |
| CN111613669A (en) | AlGaN high electron mobility transistor with high breakdown voltage and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200211 |
|
| RJ01 | Rejection of invention patent application after publication |