JP4549287B2 - Semiconductor module - Google Patents

Semiconductor module Download PDF

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JP4549287B2
JP4549287B2 JP2005353247A JP2005353247A JP4549287B2 JP 4549287 B2 JP4549287 B2 JP 4549287B2 JP 2005353247 A JP2005353247 A JP 2005353247A JP 2005353247 A JP2005353247 A JP 2005353247A JP 4549287 B2 JP4549287 B2 JP 4549287B2
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metal
semiconductor
plate
base plate
insulating
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JP2007158156A (en
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直樹 吉松
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Mitsubishi Electric Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、半導体モジュールに関するものであり、特に、発熱量が大きい半導体素子を用いた半導体モジュールに関する。   The present invention relates to a semiconductor module, and more particularly, to a semiconductor module using a semiconductor element that generates a large amount of heat.

発熱量が大きい、例えば電力用半導体素子を用いた半導体モジュールにおいて、はんだ部材(接合部材)に亀裂が発生することがある。これは、熱膨張率が大きく異なる部材同士を接合しているはんだ部材に起こりやすい。半導体モジュールが駆動や停止を繰り返すと、はんだ部材によって接合されている部材がそれぞれの熱膨張率に対応して熱膨張や熱収縮を繰り返し、その熱膨張量差や熱収縮量差に対応する応力がはんだ部材に発生して亀裂が生じる。特に、亀裂は、応力によるひずみ量が大きいはんだ部材の周縁部で発生しやすい。亀裂が発生するとはんだ部材の熱伝導性が低下し、その結果、半導体モジュールの放熱効率が低下して寿命が短くなる。   In a semiconductor module that generates a large amount of heat, for example, a power semiconductor element, a crack may occur in the solder member (joining member). This is likely to occur in a solder member that joins members having greatly different coefficients of thermal expansion. When the semiconductor module is repeatedly driven and stopped, the member joined by the solder member repeats thermal expansion and contraction corresponding to each thermal expansion coefficient, and the stress corresponding to the difference in thermal expansion and thermal contraction Is generated in the solder member to cause a crack. In particular, cracks are likely to occur at the periphery of a solder member having a large strain due to stress. When cracks occur, the thermal conductivity of the solder member decreases, and as a result, the heat dissipation efficiency of the semiconductor module decreases and the life is shortened.

はんだ部材における亀裂の発生(発生後の亀裂の進展も含む)を抑制した半導体モジュールとして、特許文献1のものがある。図4は、特許文献1の半導体モジュールを示している。図に示すように、半導体モジュール510は、主面と裏面の両面に金属パターン512、514が形成された絶縁基板516と該主面の金属パターン512にはんだ部材524で接合される半導体素子518とからなる半導体実装基板520と、絶縁基板516の裏面の金属パターン514を介して半導体実装基板520が接合される金属ベース板522と、これらを接合するはんだ部材526とを有する。   There exists a thing of patent document 1 as a semiconductor module which suppressed generation | occurrence | production of the crack in a solder member (including progress of the crack after generation | occurrence | production). FIG. 4 shows the semiconductor module of Patent Document 1. As shown in the drawing, the semiconductor module 510 includes an insulating substrate 516 having metal patterns 512 and 514 formed on both the main surface and the back surface, and a semiconductor element 518 bonded to the metal pattern 512 on the main surface with a solder member 524. A semiconductor mounting substrate 520, a metal base plate 522 to which the semiconductor mounting substrate 520 is bonded via the metal pattern 514 on the back surface of the insulating substrate 516, and a solder member 526 for bonding them.

半導体素子518から発生した熱は、はんだ部材524を介して主面の金属パターン512に伝わり、続いて順に、絶縁基板516、裏面の金属パターン514、はんだ部材526、金属ベース板522と伝わり、金属ベース板522から外気に放熱される。   The heat generated from the semiconductor element 518 is transferred to the metal pattern 512 on the main surface via the solder member 524, and is then transferred to the insulating substrate 516, the metal pattern 514 on the back surface, the solder member 526, and the metal base plate 522 in order. Heat is radiated from the base plate 522 to the outside air.

半導体モジュール510は、はんだ部材526の周縁部528における亀裂の発生を抑えるために、半導体モジュール510の構成要素の積層方向から見た場合、裏面の金属パターン514の周縁が絶縁基板516の周縁より外側に位置するように構成されている。すなわち、裏面の金属パターン514の周縁部530が絶縁基板516に接合されておらず、そのため、周縁部530は、絶縁基板516に妨害されることなく、金属の熱膨張率で熱膨張や熱収縮することができる(絶縁基板516に接合されている場合、金属パターン514は、金属の熱膨張率で膨張または収縮できず、金属より小さく絶縁基板516に近い熱膨張率で熱膨張または熱収縮する。)。したがって、裏面の金属パターン514の周縁部530と金属ベース板522に挟まれたはんだ部材526の周縁部528に発生する応力は、裏面の金属パターン514と金属ベース板522が金属の熱膨張率で膨張または収縮し、またその膨張量差または収縮量差が小さい(絶縁基板と金属の差に比べて小さい)ことから小さくなる。その結果、応力によるひずみ量も小さくなり、はんだ部材526の周縁部528における亀裂の発生および進展が抑制される。   When the semiconductor module 510 is viewed from the stacking direction of the components of the semiconductor module 510 in order to suppress the occurrence of cracks in the peripheral portion 528 of the solder member 526, the peripheral edge of the metal pattern 514 on the back surface is outside the peripheral edge of the insulating substrate 516. It is comprised so that it may be located in. That is, the peripheral portion 530 of the metal pattern 514 on the back surface is not bonded to the insulating substrate 516, and therefore, the peripheral portion 530 is not disturbed by the insulating substrate 516 and is thermally expanded or contracted by the thermal expansion coefficient of the metal. (When bonded to the insulating substrate 516, the metal pattern 514 cannot expand or contract with the coefficient of thermal expansion of the metal, but expands or contracts with a coefficient of thermal expansion smaller than that of the metal and close to the insulating substrate 516. .) Therefore, the stress generated in the peripheral portion 530 of the solder member 526 sandwiched between the peripheral portion 530 of the metal pattern 514 on the back surface and the metal base plate 522 is the coefficient of thermal expansion of the metal pattern 514 and the metal base plate 522 on the back surface. The expansion or contraction is small, and the difference in expansion or contraction is small (small compared to the difference between the insulating substrate and the metal), and thus becomes small. As a result, the amount of strain due to stress is also reduced, and the generation and propagation of cracks at the peripheral edge 528 of the solder member 526 is suppressed.

特開2000−101203公報JP 2000-101203 A

しかしながら、半導体モジュールの規模拡大や回路構成などから、上記の半導体実装基板が複数存在して金属ベース板を共通化するような場合、すなわち、単一の金属ベース板に、複数の半導体実装基板をはんだ接合する場合、周縁が絶縁基板より外側に位置する裏面の金属パターンを各半導体実装基板について備える必要があるだけでなく、加えて、実装における位置決め精度が良くないため、各半導体実装基板同士が接触しないように所定の間隔(余裕)を設けて金属ベース板に配置、接合しなければならず、半導体実装基板の設置面積は複数の半導体実装基板の面積を単純に合計した以上に大きくなる。そのため、複数の半導体実装基板と単一の金属ベース板からなる半導体モジュールは大型化する。   However, due to the expansion of the scale of the semiconductor module, the circuit configuration, etc., when a plurality of the above-described semiconductor mounting substrates exist and the metal base plate is shared, that is, a plurality of semiconductor mounting substrates are provided on a single metal base plate. When soldering, not only is it necessary to provide each semiconductor mounting board with a metal pattern on the back surface, the periphery of which is located outside the insulating board, but in addition, the positioning accuracy in mounting is not good, It must be arranged and bonded to the metal base plate with a predetermined interval (margin) so as not to contact, and the installation area of the semiconductor mounting substrate becomes larger than the sum of the areas of the plurality of semiconductor mounting substrates. For this reason, a semiconductor module composed of a plurality of semiconductor mounting substrates and a single metal base plate is increased in size.

また、一方で、複数の半導体実装基板を1つの絶縁基板にまとめるようにした場合、基板が大型化するので新たに反りが顕在化する等の問題を生じ、はんだ部材の周縁部に発生する応力によるひずみ量も増大したり、また、金属ベース板との接合の際、基板の下のはんだ部材中に空気(気泡)が残り熱伝導性の低下を招いたりと半導体モジュールの信頼性を悪くすることがあった。さらには複数の半導体実装基板を金属ベース板に実装することになると、部品点数が増えるので組み立て効率を低下させることになっていた。   On the other hand, when a plurality of semiconductor mounting substrates are combined into one insulating substrate, the size of the substrate increases, causing a problem such as newly appearing warpage, and stress generated at the peripheral portion of the solder member. Also increases the amount of strain due to heat, and air (bubbles) remains in the solder member under the board when joining to the metal base plate, causing deterioration of the thermal conductivity and reducing the reliability of the semiconductor module. There was a thing. Furthermore, when a plurality of semiconductor mounting boards are mounted on a metal base plate, the number of parts increases, resulting in a reduction in assembly efficiency.

そこで、本発明は、複数の半導体実装基板要素を共通の金属ベース板に接合する必要が生じても大型化することがなく、また、はんだ部材における亀裂の発生および進展を抑制することができる構造の半導体モジュールを提供することを目的とする。   Therefore, the present invention does not increase in size even if it is necessary to join a plurality of semiconductor mounting board elements to a common metal base plate, and can suppress the occurrence and development of cracks in a solder member. An object of the present invention is to provide a semiconductor module.

上記目的を達成するために、本発明に係る半導体モジュールは、
金属パターンが主面及び裏面に設けられた複数の絶縁基板と上記主面の金属パターンに接合された半導体素子とからなる半導体実装基板が、単一の金属ベース板上に接合された半導体モジュールであって、
上記半導体実装基板における上記複数の絶縁基板は、互いに近接して配置され、上記裏面の金属パターンが単一の金属薄板で共通化されてなり、
上記半導体実装基板と上記金属ベース板との接合は、上記金属薄板を介してはんだ部材を用いて行われ、
上記絶縁基板と金属薄板の積層方向から見たとき、上記金属薄板の周縁が対向する上記絶縁基板の周縁より外側に位置することを特徴とする。
In order to achieve the above object, a semiconductor module according to the present invention includes:
A semiconductor module in which a semiconductor mounting substrate comprising a plurality of insulating substrates provided with metal patterns on the main surface and the back surface and semiconductor elements bonded to the metal patterns on the main surface is bonded on a single metal base plate. There,
The plurality of insulating substrates in the semiconductor mounting substrate are arranged close to each other, and the metal pattern on the back surface is shared by a single thin metal plate,
The semiconductor mounting substrate and the metal base plate are joined using a solder member through the metal thin plate,
When viewed from the stacking direction of the insulating substrate and the thin metal plate, the peripheral edge of the thin metal plate is positioned outside the peripheral edge of the opposing insulating substrate.

本発明によれば、複数の半導体実装基板要素(絶縁基板単位)と単一の金属ベース板からなる半導体モジュールにおいて複数の絶縁基板の裏面の金属パターンが単一の金属薄板で共通に構成されつつ、その周縁が絶縁基板の周縁より外側に位置するために、モジュールが大型化することなく、金属薄板と金属ベース板を接合するはんだ部材における亀裂の発生が抑制される。   According to the present invention, in a semiconductor module composed of a plurality of semiconductor mounting substrate elements (insulating substrate units) and a single metal base plate, the metal pattern on the back surface of the plurality of insulating substrates is commonly configured by a single metal thin plate. Since the periphery is located outside the periphery of the insulating substrate, the generation of cracks in the solder member that joins the metal thin plate and the metal base plate is suppressed without increasing the size of the module.

実施の形態1.
本発明の一実施形態に係る、全体が符号10で示される半導体モジュールを図1、2に示す。図2は、図1における一点鎖線で示される半導体モジュール10の断面をA方向から見た図である。
Embodiment 1 FIG.
1 and 2 show a semiconductor module generally designated by reference numeral 10 according to an embodiment of the present invention. FIG. 2 is a view of a cross section of the semiconductor module 10 indicated by a one-dot chain line in FIG.

半導体モジュール10は、駆動時の発熱量が大きい、例えばIGBT(Insulated Gate Bipolar Transistor)などの電力用半導体素子(半導体チップ)12a〜12dとこれらのチップを搭載する基板14aからなる半導体実装ブロック16aと、半導体チップ12e〜12hとこれらのチップを搭載する基板14bからなる半導体実装ブロック16bとから構成された半導体実装基板16を、1つの金属ベース板18に搭載した構造である。また、図示してはいないが、半導体モジュール10は、必要に応じて、金属ベース板18に放熱フィンが当接され、または全体が樹脂パッケージに覆われて構成される。   The semiconductor module 10 has a semiconductor mounting block 16a composed of power semiconductor elements (semiconductor chips) 12a to 12d such as IGBT (Insulated Gate Bipolar Transistor) and a substrate 14a on which these chips are mounted, which generate a large amount of heat during driving. In this structure, the semiconductor mounting substrate 16 composed of the semiconductor chips 12e to 12h and the semiconductor mounting block 16b including the substrate 14b on which these chips are mounted is mounted on one metal base plate 18. Although not shown, the semiconductor module 10 is configured such that the heat dissipation fins are in contact with the metal base plate 18 or the whole is covered with a resin package as required.

半導体実装ブロック16a、16bにおける基板14a、14bは、セラミックで作製された絶縁基板20a、20bの主面(半導体チップと接合される面)に金属薄板で作製された回路パターン(以下、「主面パターン」と称する。)22a、22bが形成されて構成されている。そして、基板14a、14bの絶縁基板20a、20bにおける裏面(金属ベース板18と接合される面)には、金属薄板で作製された回路パターン(以下、「裏面パターン」と称するがこれにはべたパターンも含む)24a、24bが形成されている。なお、これら裏面パターン24a、24bは、半導体実装基板16における構造としては一体、すなわち単一の金属薄板24で形成されており、基板14a、14bのそれぞれに対応する金属薄板24の一部分を便宜的に示すものである。主面パターン22a、22bと金属薄板24は、例えば、アルミや銅などで作製される。主面パターン22a、22bの材料と金属薄板24の材料は、異なっていても良いし、または、同一であっても良い。   The substrates 14a and 14b in the semiconductor mounting blocks 16a and 16b are circuit patterns (hereinafter referred to as “main surfaces”) made of thin metal plates on the main surfaces (surfaces bonded to the semiconductor chips) of the insulating substrates 20a and 20b made of ceramic. This is called a “pattern”.) 22a and 22b are formed. A circuit pattern (hereinafter referred to as a “back pattern”) made of a thin metal plate is used for the back surfaces (surfaces to be joined to the metal base plate 18) of the insulating substrates 20a and 20b of the substrates 14a and 14b. 24a and 24b are also formed. The back surface patterns 24a and 24b are integrated as a structure in the semiconductor mounting substrate 16, that is, are formed of a single metal thin plate 24, and a part of the metal thin plate 24 corresponding to each of the substrates 14a and 14b is provided for convenience. It is shown in The main surface patterns 22a and 22b and the metal thin plate 24 are made of, for example, aluminum or copper. The material of the main surface patterns 22a and 22b and the material of the metal thin plate 24 may be different or the same.

基板14a、14bにおいて、絶縁基板20a、20bに対する主面パターン22a、22bや金属薄板24(裏面パターン24a、24b)の接合は、例えば活性金属法を用いてろう材(図示せず)を介して行われている。   In the substrates 14a and 14b, the main surface patterns 22a and 22b and the metal thin plates 24 (back surface patterns 24a and 24b) are joined to the insulating substrates 20a and 20b through a brazing material (not shown) using, for example, an active metal method. Has been done.

なお、この場合、金属薄板24に接合された絶縁基板20aと20bとの間隔は、裏面パターンが一体でない個々の半導体実装基板を金属ベース板に接合する場合と比べ、精度良く位置決めされるので狭くすることができる。また、半導体実装基板16としては絶縁基板20aと20bとの間がはんだ部材の周縁ではなくなることから、はんだ部材の亀裂対策も基本的には不要となり、金属薄板と絶縁基板との接合形成工程における位置決め精度、および熱膨張の影響を考慮した程度のわずかな距離を採れば十分と言える。これにより、単一の金属ベース板に複数の半導体実装基板要素を設けるようにしても半導体モジュールの大型化を抑制することができる。   In this case, the distance between the insulating substrates 20a and 20b bonded to the metal thin plate 24 is narrower because it is positioned with higher accuracy than the case where individual semiconductor mounting substrates whose back surface patterns are not integrated are bonded to the metal base plate. can do. Further, since the semiconductor mounting substrate 16 is not the periphery of the solder member between the insulating substrates 20a and 20b, it is basically unnecessary to take measures against cracking of the solder member, and in the process of forming the joint between the metal thin plate and the insulating substrate. It can be said that it is sufficient to take a slight distance in consideration of the positioning accuracy and the influence of thermal expansion. Thereby, even if it provides a several semiconductor mounting board | substrate element in a single metal base board, the enlargement of a semiconductor module can be suppressed.

例えば、本実施形態における絶縁基板20aと20bとの間の距離Dについては、金属薄板24の周縁部38の幅Wと同じ、或いはそれ以下(D≦W)とすることも可能である。(図2参照)よって従来は、各半導体実装基板に周縁部を設けなければならないことから、2つの半導体実装基板における絶縁基板間に必要な距離は少なくとも2×Wとなるが、本実施形態においてはその距離を少なくとも1/2以下に縮められることになるのである。   For example, the distance D between the insulating substrates 20a and 20b in the present embodiment can be the same as or smaller than the width W of the peripheral edge 38 of the metal thin plate 24 (D ≦ W). Therefore, conventionally, since each semiconductor mounting substrate has to be provided with a peripheral portion, the required distance between the insulating substrates in the two semiconductor mounting substrates is at least 2 × W. In this embodiment, The distance can be reduced to at least 1/2 or less.

金属ベース板18は、半導体実装基板16における半導体実装ブロック16a、16bが駆動することによって発生する熱を外部に放出するためのものである。金属ベース板18は、金属薄板24の材料と同一の材料、または熱膨張率が略同一の材料が好ましく、例えばアルミや銅で作製される。また、金属ベース板18は、一般に、ねじを用いて半導体モジュール10を他の装置に取り付けるための貫通穴26を有する。   The metal base plate 18 is for releasing heat generated by driving the semiconductor mounting blocks 16a and 16b in the semiconductor mounting substrate 16 to the outside. The metal base plate 18 is preferably made of the same material as that of the metal thin plate 24 or a material having substantially the same thermal expansion coefficient, and is made of, for example, aluminum or copper. Further, the metal base plate 18 generally has a through hole 26 for attaching the semiconductor module 10 to another device using a screw.

図2に示すように、基板14a、14bと半導体チップ12a〜12hの接合は、主面パターン22a、22bに半導体チップ12a〜12hがはんだ部材28を介して接合されることにより行われる。また、基板14a、14bと金属ベース板18の接合、言い換えると半導体実装基板16と金属ベース板18との接合は、金属薄板24に金属ベース板18がはんだ部材30を介して接合されることにより行われる。   As shown in FIG. 2, the substrates 14 a and 14 b and the semiconductor chips 12 a to 12 h are joined by joining the semiconductor chips 12 a to 12 h to the main surface patterns 22 a and 22 b via a solder member 28. Further, the bonding between the substrates 14 a and 14 b and the metal base plate 18, in other words, the bonding between the semiconductor mounting substrate 16 and the metal base plate 18 is performed by bonding the metal base plate 18 to the metal thin plate 24 via the solder member 30. Done.

また、半導体モジュール10は、図2に示すように、はんだ部材30の周縁部32における亀裂の発生および進展を抑えるために、半導体モジュール10の構成要素の積層方向から見た場合、すなわち、図1に示すように、金属薄板24の周縁(輪郭)34全体が絶縁基板20a、20bの周縁(輪郭)36a、36bより外側に位置するように構成されている。言い換えると、金属薄板24の周縁部38(図1において、クロスハッチング部分)が絶縁基板20a、20bに接合されていない。そのため、金属薄板24の周縁部38は、絶縁基板20a、20bに妨害されることなく、金属の熱膨張率で熱膨張や熱収縮することができる(絶縁基板20a、20bに接合されている場合、金属の熱膨張率で膨張または収縮できず、金属より小さく絶縁基板20a、20bに近い熱膨張率で熱膨張するまたは熱収縮する)。したがって、金属薄板24の周縁部38と金属ベース板18とを接合しているはんだ部材30の周縁部32に発生する応力は、金属薄板24と金属ベース板18が略同一の金属の熱膨張率で膨張または収縮し、またその膨張量差または収縮量差が小さい(絶縁基板と金属の膨張量差または収縮量差に比べて小さい)ことから小さくなる。その結果、応力によるひずみ量も小さくなり、はんだ部材30の周縁部32における亀裂の発生および進展が抑制される。   Further, as shown in FIG. 2, the semiconductor module 10 is viewed from the stacking direction of the components of the semiconductor module 10 in order to suppress the occurrence and development of cracks in the peripheral portion 32 of the solder member 30, that is, FIG. 1. As shown in FIG. 3, the entire periphery (contour) 34 of the thin metal plate 24 is configured to be located outside the periphery (contours) 36a and 36b of the insulating substrates 20a and 20b. In other words, the peripheral portion 38 (cross hatched portion in FIG. 1) of the metal thin plate 24 is not joined to the insulating substrates 20a and 20b. Therefore, the peripheral portion 38 of the metal thin plate 24 can be thermally expanded or contracted by the thermal expansion coefficient of the metal without being obstructed by the insulating substrates 20a and 20b (when bonded to the insulating substrates 20a and 20b). The metal cannot be expanded or contracted at the thermal expansion coefficient of the metal, and is thermally expanded or contracted at a thermal expansion coefficient smaller than that of the metal and close to the insulating substrates 20a and 20b). Therefore, the stress generated in the peripheral portion 32 of the solder member 30 that joins the peripheral portion 38 of the metal thin plate 24 and the metal base plate 18 is the coefficient of thermal expansion of the metal that is substantially the same in the metal thin plate 24 and the metal base plate 18. And the difference in expansion amount or contraction amount is small (smaller than the difference in expansion amount or contraction amount between the insulating substrate and the metal). As a result, the amount of strain due to stress is also reduced, and the generation and propagation of cracks at the peripheral edge 32 of the solder member 30 is suppressed.

半導体実装ブロック16a、16bと金属ベース板18との接合時、すなわち、半導体実装基板16における金属薄板24と金属ベース板18とをはんだ部材30を介して接合する際に、金属薄板24と金属ベース板18との間に空気が残らないように、金属薄板24は空気を抜くための貫通孔40を設けるのが好ましい。空気が残ると(言い換えると、はんだ部材30に気泡が存在すると)、はんだ部材30の熱伝導性が低下する。それにより、熱がはんだ部材30を介して金属ベース板18に十分に伝達されなくなり、その結果、半導体モジュール10の寿命が低下することがある。図1に示すように、本実施形態における貫通孔40は、金属薄板24の中央、すなわち、2つの半導体実装ブロック16aと16bとの間に設けられている。なお、貫通孔は、図1に示すようなスリット状に限らず、例えば、複数に分割されるようにしてもよい。   When joining the semiconductor mounting blocks 16a and 16b and the metal base plate 18, that is, when joining the metal thin plate 24 and the metal base plate 18 in the semiconductor mounting substrate 16 via the solder member 30, the metal thin plate 24 and the metal base The metal thin plate 24 is preferably provided with a through hole 40 for extracting air so that no air remains between the plate 18 and the plate 18. When air remains (in other words, when air bubbles exist in the solder member 30), the thermal conductivity of the solder member 30 decreases. Thereby, heat is not sufficiently transmitted to the metal base plate 18 via the solder member 30, and as a result, the life of the semiconductor module 10 may be reduced. As shown in FIG. 1, the through hole 40 in the present embodiment is provided at the center of the thin metal plate 24, that is, between the two semiconductor mounting blocks 16a and 16b. Note that the through hole is not limited to the slit shape as shown in FIG.

半導体モジュール10が駆動すると(半導体チップ12a〜12hが駆動すると)、半導体チップ12a〜12hから発生した熱のほとんどは、はんだ部材28を介して絶縁基板20a、20bの主面パターン22a、22bに伝わる。次に、熱は、主面パターン22a、22bから絶縁基板20a、20bを介して金属薄板24に伝達され、さらに、はんだ部材30を介して金属ベース板18に伝達される。そして金属ベース板18から外部に放熱される。このときに金属ベース板18と金属薄板24が熱膨張する(他の部材も熱膨張する。)。   When the semiconductor module 10 is driven (when the semiconductor chips 12a to 12h are driven), most of the heat generated from the semiconductor chips 12a to 12h is transmitted to the main surface patterns 22a and 22b of the insulating substrates 20a and 20b via the solder member 28. . Next, heat is transmitted from the main surface patterns 22 a and 22 b to the metal thin plate 24 through the insulating substrates 20 a and 20 b, and further to the metal base plate 18 through the solder member 30. Then, heat is radiated from the metal base plate 18 to the outside. At this time, the metal base plate 18 and the metal thin plate 24 are thermally expanded (other members are also thermally expanded).

本実施形態の半導体モジュールによれば、金属ベース板と接合される金属薄板の周縁が対向する各絶縁基板の周縁より外側に配置されるように構成されているため、金属薄板と金属ベース板とを接合しているはんだ部材の周縁部における亀裂の発生および進展が抑制される。また、複数の半導体実装基板要素(絶縁基板単位)が単一の金属ベース板に接合されてなる半導体モジュールは、複数の半導体実装基板要素を半導体実装ブロックとして絶縁基板の裏面パターンが単一の金属薄板で形成され、1つの半導体実装基板として構成されるため、半導体実装基板としての設置面積が小さくなり(裏面パターンが単一の金属薄板で形成されない場合に比べて小さくなり)、その結果、半導体モジュールが大型化が抑制される(半導体モジュール全体に対する半導体実装基板の占有率が高くなる、いわゆる高集積化される。)。さらには、各絶縁基板に対応する複数の半導体実装ブロックを1つの半導体実装基板として扱えるので、組み立て時の部品点数が少なくて済み、組み立て効率を向上させることができる。   According to the semiconductor module of the present embodiment, the metal thin plate and the metal base plate are arranged so that the peripheral edge of the metal thin plate joined to the metal base plate is arranged outside the peripheral edge of each opposing insulating substrate. The generation and propagation of cracks at the peripheral edge of the solder member that joins are suppressed. In addition, a semiconductor module in which a plurality of semiconductor mounting substrate elements (insulating substrate units) are bonded to a single metal base plate has a plurality of semiconductor mounting substrate elements as semiconductor mounting blocks and the back surface pattern of the insulating substrate is a single metal. Since it is formed of a thin plate and configured as a single semiconductor mounting substrate, the installation area as the semiconductor mounting substrate is reduced (compared to the case where the back surface pattern is not formed of a single metal thin plate), and as a result, the semiconductor An increase in the size of the module is suppressed (the so-called high integration in which the occupation ratio of the semiconductor mounting substrate to the entire semiconductor module increases). Furthermore, since a plurality of semiconductor mounting blocks corresponding to each insulating substrate can be handled as one semiconductor mounting substrate, the number of parts at the time of assembly can be reduced, and the assembly efficiency can be improved.

実施の形態2.
本実施の形態が上述の実施形態と異なる点は、半導体実装基板における絶縁基板、および絶縁基板と金属薄板との一部関係が異なる点である。
Embodiment 2. FIG.
The present embodiment is different from the above-described embodiment in that the insulating substrate in the semiconductor mounting substrate and a partial relationship between the insulating substrate and the metal thin plate are different.

具体的に説明するために、本実施形態に係る、全体が符号110で示される半導体モジュールの構成を図3に示す。半導体モジュール110は、上述の実施形態の半導体モジュール10と同様に、金属ベース板118に2つの半導体実装ブロック116a、116bからなる半導体実装基板116が接合された構造である。   For specific description, FIG. 3 shows a configuration of a semiconductor module generally designated by reference numeral 110 according to the present embodiment. Similar to the semiconductor module 10 of the above-described embodiment, the semiconductor module 110 has a structure in which a semiconductor mounting substrate 116 including two semiconductor mounting blocks 116 a and 116 b is bonded to a metal base plate 118.

半導体実装基板116の各半導体実装ブロック116a、116bは、上述の実施形態の2つの半導体実装ブロック16a、16bと同様に、それぞれ複数の半導体チップ112a〜112hとこれらチップを搭載する基板114a、114bから構成される。また、基板114a、114bは、上述の実施形態の基板14a、14bと同様に、絶縁基板120a、120bと、主面パターン122a、122bと、裏面パターン124a、124bから構成される。なお、これら裏面パターン124a、124bは、半導体実装基板116における構造としては一体、すなわち単一の金属薄板124で形成されている。さらに、上述の実施形態と同様に、半導体チップ112a〜112hと基板114a、114bの主面パターン122a、122bの接合と、金属薄膜124と金属ベース板118の接合は、はんだ部材(図示せず)を介して行われている。   Each of the semiconductor mounting blocks 116a and 116b of the semiconductor mounting substrate 116 includes a plurality of semiconductor chips 112a to 112h and substrates 114a and 114b on which these chips are mounted, respectively, similarly to the two semiconductor mounting blocks 16a and 16b of the above-described embodiment. Composed. The substrates 114a and 114b are composed of insulating substrates 120a and 120b, main surface patterns 122a and 122b, and back surface patterns 124a and 124b, similarly to the substrates 14a and 14b of the above-described embodiment. Note that these back surface patterns 124 a and 124 b are integrally formed as a structure in the semiconductor mounting substrate 116, that is, formed of a single metal thin plate 124. Further, as in the above-described embodiment, the bonding between the semiconductor chips 112a to 112h and the main surface patterns 122a and 122b of the substrates 114a and 114b and the bonding between the metal thin film 124 and the metal base plate 118 are performed by solder members (not shown). Is done through.

本実施形態の半導体モジュール110は、絶縁基板120a、120bと金属薄板124の積層方向から見たとき、上述の実施形態の半導体モジュール10のように、金属薄板124の周縁134全体が絶縁基板120a、120bの周縁136a、136bより外側に配置されるように構成されていない。言い換えると、金属薄板124の周縁134の一部が、絶縁基板120a、120bの周縁136a、136bより内側または同じ位置に存在するように構成されている。   When viewed from the stacking direction of the insulating substrates 120a and 120b and the thin metal plate 124, the semiconductor module 110 of the present embodiment has the entire periphery 134 of the thin metal plate 124 as the insulating substrate 120a, as in the semiconductor module 10 of the above-described embodiment. It is not configured to be arranged outside the peripheral edges 136a and 136b of 120b. In other words, a part of the peripheral edge 134 of the thin metal plate 124 is configured to exist inside or at the same position as the peripheral edges 136a and 136b of the insulating substrates 120a and 120b.

この理由について説明する。金属ベース板118や金属薄板124は、半導体チップ112a〜112hから熱が放出されて熱膨張し、または熱の放出が停止されて熱収縮する。特に、半導体チップ112a〜112hに比較的近い金属ベース板118や金属薄板124の部分(領域)が、他の部分に比べて大きく膨張または収縮する。言い換えると、半導体チップ112a〜112hから比較的遠い金属ベース板118や金属薄板124の部分の膨張量や収縮量は比較的小さい。そのため、半導体チップから遠い金属ベース板118や金属薄板124の部分を接合しているはんだ部材の部分は、他の部分と比較して亀裂が発生しにくい。したがって、図3に示すように(絶縁基板120a、120bと金属薄板124の積層方向から見たとき)、上述の実施形態のように金属薄板124の周縁134全体が絶縁基板120a、120bの周縁136a、136bより外側に位置する必要はなく、半導体チップ112a〜112h近傍の絶縁基板120a、120bの周縁136a、136bの部分において、金属薄板124の周縁134が絶縁基板120a、120bの周縁136a、136bより外側に位置すればよい。   The reason for this will be described. The metal base plate 118 and the metal thin plate 124 are thermally expanded by releasing heat from the semiconductor chips 112a to 112h, or are thermally contracted by stopping the release of heat. In particular, portions (regions) of the metal base plate 118 and the metal thin plate 124 that are relatively close to the semiconductor chips 112a to 112h expand or contract significantly compared to other portions. In other words, the amount of expansion or contraction of the metal base plate 118 or the metal thin plate 124 that is relatively far from the semiconductor chips 112a to 112h is relatively small. Therefore, the portion of the solder member that joins the metal base plate 118 and the metal thin plate 124 far from the semiconductor chip is less likely to crack compared to other portions. Therefore, as shown in FIG. 3 (when viewed from the stacking direction of the insulating substrates 120a and 120b and the thin metal plate 124), the entire peripheral edge 134 of the thin metal plate 124 is the peripheral edge 136a of the insulating substrates 120a and 120b as in the above-described embodiment. The peripheral edge 134 of the metal thin plate 124 is less than the peripheral edges 136a and 136b of the insulating substrates 120a and 120b at the peripheral edges 136a and 136b of the insulating substrates 120a and 120b in the vicinity of the semiconductor chips 112a to 112h. What is necessary is just to be located outside.

このことを考慮して、絶縁基板120a、120b上のレイアウトは決定されている。例えば、図3に示す半導体モジュール110のように、発熱体である半導体チップ112a〜112hを絶縁基板120a、120b上の一方側(図中、上側)に、また、発熱体でない例えばワイヤ配線150a、150bが引き出される配線引き出し領域152a、152bを他方側(図中、下側)に配置されるようにレイアウト設計されている。このような絶縁基板120a、120b上のレイアウトを有する半導体モジュール110において、金属薄板124は、絶縁基板120a、120bと金属薄板124の積層方向から見たとき、半導体チップ112a〜112h近傍においては金属薄板124の周縁134が絶縁基板120a、120bの周縁136a、136bより外側に位置し、半導体チップ112a〜112hから遠い配線引き出し領域152a、152b近傍においては金属薄板124の周縁134が絶縁基板120a、120bの周縁136a、136bより内側または同じに位置されるように構成されている。   Considering this, the layout on the insulating substrates 120a and 120b is determined. For example, as in the semiconductor module 110 shown in FIG. 3, the semiconductor chips 112a to 112h, which are heating elements, are disposed on one side (the upper side in the figure) on the insulating substrates 120a, 120b, and the wire wiring 150a, which is not a heating element, for example. The layout is designed so that the wiring lead-out regions 152a and 152b from which the lead 150b is drawn out are arranged on the other side (lower side in the figure). In the semiconductor module 110 having the layout on the insulating substrates 120a and 120b, the metal thin plate 124 is a metal thin plate in the vicinity of the semiconductor chips 112a to 112h when viewed from the stacking direction of the insulating substrates 120a and 120b and the metal thin plate 124. 124 is located outside the peripheral edges 136a and 136b of the insulating substrates 120a and 120b, and the peripheral edge 134 of the thin metal plate 124 is located near the insulating substrates 120a and 120b in the vicinity of the wiring lead-out regions 152a and 152b far from the semiconductor chips 112a to 112h. It is comprised so that it may be located inside or the same as the periphery 136a, 136b.

本実施形態によれば、金属薄板の周縁全体が絶縁基板の周縁より外側に位置するように該金属薄板を構成していない、すなわち、その一部において金属薄板の周縁が絶縁基板の周縁より内側または同じ位置にするようにしているため、上述の実施形態に比べて、金属薄板を形成する材料の量を少なくすることができ、半導体実装基板としての面積も小さくできる。   According to this embodiment, the thin metal plate is not configured so that the entire periphery of the thin metal plate is located outside the peripheral edge of the insulating substrate, that is, the peripheral edge of the thin metal plate is partly inside the peripheral edge of the insulating substrate. Or since it is made to be the same position, compared with the above-mentioned embodiment, the quantity of the material which forms a metal thin plate can be decreased, and the area as a semiconductor mounting substrate can also be made small.

また、上述の実施形態のように、金属薄板と金属ベース板とのはんだ接合時に空気を抜くための貫通穴を設けてもよい。   Moreover, you may provide the through-hole for extracting air at the time of solder joining of a metal thin plate and a metal base plate like the above-mentioned embodiment.

最後に、上述の2つの実施形態の半導体モジュールは、2つの半導体実装ブロックから形成されているが、これに限定されるわけでない。本発明によれば、半導体モジュールを構成する半導体実装ブロックの個数が大きくなるほど、半導体モジュールの大型化抑制の効果が大きくなる、いわゆる高集積化されるのは明らかである。   Finally, the semiconductor modules of the two embodiments described above are formed from two semiconductor mounting blocks, but are not limited thereto. According to the present invention, as the number of semiconductor mounting blocks constituting the semiconductor module increases, the effect of suppressing the increase in the size of the semiconductor module increases.

本発明の実施の形態1に係る半導体モジュールを示す図である。It is a figure which shows the semiconductor module which concerns on Embodiment 1 of this invention. 図1に示すA方向から見た半導体モジュールの断面図である。It is sectional drawing of the semiconductor module seen from the A direction shown in FIG. 本発明の実施の形態2に係る半導体モジュールを示す図である。It is a figure which shows the semiconductor module which concerns on Embodiment 2 of this invention. 従来の半導体モジュールの断面図である。It is sectional drawing of the conventional semiconductor module.

符号の説明Explanation of symbols

10 半導体モジュール、 16a、16b 半導体実装ブロック、 16 半導体実装基板、 18 金属ベース板、 20a、20b 絶縁基板、 24 金属薄板、 24a、24b 裏面金属パターン、 34 金属薄板の周縁(輪郭)、 36a、36b 絶縁基板の周縁
DESCRIPTION OF SYMBOLS 10 Semiconductor module, 16a, 16b Semiconductor mounting block, 16 Semiconductor mounting board, 18 Metal base board, 20a, 20b Insulating board, 24 Metal thin plate, 24a, 24b Back metal pattern, 34 Perimeter (contour) of metal thin plate, 36a, 36b Insulation substrate periphery

Claims (3)

金属パターンが主面及び裏面に設けられた複数の絶縁基板と上記主面の金属パターンに接合された半導体素子とからなる半導体実装基板が、単一の金属ベース板上に接合された半導体モジュールであって、
上記半導体実装基板における上記複数の絶縁基板は、互いに近接して配置され、上記裏面の金属パターンが単一の金属薄板で共通化されてなり、
上記半導体実装基板と上記金属ベース板との接合は、上記金属薄板を介してはんだ部材を用いて行われ、
上記絶縁基板と金属薄板の積層方向から見たとき、上記金属薄板の周縁が対向する上記絶縁基板の周縁より外側に位置することを特徴とする半導体モジュール。
A semiconductor module in which a semiconductor mounting substrate comprising a plurality of insulating substrates provided with metal patterns on the main surface and the back surface and semiconductor elements bonded to the metal patterns on the main surface is bonded on a single metal base plate. There,
The plurality of insulating substrates in the semiconductor mounting substrate are arranged close to each other, and the metal pattern on the back surface is shared by a single thin metal plate,
The semiconductor mounting substrate and the metal base plate are joined using a solder member through the metal thin plate,
A semiconductor module, wherein when viewed from the stacking direction of the insulating substrate and the thin metal plate, the peripheral edge of the thin metal plate is positioned outside the peripheral edge of the opposing insulating substrate.
金属パターンが主面及び裏面に形成された複数の絶縁基板と上記主面の金属パターンに接合された半導体素子とからなる半導体実装基板が、単一の金属ベース板上に接合された半導体モジュールであって、
上記半導体実装基板における上記複数の絶縁基板は、互いに近接して配置され、上記裏面の金属パターンが単一の金属薄板で共通化されてなり、
上記半導体実装基板と上記金属ベース板との接合は、上記金属薄板を介してはんだ部材を用いて行われ、
上記絶縁基板と金属薄板の積層方向から見たとき、上記半導体素子近傍における上記絶縁基板の周縁の部分において、上記金属薄板の周縁が絶縁基板の周縁部分より外側に位置することを特徴とする半導体モジュール。
A semiconductor module in which a semiconductor mounting substrate composed of a plurality of insulating substrates each having a metal pattern formed on the main surface and the back surface and a semiconductor element bonded to the metal pattern on the main surface is bonded on a single metal base plate. There,
The plurality of insulating substrates in the semiconductor mounting substrate are arranged close to each other, and the metal pattern on the back surface is shared by a single thin metal plate,
The semiconductor mounting substrate and the metal base plate are joined using a solder member through the metal thin plate,
When viewed from the stacking direction of the insulating substrate and the metal thin plate, the periphery of the metal thin plate is located outside the peripheral portion of the insulating substrate in the peripheral portion of the insulating substrate in the vicinity of the semiconductor element. module.
複数の絶縁基板の間にあって、絶縁基板と接合されていない金属薄板の部分に貫通孔が形成されていることを特徴とする請求項1または2のいずれかに記載の半導体モジュール。
The semiconductor module according to claim 1, wherein a through hole is formed in a portion of the thin metal plate that is between the plurality of insulating substrates and is not joined to the insulating substrate.
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JPS56116631A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor device
JP2000049425A (en) * 1998-07-27 2000-02-18 Denki Kagaku Kogyo Kk Ceramics circuit board, its manufacture and power module using the same
JP2000101203A (en) * 1998-09-28 2000-04-07 Denki Kagaku Kogyo Kk Ceramics circuit substrate and power module using the same
JP2003133662A (en) * 2001-10-29 2003-05-09 Kyocera Corp Ceramic circuit board
JP2004140199A (en) * 2002-10-18 2004-05-13 Denki Kagaku Kogyo Kk Module structure and its manufacturing method
JP2005109374A (en) * 2003-10-02 2005-04-21 Fuji Electric Device Technology Co Ltd Semiconductor device
JP2005150309A (en) * 2003-11-13 2005-06-09 Toyota Industries Corp Semiconductor device

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Publication number Priority date Publication date Assignee Title
JPS56116631A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor device
JP2000049425A (en) * 1998-07-27 2000-02-18 Denki Kagaku Kogyo Kk Ceramics circuit board, its manufacture and power module using the same
JP2000101203A (en) * 1998-09-28 2000-04-07 Denki Kagaku Kogyo Kk Ceramics circuit substrate and power module using the same
JP2003133662A (en) * 2001-10-29 2003-05-09 Kyocera Corp Ceramic circuit board
JP2004140199A (en) * 2002-10-18 2004-05-13 Denki Kagaku Kogyo Kk Module structure and its manufacturing method
JP2005109374A (en) * 2003-10-02 2005-04-21 Fuji Electric Device Technology Co Ltd Semiconductor device
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