JP6320347B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a plurality of insulating substrates are bonded to an upper surface of a metal base plate.

  A semiconductor device called a power module that controls a large current is used in electric cars, trains, machine tools, and the like. In a power module, a metal circuit board is bonded to one surface of a ceramic substrate as an insulating circuit substrate, and a metal base plate for heat dissipation is bonded to the other surface by soldering or the like. Further, the metal base plate is attached to a metal radiation fin (ie, heat sink), a cooling jacket (ie, water cooling jacket), etc. via heat conduction grease by screwing or the like. A power semiconductor element such as an IGBT, a drive circuit for driving the power semiconductor element, and the like are disposed on the metal circuit board.

  Soldering of the ceramic substrate to the metal base plate is performed by heating. Therefore, the metal base plate is likely to warp due to the difference in thermal expansion coefficient between the joining members during soldering. During operation of the semiconductor device, the heat generated from the semiconductor elements and electronic components mounted on the metal circuit board is transferred to the air or cooling water through the metal circuit board, the ceramic substrate, the solder, and the metal base plate by the radiation fins or the cooling jacket. Is transmitted to. For this reason, if the metal base plate is warped, a gap due to the warp is generated when the heat dissipating fins and the cooling jacket are attached to the metal base plate, and the heat dissipation is extremely lowered. Moreover, since the thermal conductivity of solder itself is low, the heat dissipation to a base board is impaired by interposing solder.

  In order to solve these problems, Patent Document 1 discloses a technique for joining a metal base plate and a ceramic insulating substrate by bringing a molten metal base plate into contact with the ceramic insulating substrate. . Thereby, the curvature of the metal base board which arises by soldering joining is avoided. However, since the thickness of the metal base plate is larger than the thickness of the metal circuit plate provided on the ceramic substrate, there is a possibility that the metal base plate greatly warps due to heat generation during operation of the semiconductor device, thereby causing warping.

  Due to the warpage of the metal base plate, there is a problem that heat dissipation is reduced between the heat dissipation fin and the cooling jacket. Alternatively, the ceramic substrate may be cracked by the warp of the metal base plate, which may impair the insulation.

  Therefore, Patent Document 2 discloses a structure in which a reinforcing material is disposed in a metal base plate in order to suppress warping of the metal base plate. By disposing the reinforcing material inside the metal base plate, thermal expansion on the metal base plate side when a heat load is applied can be suppressed, and the warpage of the substrate can be reduced. Thereby, the heat dissipation when attached to the radiation fins or the cooling jacket can be improved, and cracking due to warping of the ceramic substrate can be suppressed.

JP 2002-76551 A JP 2011-77389 A

  In power semiconductor devices equipped with drive circuit elements such as gate resistors, ceramic substrates with drive circuit elements mounted on the same metal base plate are separated from ceramic substrates with semiconductor elements mounted due to layout requirements. May be placed.

  In this case, the reinforcing material provided in the metal base plate is arranged in balance of thermal stress so that the warp of the metal base plate is reduced in a state where the metal circuit plate and the ceramic substrate are arranged. Therefore, it is necessary to dispose a reinforcing material for each of the plurality of ceramic substrates, which increases the material cost of the reinforcing material. Further, in order to balance the thermal stress, the reinforcing materials need to be positioned and arranged with high accuracy. As a result, the substrate manufacturing method becomes complicated, resulting in an increase in manufacturing cost.

  The present invention has been made in order to solve the above-described problems, and suppresses an increase in the amount and number of reinforcing materials used to reinforce the metal base plate, and suppresses the warp of the metal base plate. An object of the present invention is to provide a semiconductor device.

  A semiconductor device according to the present invention includes a metal base plate and first and second insulating substrates bonded to one main surface of the metal base plate, and the first surface of the first insulating substrate is provided with a first surface. The metal pattern is bonded, the second metal pattern is bonded to the upper surface of the second insulating substrate, the power semiconductor element is disposed on the first metal pattern, and the second metal pattern is positioned on the second metal pattern. A region where the power semiconductor element is not disposed and a reinforcing material is embedded in a region overlapping the first insulating substrate of the metal base plate in plan view and overlaps the second insulating substrate of the metal base plate in plan view The reinforcing material is not embedded, and the thickness of the region overlapping the second insulating substrate of the metal base plate in plan view is smaller than the thickness of the region overlapping the first insulating substrate of the metal base plate in plan view. .

  According to the semiconductor device of the present invention, the reinforcing material is embedded in the metal base plate in a region overlapping the first insulating substrate on which the power semiconductor element is mounted in plan view. Therefore, it is possible to suppress warpage due to thermal expansion of the metal base plate in a region where heat dissipation is required. Thereby, it is possible to suppress the crack of the first insulating substrate.

  Further, a reinforcing material is not embedded in a region overlapping the second insulating substrate on which the power semiconductor element is not mounted in plan view. Further, in this region, the thickness of the metal base plate is smaller than the thickness of the metal base plate in the region overlapping with the first insulating substrate in plan view. Therefore, it is possible to suppress warpage due to thermal expansion of the metal base plate by reducing the thickness of the metal base plate in an area where the requirement for heat dissipation is small. Thereby, it is possible to suppress the crack of the second insulating substrate.

  Therefore, according to the present invention, the amount of reinforcing material used (number of sheets used) is reduced, and the metal base plate is warped even in a region where the reinforcing material is not disposed (that is, a region overlapping the second insulating substrate in plan view). It is possible to suppress. Therefore, cracking of the first and second insulating substrates can be suppressed while suppressing the material cost and manufacturing cost of the reinforcing material. In addition, since the warp of the metal base plate can be reduced, the heat dissipation when the semiconductor device is attached to the heat dissipation fin or the cooling jacket can be improved.

1 is a plan view of a semiconductor device according to a first embodiment. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. 1 is a cross-sectional view of a configuration in which a semiconductor device according to a first embodiment is attached to a radiation fin. It is sectional drawing of the structure which attached the semiconductor device which concerns on Embodiment 1 to another radiation fin. FIG. 10 is a cross-sectional view of a modification of the semiconductor device according to the first embodiment. 4 is a cross-sectional view of a semiconductor device according to a second embodiment. FIG. 6 is a cross-sectional view of a semiconductor device according to a third embodiment. 1 is a cross-sectional view of a configuration in which a semiconductor device according to a first embodiment is attached to a radiation fin.

<Embodiment 1>
FIG. 1 is a plan view of the semiconductor device 10 according to the first embodiment. FIG. 2 is a cross-sectional view taken along line AB in FIG. As shown in FIGS. 1 and 2, the semiconductor device 10 includes a metal base plate 1, first and second insulating substrates 2 and 4, and first and second metal patterns 3 and 5.

  As shown in FIG. 1, one first insulating substrate 2 and four second insulating substrates 4 are bonded to the upper surface of the metal base plate 1. The second insulating substrate 4 is disposed around the first insulating substrate 2. The area of each second insulating substrate 4 is smaller than the area of the first insulating substrate 2.

  The material of the metal base plate 1 is, for example, aluminum or an alloy containing aluminum. The materials of the first and second insulating substrates 2 and 4 are ceramics such as alumina and aluminum nitride. The first and second insulating substrates 2 and 4 and the metal base plate 1 are bonded by, for example, direct bonding or indirect bonding. In direct bonding, bonding is performed by diffusion bonding, room temperature bonding, or the like. In indirect joining, joining is performed by soldering, for example.

  A first metal pattern 3 is bonded to the surface of the first insulating substrate 2 opposite to the metal base plate 1. Similarly, the second metal pattern 5 is bonded to the surface of the second insulating substrate 4 opposite to the metal base plate 1. Here, it is assumed that the thickness of the second metal pattern 5 is smaller than the thickness of the first metal pattern.

  On the first metal pattern 3, a power semiconductor element 6 having a large calorific value is disposed. The power semiconductor element 6 is, for example, an IGBT (Insulated Gate Bipolar Transistor) as a switching element for switching on / off of a large current. The power semiconductor element 6 is, for example, a free-wheeling diode connected in parallel with the switching element.

  On the second metal pattern 5, a circuit component (not shown) having a relatively small calorific value is arranged. Here, the circuit component is, for example, a component that constitutes a control circuit that controls driving of the power semiconductor element 6. Alternatively, the circuit component is a wired circuit board (including a circuit in which a resistance element is mounted) that has a function of relaying wiring. The circuit components arranged on the second metal pattern 5 generate relatively little heat during operation. Therefore, the metal base plate 1 directly under the second metal pattern 5 has a relatively low required heat dissipation.

  As shown in FIG. 2, the region of the metal base plate 1 that overlaps the first insulating substrate 2 in plan view has a thickness T1. Moreover, the area | region (thin part 1a of the metal base board 1) which overlaps with the 2nd insulating board | substrate 4 of the metal base board 1 in planar view has thickness T2. Here, the thickness T2 is smaller than the thickness T1. In order to improve heat dissipation, the thickness T1 is desirably 3 mm or more.

  As shown in FIG. 2, a reinforcing material 7 is embedded in a region of the metal base plate 1 that overlaps the first insulating substrate 2 in plan view. The reinforcing material 7 is, for example, a ceramic plate such as alumina or aluminum nitride, and is disposed at a position overlapping the first insulating substrate 2 having a large area in plan view. The reinforcing material 7 is preferably made of the same material as the first insulating substrate 2 and has substantially the same dimensions (substantially the same thickness and substantially the same area). This is to balance the thermal stress between the reinforcing material 7 and the first insulating substrate 2 when a thermal load is applied.

  The thickness T2 of the thin portion 1a of the metal base plate 1 is desirably substantially the same as the thickness of the second metal pattern 5. This is to balance the stress between the thin portion 1a of the metal base plate 1 and the second metal pattern 5 when a thermal load is applied.

  FIG. 3 is a cross-sectional view of the semiconductor device 10 to which the radiating fins 8 (that is, the heat sink) are attached. The upper surface of the radiation fin 8 is flat. Semiconductor device 10 is fixed to heat radiating fin 8 such that the upper surface of heat radiating fin 8 and the bottom surface of metal base plate 1 are in contact with each other through heat conductive grease. For example, the radiating fins 8 are screwed through the attachment holes 11 (FIG. 1) provided in the metal base plate 1.

  The thin portion 1 a of the metal base plate 1 is recessed with respect to the bottom surface of the metal base plate 1. Therefore, as shown in FIG. 3, the thin portion 1 a of the metal base plate 1 does not come into contact with the heat radiating fins 8.

  FIG. 4 is a cross-sectional view of the semiconductor device 10 to which another radiating fin 8A is attached. On the upper surface of the radiating fin 8A, a convex portion 81 is provided at a position overlapping the thin portion 1a of the metal base plate 1 in plan view. The convex portion 81 has a shape that fits into the recess of the thin portion 1a.

  By providing the projections 81 on the radiating fins 8, the heat transmitted to the second insulating substrate 4 through the second metal pattern 5 can be radiated more efficiently through the projections 81.

<Manufacturing method>
First, the metal base plate 1 is produced. Molten aluminum or aluminum alloy is poured into a previously prepared mold. At this time, the reinforcing material 7 is disposed inside the mold. A metal base plate 1 is obtained by solidifying the metal poured into the mold. As shown in FIG. 2, a reinforcing material 7 is embedded in the metal base plate 1. The metal base plate 1 is provided with a thin portion 1a.

  Next, the first and second insulating substrates 2 and 4 are directly bonded or indirectly bonded to the upper surface of the metal base plate 1 (that is, the surface opposite to the surface on which the thin portion 1a is formed). To join. The first insulating substrate 2 is arranged so as to overlap the reinforcing material 7 in plan view. The second insulating substrate 4 is arranged so as to overlap the thin portion 1a in plan view.

  Next, metal patterns 3 and 5 are respectively formed on the upper surfaces of the first and second insulating substrates 2 and 4. The metal patterns 3 and 5 are formed by bonding a metal plate having a desired pattern shape to the first and second insulating substrates 2 and 4 by, for example, solder bonding.

  Then, the power semiconductor element 6 is joined onto the metal pattern 3 by solder. A circuit component (not shown) is bonded on the metal pattern 5. Further, a wire is appropriately bonded between the power semiconductor element 6 and the circuit component, for example, by wire bonding. Thus, the semiconductor device 10 according to the first embodiment is obtained.

<Effect>
The semiconductor device 10 according to the first embodiment includes a metal base plate 1 and first and second insulating substrates 2 and 4 joined to one main surface of the metal base plate 1 and includes a first insulation. A first metal pattern 3 is bonded to the upper surface of the conductive substrate 2, a second metal pattern 5 is bonded to the upper surface of the second insulating substrate 4, and a power semiconductor is mounted on the first metal pattern 3. The element 6 is disposed, the power semiconductor element 6 is not disposed on the second metal pattern 5, and the reinforcing material 7 is formed in a region overlapping the first insulating substrate 2 of the metal base plate 1 in plan view. The reinforcing material 7 is not embedded in the region that is embedded and overlaps the second insulating substrate 4 of the metal base plate 1 in plan view, and the region that overlaps the second insulating substrate 4 of the metal base plate 1 in plan view. The thickness is smaller than the thickness of the region overlapping the first insulating substrate 2 of the metal base plate 1 in plan view. There.

  According to the semiconductor device 10, the reinforcing material 7 is embedded in the metal base plate 1 in a region overlapping the first insulating substrate 2 on which the power semiconductor element 6 that generates large heat during operation is mounted. . Therefore, it is possible to suppress warpage due to thermal expansion of the metal base plate 1 in a region where heat dissipation is required. Thereby, it is possible to suppress the crack of the first insulating substrate 2 on which the power semiconductor element 6 is mounted.

  Further, the reinforcing material 7 is not embedded in a region overlapping the second insulating substrate 4 on which a circuit component (for example, a drive control circuit) that generates a small amount of heat during operation is mounted. Further, in this region, the thickness of the metal base plate 1 is smaller than the thickness of the metal base plate 1 in the region overlapping the first insulating substrate 2 in plan view. Therefore, it is possible to suppress warpage due to thermal expansion of the metal base plate 1 by reducing the thickness of the metal base plate 1 in a region where the heat dissipation requirement is small. Thereby, it is possible to suppress the cracking of the second insulating substrate 4 on which circuit components with small heat generation are mounted.

  Therefore, in the first embodiment, the usage amount (the number of sheets used) of the reinforcing material 7 is reduced, and also in a region where the reinforcing material 7 is not disposed (that is, a region overlapping the second insulating substrate 4 in plan view). The warp of the metal base plate 1 can be suppressed. Therefore, the cracks of the first and second insulating substrates 2 and 4 can be suppressed while suppressing the material cost and the manufacturing cost of the reinforcing material 7. Moreover, since the curvature of the metal base board 1 can be reduced, the heat dissipation when the semiconductor device 10 is attached to the heat dissipation fin or the cooling jacket can be improved.

  Further, in the semiconductor device 10 according to the first embodiment, the heat dissipating fins 8 (on the other main surface (back surface) of the metal base plate 1 so as to overlap the first and second insulating substrates 2 and 4 in plan view. Alternatively, heat radiation fins 8A) are provided. Therefore, according to this Embodiment 1, since the curvature of the metal base board 1 can be reduced, the heat dissipation when the semiconductor device 10 is attached to the radiation fins 8 and 8A or the cooling jacket can be improved.

  In the semiconductor device 10 according to the first embodiment, the thickness of the second metal pattern 5 is smaller than the thickness of the first metal pattern 3.

  On the first metal pattern 3, a power semiconductor element through which a large current flows is disposed. Therefore, it is preferable that the thickness of the first metal pattern 3 is large. On the other hand, circuit components, wirings, and the like are arranged on the second metal pattern 5. Therefore, since the second metal pattern 5 requires patterning accuracy, the thickness of the second metal pattern 5 is preferably small.

  In the semiconductor device 10 according to the first embodiment, the thickness (thickness T2) of the region overlapping the second insulating substrate 4 of the metal base plate 1 in plan view is bonded to the upper surface of the second insulating substrate 4. The thickness of the formed metal pattern 5 is the same.

  Therefore, the thickness (thickness T2) of the region overlapping the second insulating substrate 4 of the metal base plate 1 in plan view and the thickness of the metal pattern 5 bonded to the upper surface of the second insulating substrate 4 are substantially the same. By doing so, the thermal stress between the metal base plate 1 and the metal pattern 5 can be balanced. Therefore, the warp of the second insulating substrate 4 can be further suppressed.

  In the semiconductor device 10 according to the first embodiment, the reinforcing material 7 is made of the same material as the first insulating substrate 2. Therefore, by making the first insulating substrate 2 and the reinforcing material 7 the same material, the thermal expansion coefficients become equal. Thereby, it becomes easy to balance the thermal stress between the first insulating substrate 2 and the reinforcing material 7. Therefore, the warp of the metal base plate 1 can be suppressed.

  In the semiconductor device 10 according to the first embodiment, the area and thickness of the reinforcing material 7 are the same as the area and thickness of the first insulating substrate 2.

  Therefore, the first insulating substrate 2 and the reinforcing material 7 are made of the same material, and the area and thickness thereof are substantially the same, so that the thermal stress of the first insulating substrate 2 and the reinforcing material 7 is reduced. It becomes easy to balance. Therefore, it is possible to further suppress the warp of the metal base plate 1.

  In the semiconductor device 10 according to the first embodiment, the power semiconductor element 6 is an IGBT. Therefore, even when an IGBT capable of operating at a high temperature is applied as the power semiconductor element 6 to the semiconductor device 10 of the present invention, the warp of the metal base plate 1 can be suppressed.

<Modification of Embodiment 1>
FIG. 5 is a cross-sectional view of a semiconductor device 10A according to a modification of the first embodiment. In this modification, the thickness of the outer peripheral portion 1b of the metal base plate 1 is made the same as the thickness T2 of the thin portion 1a. Thereby, compared with Embodiment 1 (FIG. 2), the volume of the metal base plate 1 can be reduced, and the metal amount required for manufacture of the metal base plate 1 can be reduced.

<Embodiment 2>
FIG. 6 is a cross-sectional view taken along line AB in FIG. 1 when FIG. 1 is a semiconductor device 20 according to the second embodiment. The semiconductor device 20 includes pin fins 9 on the surface opposite to the first insulating substrate 5 in the thin portion 1 a of the metal base plate 1. Other configurations are the same as those of the first embodiment (FIG. 2), and thus description thereof is omitted.

  The material of the pin fin 9 is, for example, aluminum or an alloy containing aluminum. The pin fin 9 is integrally formed with the metal base plate 1 by casting or cutting. A plate-like fin may be provided instead of the pin fin 9.

<Effect>
In the semiconductor device 20 according to the second embodiment, heat radiation fins (that is, pin fins 9) are provided on the other main surface (that is, the back surface) of the region that overlaps the second insulating substrate 4 of the metal base plate 1 in plan view. .

  Therefore, by forming a heat radiating fin on the back surface of the metal base plate 1 immediately below the second insulating substrate 4, warpage due to thermal expansion of the metal base plate 1 in a region overlapping the second insulating substrate 4 in plan view. Can be suppressed. Therefore, in addition to the effects described in the first embodiment, the warpage of the second insulating substrate 4 is further suppressed, so that the cracking of the second insulating substrate 4 is further suppressed.

<Embodiment 3>
FIG. 7 is a cross-sectional view taken along line AB in FIG. 1 when FIG. 1 is a semiconductor device 30 according to the third embodiment.

  In the first embodiment (FIG. 2), the metal base plate 1 has an upper surface (that is, a surface on which the first and second insulating substrates 2 and 4 are joined) having the same height. The thin portion 1a is provided on the back surface (that is, the surface opposite to the top surface) of the base plate 1.

  On the other hand, in the third embodiment (FIG. 7), the thin portion 1a is provided on the upper surface side of the metal base plate 1 so that the height of the back surface of the metal base plate 1 is the same.

  In the third embodiment, as in the first embodiment, the thickness T2 of the thin portion 1a of the metal base plate 1 is smaller than the thickness T1 of the region where the first insulating substrate 2 of the metal base plate 1 is joined. .

  FIG. 8 is a cross-sectional view of the semiconductor device 30 to which the radiation fins 8 are attached. In the semiconductor device 30 according to the third embodiment, since the height of the back surface of the metal base plate 1 is uniform, the entire back surface of the metal base plate 1 can be brought into contact with the radiating fins 8. The same applies when a cooling jacket is used in place of the radiating fins 8.

<Effect>
In the semiconductor device 30 according to the third embodiment, on the other main surface (that is, the back surface) of the metal base plate 1, a region overlapping the first insulating substrate 2 in plan view, and the second insulating substrate 4 and plan view. The height of the overlapping area is the same.

  Therefore, since the height of the back surface of the metal base plate 1 becomes uniform, the entire back surface of the metal base plate 1 can be brought into contact with the radiation fins 8. Thereby, the heat dissipation of the semiconductor device 30 is improved. Therefore, in addition to the effects described in the first embodiment, the warp of the metal base plate 1 can be further suppressed.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  DESCRIPTION OF SYMBOLS 1 Metal base board, 1a Thin part, 1b Outer peripheral part, 1st insulating board, 3 1st metal pattern, 4 2nd insulating board, 5 2nd metal pattern, 6 Power semiconductor element, 7 Reinforcement material, 8, 8A Radiation fin, 9 pin fin, 10, 10A, 20, 30 Semiconductor device, 11 Mounting hole.

Claims (9)

A metal base plate;
First and second insulating substrates joined to one main surface of the metal base plate;
With
A first metal pattern is bonded to the upper surface of the first insulating substrate,
A second metal pattern is bonded to the upper surface of the second insulating substrate,
A power semiconductor element is disposed on the first metal pattern,
No power semiconductor element is disposed on the second metal pattern,
In the region of the metal base plate that overlaps the first insulating substrate in plan view, a reinforcing material is embedded,
In a region overlapping the second insulating substrate of the metal base plate in plan view, no reinforcing material is embedded,
The thickness of the region overlapping the second insulating substrate of the metal base plate in plan view is smaller than the thickness of the region overlapping the first insulating substrate of the metal base plate in plan view.
Semiconductor device. Radiation fins are provided on the other main surface of the region overlapping the second insulating substrate of the metal base plate in plan view.
The semiconductor device according to claim 1. On the other main surface of the metal base plate, the height of the region overlapping the first insulating substrate in plan view and the region overlapping the second insulating substrate in plan view are equal.
The semiconductor device according to claim 1. Radiation fins are provided on the other main surface of the metal base plate so as to overlap the first and second insulating substrates in plan view.
The semiconductor device as described in any one of Claims 1-3. The thickness of the second metal pattern is smaller than the thickness of the first metal pattern,
The semiconductor device according to claim 1. The thickness of the region of the metal base plate that overlaps the second insulating substrate in plan view is the same as the thickness of the metal pattern bonded to the upper surface of the second insulating substrate.
The semiconductor device according to any one of claims 1 to 5. The reinforcing material is the same material as the first insulating substrate.
The semiconductor device as described in any one of Claims 1-6. The area and thickness of the reinforcing material are the same as the area and thickness of the first insulating substrate.
The semiconductor device according to claim 7. The power semiconductor element is an IGBT.
The semiconductor device according to claim 1.

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