JP4513305B2 - メモリ装置 - Google Patents
メモリ装置 Download PDFInfo
- Publication number
- JP4513305B2 JP4513305B2 JP2003354006A JP2003354006A JP4513305B2 JP 4513305 B2 JP4513305 B2 JP 4513305B2 JP 2003354006 A JP2003354006 A JP 2003354006A JP 2003354006 A JP2003354006 A JP 2003354006A JP 4513305 B2 JP4513305 B2 JP 4513305B2
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- JP
- Japan
- Prior art keywords
- data
- bit
- memory cell
- memory cells
- charge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/20—Analysis of motion
- G06T7/223—Analysis of motion using block-matching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2200/00—Indexing scheme for image data processing or generation, in general
- G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/10—Image acquisition modality
- G06T2207/10016—Video; Image sequence
Description
図1は、実施の形態としてのメモリブロック100の構成を示している。このメモリブロック100は、メモリセルアレイ110と、記憶データ入出力用ポート120と、ロウアドレスデコーダ130と、演算データ出力用ポート140と、制御回路150とを有している。
このメモリブロック100は、演算データ出力用ポート140を除く部分のみで、図8に示す従来のメモリブロック200と同様の動作によって、メモリセルアレイ110の所定のメモリセルMLに対する、記憶データの書き込み、読み出しが可能である。
Qb=Qc×Cb/(Cm+Cb) ・・・(1)
Claims (3)
- それぞれがワード線に接続される8個のメモリセルを含み1つのデータを構成する8ビットを記憶するユニットであって、それぞれの前記ユニットを構成する8個のメモリセルのキャパシタの容量が、最下位のビットを表す電荷を蓄積するものから順に2倍ずつ多くなる前記ユニットがビット線毎に複数接続されるメモリセルアレイと、
2つ以上の前記データに係るワード線を同時に活性化する活性化手段と、
上記活性化手段で活性化された複数のワード線に接続された複数のメモリセルのキャパシタの蓄積電荷が結合されて1つのビット線上に得られた電荷総量に対応した値のデジタル信号を出力する信号出力手段と
を備えるメモリ装置。 - 上記信号出力手段は、
上記電荷総量を、該電荷総量に対応した値の電圧信号に変換する電圧変換手段と、
上記電圧変換手段で変換された電圧信号をアナログ信号からデジタル信号に変換するアナログ−デジタル変換手段とを有してなる
請求項1に記載のメモリ装置。 - 前記ユニットには、それぞれ加算すべき前記データが記憶される
請求項1に記載のメモリ装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003354006A JP4513305B2 (ja) | 2002-10-15 | 2003-10-14 | メモリ装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002300902 | 2002-10-15 | ||
JP2003354006A JP4513305B2 (ja) | 2002-10-15 | 2003-10-14 | メモリ装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004158170A JP2004158170A (ja) | 2004-06-03 |
JP4513305B2 true JP4513305B2 (ja) | 2010-07-28 |
Family
ID=32827905
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003354006A Expired - Fee Related JP4513305B2 (ja) | 2002-10-15 | 2003-10-14 | メモリ装置 |
Country Status (1)
Country | Link |
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JP (1) | JP4513305B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101952456B1 (ko) | 2010-10-29 | 2019-02-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 기억 장치 |
US9430191B2 (en) | 2013-11-08 | 2016-08-30 | Micron Technology, Inc. | Division operations for memory |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000035878A (ja) * | 1998-07-17 | 2000-02-02 | Texas Instr Japan Ltd | 加算演算装置及び加算演算機能付き半導体メモリ装置 |
-
2003
- 2003-10-14 JP JP2003354006A patent/JP4513305B2/ja not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000035878A (ja) * | 1998-07-17 | 2000-02-02 | Texas Instr Japan Ltd | 加算演算装置及び加算演算機能付き半導体メモリ装置 |
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Publication number | Publication date |
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JP2004158170A (ja) | 2004-06-03 |
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