JP4501977B2 - 半導体装置とワイヤボンディング方法 - Google Patents
半導体装置とワイヤボンディング方法 Download PDFInfo
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- JP4501977B2 JP4501977B2 JP2007238001A JP2007238001A JP4501977B2 JP 4501977 B2 JP4501977 B2 JP 4501977B2 JP 2007238001 A JP2007238001 A JP 2007238001A JP 2007238001 A JP2007238001 A JP 2007238001A JP 4501977 B2 JP4501977 B2 JP 4501977B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 184
- 238000000034 method Methods 0.000 title claims description 28
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005520 cutting process Methods 0.000 claims description 11
- 230000015556 catabolic process Effects 0.000 description 11
- 239000012535 impurity Substances 0.000 description 9
- 210000000746 body region Anatomy 0.000 description 7
- 230000005684 electric field Effects 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000001154 acute effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
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Description
半導体装置の表面にパッドを設け、そのパッドにワイヤをボンディングする装置が特許文献1,2に開示されている。
(1)半導体基板の表面の外周に沿って外周の内側を一巡するFLRによって耐圧能力を向上させている半導体装置の場合、半導体構造と小信号パッドをFLRの内側の領域に収容しなければならない。当然ながら、半導体基板の面積の全部を有効に利用することができない。
(2)小信号パッドの下方には必要な半導体構造を実現することができない。すなわち、パッドの存在によって、有効に活用できる面積がさらに減少している。
従来の半導体装置では、FLRと小信号パッドによって、半導体装置が機能するのに必要な半導体構造を製造できる有効面積が狭くされている。
本発明では、半導体装置が機能するのに必要な半導体構造を製造できる有効面積を拡大する技術を提供する。
本発明では、上記認識に基づいて、半導体装置が機能するのに必要な半導体構造を製造できる有効面積を拡大することに成功した。
本発明の半導体装置では、第1パッドで切断作業をする必要がないので、第1パッドで引き摺り痕が形成されることがない。引き摺り痕の形成範囲を含む程度にまで第1パッドを拡大して形成する必要がない。これにより、ボンディングできればよい面積まで第1パッドを縮小することができ、半導体装置が機能するのに必要な半導体構造を製造できる有効面積を拡大することができる。本半導体装置では、第2パッドを必要とする。しかしながら、その第2パッドはFLRの外側に配置され、しかも耐圧を確保するためにはFLRの外側に一定の広がりをもった面積がもともと必要とされることから、第2パッドが有効面積を減少させることもない。
半導体装置が垂直方向から観測して多角形である場合、半導体装置の頂点部では電場の集中を防ぐ為にFLRが湾曲して形成される。例えば、半導体装置の頂点が鋭角や鈍角など180度未満の角度を持って形成される場合、FLRは大きな曲率半径を持ち、外側に凸な湾曲形状に形成される。本発明では、FLRのうち、半導体装置の頂点部近傍において湾曲している部分を湾曲部と呼ぶ。半導体装置の頂点部の周辺部では、半導体装置の頂点部以外の周辺部に比べて、FLRの外側の領域が広く形成され、第2パッドを形成する十分な領域を確保しやすい。これにより、半導体装置全体の大面積化を避けながら、半導体装置の有効面積を拡大することができる。
このワイヤボンディング方法では、第1パッドでワイヤを切断しない。その為、第1パッドを単にボンディングできればよい面積まで小さくすることができ、半導体装置の有効面積を拡大することができる。
(特徴1)FLRよりも外側の領域には厚い酸化膜が形成されている。
(特徴2)FLRよりも外側の領域には、EQRのフィールドプレートと第2パッドが同一工程で形成される。
(特徴3)第2パッドとEQRの間には溝が形成されており、第2パッドとEQRは絶縁されている。
(特徴4)半導体構造を製造できる有効面積を同一面積に保つ場合、第1パッドの面積を縮小することによって、半導体装置全体の面積を縮小することができる。半導体装置の製造コストを下げることができる。
(特徴5)同一面積の半導体基板を用いる場合、第1パッドの面積を縮小することによって、半導体構造を製造できる有効面積を拡大することができる。
図1に、本発明を具現化した半導体装置2を示す。半導体装置2では、終端耐圧領域18が半導体基板3の外周の内側を一巡している。終端耐圧領域18には、FLR65が二重に形成されている。FLR65の内部には活性領域4が形成されており、FLR65の外部には不活性領域6が形成されている。活性領域4には半導体構造を構成している半導体領域8とパッド領域10が形成されている。パッド領域10には、半導体領域8に導通している4つの第1パッド24a、24b、24c、24dが形成されている。以下の説明でアルファベット記号が省略されている場合は、同じ参照数字の部材に共通する説明であることを示す。パッド領域10内の半導体基板3内には半導体構造が形成されていない。パッド領域10が小さいほど、広い半導体領域8を確保することができる。不活性領域6には、半導体領域8から絶縁されている4つの第2パッド26a、26b、26c、26dと導電性のフィールドプレート70が形成されている。図示番号22a、22b、22c、22dはワイヤを示し、半導体装置2の半導体領域8の表面に露出している4つのエミッタ電極パッド16a、16b、16c、16dとボンディングされており、外部回路(図示されていない)とエミッタ電極パッド16を電気的に接続している。図示番号14a、14b、14c、14dはワイヤを示し、半導体装置2のパッド領域10の表面に形成された第1パッド24a、24b、24c、24dとボンディングされており、外部回路(図示されていない)と第1パッド24を電気的に接続している。ワイヤ14a、14b、14c、14dの終端部は不活性領域6に形成された第2パッド26a、26b、26c、26dにボンディングされている。
半導体装置2の活性領域4の半導体領域8には、絶縁ゲート型バイポーラトランジスタ(Insulated Gate Bipolar Transistorであり、以下ではIGBTという)が形成されている。半導体装置2は、1枚のn型不純物を低濃度に含む半導体基板3に形成されており、半導体基板3が未加工状態で残っている部分によって、ドリフト領域46が形成されている。ドリフト領域46の表面側に、p型不純物を低濃度に含むボディ領域48が形成されている。ボディ領域48の表面に臨む位置に、n型不純物を高濃度に含んでいるエミッタ領域54が形成されている。エミッタ領域54は、ボディ領域48によって、ドリフト領域46から隔てられている。
エミッタ領域54の表面から、エミッタ領域54とボディ領域48を貫通し、ドリフト領域46に達するトレンチ56が形成されている。トレンチ56の底面と壁面はゲート絶縁膜60で被覆されており、トレンチ56の内側にトレンチゲート電極58が充填されている。トレンチゲート電極58の上面は、ゲート絶縁膜60で被覆されている。半導体領域8内のエミッタ領域54及びトレンチ56が形成されている範囲の半導体装置2の表面には酸化膜52が形成されている。酸化膜52の表面を含む半導体領域8内の半導体装置2の表面には、エミッタ電極パッド16が形成されている。エミッタ電極パッド16は、エミッタ領域54に導通している。また、エミッタ電極パッド16は、酸化膜52に形成されたコンタクト59を通してボディ領域48と導通している。
また、半導体装置2のパッド領域10の表面にはゲート電極用の第1パッド24が形成されている。トレンチゲート電極58は図示しない断面で、半導体装置2の表面に露出し、ゲート電極用の第1パッド24に接続されている。半導体装置2のパッド領域10のゲート電極用の第1パッド24が形成された領域には、ドリフト領域46の表面に臨む位置にp型不純物を高濃度に含むP型拡散領域50が形成されている。P型拡散領域50はp型不純物を含むボディ領域48の終端部と接続し、電気的に導通している。
半導体装置2の裏面側には、p型不純物を高濃度に含むコレクタ領域44が形成されている。半導体装置2の裏面にはコレクタ電極42が形成されている。コレクタ電極42は、コレクタ領域44と導通している。
半導体装置2の不活性領域6には、ドリフト領域46の表面に臨む位置にn型不純物を高濃度に含むチャネルストッパ領域72が形成されている。チャネルストッパ領域72は、活性領域4で発生した電界が、半導体基板3の終端領域まで広がることを防止する機能を持つ。不活性領域6の酸化膜52の表面にはフィールドプレート70と第2パッド26が形成されている。フィールドプレート70と第2パッド26の間には溝74が形成されており、これにより第2パッド26はフィールドプレート70から絶縁されている。チャネルストッパ領域72とフィールドプレート70は、不活性領域6の酸化膜52に形成されたコンタクトホール68を通して導通している。このチャネルストッパ領域72とフィールドプレート70によってEQR(Equal Potential Ring)が形成されている。
これに対し、従来技術の半導体装置302では、図7に示すように、第1パッド324を用いて半導体装置302を外部回路とワイヤボンディングする。すなわち、一端が外部回路にボンディングされているワイヤ314a、314b、314c、314dを、対応する第1パッド324a、324b、324c、324dにボンディングし、第1パッド324を端として、第1パッド324でワイヤ314を切断する。本発明の半導体装置2では第1パッド24でワイヤ14を切断しないために、第1パッド24の面積を縮小することができる。その理由を図9〜図13のワイヤボンディング方法の手順を用いて説明する。
このワイヤボンディング方法では、まず図10に示すように、ウェッジ・ツール134の底面134aを外部回路146のリード148に押し付け、リード148とワイヤ140をボンディングする。リード148表面にボンディング痕150が形成される。
次に図11に示すように、ワイヤ140及びクランプ138及びウェッジ・ツール134を次のボンディング先である半導体装置144のパッド142に移動する。次に図12に示すように、ウェッジ・ツール134の底面134aを半導体素子146のパッド142に押し付け、パッド142とワイヤ140をボンディングする。パッド142表面にボンディング痕152が形成される。
図14に示すように、パッド142がボンディング痕152と同程度の面積である場合、引き摺り痕162はパッド142を超えて形成され、半導体装置144の表面の保護膜に損傷164が形成される。保護膜に損傷164が形成された場合、損傷164を通して半導体装置144内部に不純物などが進入し、半導体装置144の特性低下及び破損の原因となる。その為、パッド142上でワイヤ140を切断する場合には、図8に示すように、パッド324を、引き摺り痕28の形成範囲を含む程度に拡大して形成していた。
本発明の半導体装置2では、厚い酸化膜52によって第2パッド26が半導体領域8から絶縁されて形成されている。その為、ワイヤ14を介して第1パッド24に入力される電気信号が第2パッド26に入力されても、半導体領域8に影響を及ぼすことがない。第2パッド26に高電圧信号が入力された場合でも、酸化膜52が厚いためにチャネルストッパ領域72に反転相が形成されることがない。第2パッド26が不活性領域6に影響を及ぼすこともない。
本発明の第2実施例の半導体装置102を図4に示す。図4に示すように、半導体装置102の表面を垂直方向から観測すると多角形(図4では四角形)である場合、4つの第2パッド126a、126b、126c、126dが多角形の頂点の内側を湾曲して伸びているFLR65の外側の領域に配置されている。図4に示すように、半導体装置102の頂点部では、FLR65は活性領域4の終端領域で電場が集中することを防ぐ為に、湾曲して形成される。図5に第2パッド126aが形成されている半導体装置102の頂点を拡大して示す。半導体装置102の頂点が180度未満の角度を持って形成される場合、FLR65は大きな曲率半径を持ち、半導体装置102の外側に向かって凸となるように湾曲して形成される。その為、半導体装置102の頂点部では、半導体装置102の頂点部以外の周辺部に比べて不活性領域6が広く形成される。これにより、半導体装置102の頂点部では、第2パッド126を形成する十分な領域を確保することができ、第2パッド126を形成する為に半導体装置102の全体面積を拡大する必要がない。半導体装置102の全体面積を保ったまま、活性領域4の4つのパッド領域110a、110b、110c、110dの合計面積を縮小させることができる。
しかし、第2パッド126を半導体装置102の頂点部の不活性領域6に配置することと、第1パッド124を半導体装置102の頂点部のFLR65に隣接する活性領域4に配置することは必ずしも同時に行われる必要はない。図6に第2パッド226a、226b、226c、226dを半導体装置202の頂点部の不活性領域6に配置することのみを実行した本発明の第3実施例の半導体装置202を示す。この実施例でも、第2パッド226を半導体装置202の頂点部の不活性領域6に配置することによって、半導体装置202全体の面積を保ったまま、活性領域4のパッド領域210の面積を縮小させることができる。
例えば半導体装置に形成される第1パッドと第2パッドの数は、半導体装置に4つ配置されている例を示したが、その数は限定されない。例えば第1パッドと第2パッドが2つずつ配置されていても構わない。
本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時の請求項に記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。
3・・・・・半導体基板
4・・・・・活性領域
6・・・・・不活性領域
8・・・・・半導体領域
10・・・・パッド領域
14・・・・ワイヤ
14a、14b、14c、14d・・・ワイヤ
16・・・・エミッタ電極パッド
16a、16b、16c、16d・・・エミッタ電極パッド
18・・・・終端耐圧領域
22・・・・ワイヤ
22a、22b、22c、22d・・・ワイヤ
24・・・・第1ボンディングパッド
24a、24b、24c、24d・・・第1ボンディングパッド
26・・・・第2ボンディングパッド
26a、26b、26c、26d・・・第2ボンディングパッド
28・・・・引き摺り痕
30・・・・ボンディング痕
42・・・・コレクタ電極
44・・・・コレクタ領域
46・・・・ドリフト領域
48・・・・ボディ領域
50・・・・P型拡散領域
52・・・・酸化膜
54・・・・エミッタ領域
56・・・・トレンチ
58・・・・トレンチゲート電極
59・・・・コンタクトホール
60・・・・ゲート絶縁膜
62・・・・コンタクトホール
62a、62b・・・コンタクトホール
64・・・・フィールドプレート
64a、64b・・・フィールドプレート
65・・・・FLR
65a、65b・・・FLR
66・・・・ガードリング
66a、66b・・・ガードリング
68・・・・コンタクトホール
70・・・・フィールドプレート
72・・・・チャネルストッパ領域
74・・・・溝
102・・・半導体装置
108・・・半導体領域
110・・・パッド領域
110a、110b、110a、110b・・・半導体領域
114・・・ワイヤ
114a、114b、114c、114d・・・ワイヤ
116・・・エミッタ電極パッド
116a、116b、116c、116d・・・エミッタ電極パッド
124・・・第1ボンディングパッド
124a、124b、124c、124d・・・第1ボンディングパッド
126・・・第2ボンディングパッド
126a、126b、126c、126d・・・第2ボンディングパッド
134・・・ウェッジ・ツール
134a・・・ウェッジ・ツールの底面
136・・・支え
138・・・クランプ
140・・・ワイヤ
142・・・ボンディングパッド
144・・・半導体装置
146・・・外部回路
148・・・リード
150・・・ボンディング痕
152・・・ボンディング痕
154・・・矢印
156・・・矢印
162・・・引き摺り痕
164・・・損傷
202・・・半導体装置
208・・・半導体領域
210・・・パッド領域
214・・・ワイヤ
214a、214b、214c、214d・・・ワイヤ
216・・・エミッタ電極パッド
216a、216b、216c、216d・・・エミッタ電極パッド
224・・・第1ボンディングパッド
224a、224b、224c、224d・・・第1ボンディングパッド
226・・・第2ボンディングパッド
226a、226b、226c、226d・・・第2ボンディングパッド
302・・・半導体装置
308・・・半導体領域
310・・・パッド領域
314・・・ワイヤ
314a、314b、314c、314d・・・ワイヤ
316・・・・エミッタ電極パッド
316a、316b、316c、316d・・・エミッタ電極パッド
324・・・第1ボンディングパッド
324a、324b、324c、324d・・・第1ボンディングパッド
Claims (5)
- 半導体基板の表面の外周の内側を一巡しているFLRと、
FLRよりも内側の領域に配置されており、制御される電力に応じた電流が流れる第1のワイヤがボンディングされる電力用パッドと、
FLRよりも内側の領域に配置されており、半導体基板内に形成されている半導体領域に導通しており、小信号を伝える第2のワイヤがボンディングされている第1ボンディングパッドと、
FLRよりも外側の領域に配置されており、半導体基板内に形成されている半導体領域から絶縁されており、小信号を伝える第2のワイヤがボンディングされている第2ボディングパッド、
を備えており、
第2のワイヤは、その一端が外部回路にボンディングされており、その中間で第1ボンディングパッドにボンディングされており、その他端が第2ボンディングパッドにボンディングされると共に第2ボンディングパッドで切断されていることを特徴とする半導体装置。 - 第1ボンディングパッドの表面を垂直方向から観測すると矩形状であり、
第1ボンディングパッドの各辺の長さは、第2ボンディングパッドの第2のワイヤを切断する方向の長さよりも短いことを特徴とする請求項1に記載の半導体装置。 - 半導体装置の表面を垂直方向から観測すると多角形であり、
第2ボンディングパッドが、多角形のいずれかの頂点と該頂点の内側を湾曲して伸びるFLRの湾曲部との間の領域に配置されていることを特徴とする請求項1又は2に記載の半導体装置。 - 第1ボンディングパッドが、FLRの内側の位置であり、第2ボンディングパッドが配置されている多角形の頂点の内側を湾曲して伸びるFLRの湾曲部に隣接する位置に配置されていることを特徴とする請求項3に記載の半導体装置。
- 請求項1の半導体装置にワイヤをボンディングする方法であり、
一端が外部回路にボンディングされているワイヤを、そのワイヤを切断しないで、第1ボンディングパッドにボンディングする工程と、
第1ボンディングパッドで切断されなかったワイヤを第2ボンディングパッドにボンディングするとともに、そのワイヤを第2ボンディングパッド上で切断する工程、
を備えていることを特徴とするワイヤボンディング方法。
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CN2008801062883A CN101803013B (zh) | 2007-09-13 | 2008-09-12 | 半导体装置以及导线焊接方法 |
US12/677,123 US8432015B2 (en) | 2007-09-13 | 2008-09-12 | Semiconductor device and wire bonding method |
PCT/IB2008/002379 WO2009034461A2 (en) | 2007-09-13 | 2008-09-12 | Semiconductor device and wire bonding method |
EP20080807066 EP2195838B1 (en) | 2007-09-13 | 2008-09-12 | Semiconductor device and wire bonding method |
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JP2004140072A (ja) * | 2002-10-16 | 2004-05-13 | Fuji Electric Device Technology Co Ltd | パワー半導体装置のワイヤボンディング方法 |
JP2005123388A (ja) * | 2003-10-16 | 2005-05-12 | Sony Corp | ボンディング構造及びボンディング方法、並びに半導体装置及びその製造方法 |
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JP2004140072A (ja) * | 2002-10-16 | 2004-05-13 | Fuji Electric Device Technology Co Ltd | パワー半導体装置のワイヤボンディング方法 |
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