JP4500373B2 - 一体化システムメモリおよび改良されたバス同時実行性を有するコンピュータシステム - Google Patents

一体化システムメモリおよび改良されたバス同時実行性を有するコンピュータシステム Download PDF

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Publication number
JP4500373B2
JP4500373B2 JP54396198A JP54396198A JP4500373B2 JP 4500373 B2 JP4500373 B2 JP 4500373B2 JP 54396198 A JP54396198 A JP 54396198A JP 54396198 A JP54396198 A JP 54396198A JP 4500373 B2 JP4500373 B2 JP 4500373B2
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Japan
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data
memory
cpu
bus
controller
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Expired - Fee Related
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JP54396198A
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Japanese (ja)
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JP2001526808A (ja
JP2001526808A5 (enExample
Inventor
メルガード，ジェイムズ・オゥ
クインビィ，マイケル・エス
ウェイクランド，カール・ケイ
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/125—Frame memory handling using unified memory architecture [UMA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/128—Frame memory using a Synchronous Dynamic RAM [SDRAM]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Graphics (AREA)
  • Bus Control (AREA)
JP54396198A 1997-04-14 1998-04-07 一体化システムメモリおよび改良されたバス同時実行性を有するコンピュータシステム Expired - Fee Related JP4500373B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/837,120 US5941968A (en) 1997-04-14 1997-04-14 Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU and expansion bus device
US08/837,120 1997-04-14
PCT/US1998/006475 WO1998047075A1 (en) 1997-04-14 1998-04-07 Computer system with unified system memory and improved bus concurrency

Publications (3)

Publication Number Publication Date
JP2001526808A JP2001526808A (ja) 2001-12-18
JP2001526808A5 JP2001526808A5 (enExample) 2005-11-10
JP4500373B2 true JP4500373B2 (ja) 2010-07-14

Family

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JP54396198A Expired - Fee Related JP4500373B2 (ja) 1997-04-14 1998-04-07 一体化システムメモリおよび改良されたバス同時実行性を有するコンピュータシステム

Country Status (3)

Country Link
US (1) US5941968A (enExample)
JP (1) JP4500373B2 (enExample)
WO (1) WO1998047075A1 (enExample)

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JP2001526808A (ja) 2001-12-18
US5941968A (en) 1999-08-24
WO1998047075A1 (en) 1998-10-22

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