JP4493981B2 - 半導体デバイスの実装部材、半導体デバイスの実装構造、および半導体デバイスの駆動装置 - Google Patents
半導体デバイスの実装部材、半導体デバイスの実装構造、および半導体デバイスの駆動装置 Download PDFInfo
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- JP4493981B2 JP4493981B2 JP2003373136A JP2003373136A JP4493981B2 JP 4493981 B2 JP4493981 B2 JP 4493981B2 JP 2003373136 A JP2003373136 A JP 2003373136A JP 2003373136 A JP2003373136 A JP 2003373136A JP 4493981 B2 JP4493981 B2 JP 4493981B2
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- Prior art keywords
- conductor plate
- semiconductor device
- wiring board
- power supply
- conductor
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- 239000004065 semiconductor Substances 0.000 title claims description 103
- 239000004020 conductor Substances 0.000 claims description 204
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 4
- 230000002457 bidirectional effect Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 35
- 239000010410 layer Substances 0.000 description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000003014 reinforcing effect Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
2 電源供給用導体板
3 GND用導体板(接地用導体板)
4 絶縁フィルム(絶縁体)
10 半導体デバイス
21・31 ピン状導体
81 電源接続部(電源供給手段)
82 GND接続部(電源供給手段)
Claims (4)
- 半導体デバイスに対して動作信号の入出力を行う配線基板と、
前記半導体デバイスに動作電源を供給するための電源供給用導体板および接地用導体板とを、絶縁体を介して積層した構造を有し、
前記配線基板、電源供給用導体板および接地用導体板は、前記配線基板が最も実装面側に配置されており、
前記配線基板における動作信号の入出力用の電極パッドと、電源供給用導体板および接地用導体板における接続電極とを、同一の実装面内に半導体デバイスの電極レイアウトと一致するように配してなり、
前記電源供給用導体板および前記接地用導体板は、前記配線基板を貫通するピン状導体を圧入され、該ピン状導体の端面が配線基板表面に位置することによって接続電極が形成されており、
前記電源供給用導体板および前記接地用導体板のうち、実装面に近い側に配置された導体板には前記実装面から遠い側に配置された導体板に圧入されたピン状導体に対応する位置に前記ピン状導体よりも大きな径を有する貫通孔が形成され、実装面から遠い側に配置された導体板に圧入されたピン状導体は、前記貫通孔を通ることによって前記貫通孔を有する導体板と非接触となっており、
前記配線基板において前記ピン状導体を貫通させる孔の周囲には、配線層の他の電極となる導体が露出しないように前記配線基板の配線層がパターニングされていることを特徴とする半導体デバイスの実装部材。 - 半導体デバイスに対して動作信号の入出力を行う配線基板と、
前記半導体デバイスに動作電源を供給するための電源供給用導体板および接地用導体板とを、絶縁体を介して積層した構造を有し、
前記配線基板、電源供給用導体板および接地用導体板は、前記配線基板が最も実装面側に配置されており、
前記配線基板における動作信号の入出力用の電極パッドと、電源供給用導体板および接地用導体板における接続電極とを、同一の実装面内に半導体デバイスの電極レイアウトと一致するように配してなり、
前記電源供給用導体板および前記接地用導体板は、前記配線基板を貫通するピン状導体を圧入され、該ピン状導体の端面が配線基板表面に位置することによって接続電極が形成されており、
前記電源供給用導体板および前記接地用導体板のうち、実装面に近い側に配置された導体板には前記実装面から遠い側に配置された導体板に圧入されたピン状導体に対応する位置に前記ピン状導体よりも大きな径を有する貫通孔が形成され、実装面から遠い側に配置された導体板に圧入されたピン状導体は、前記貫通孔を通ることによって前記貫通孔を有する導体板と非接触となっており、
前記配線基板において前記ピン状導体を貫通させる孔の周囲には、配線層の他の電極となる導体が露出しないように前記配線基板の配線層がパターニングされており、
前記実装面に半導体デバイスを接続していることを特徴とする半導体デバイスの実装構造。 - 前記半導体デバイスと前記接続電極との中間に双方向伸縮性のあるコンタクトピンを有しており、
前記半導体デバイスの電極パッドと前記接続電極とが前記コンタクトピンによって導通されることを特徴とする請求項2に記載の半導体デバイスの実装構造。 - 半導体デバイスに対して動作信号の入出力を行う配線基板と、
前記半導体デバイスに動作電源を供給するための電源供給用導体板および接地用導体板とを、絶縁体を介して積層した構造を有し、
前記配線基板、電源供給用導体板および接地用導体板は、前記配線基板が最も実装面側に配置されており、
前記配線基板における動作信号の入出力用の電極パッドと、電源供給用導体板および接地用導体板における接続電極とを、同一の実装面内に半導体デバイスの電極レイアウトと一致するように配してなり、
前記電源供給用導体板および前記接地用導体板は、前記配線基板を貫通するピン状導体を圧入され、該ピン状導体の端面が配線基板表面に位置することによって接続電極が形成されており、
前記電源供給用導体板および前記接地用導体板のうち、実装面に近い側に配置された導体板には前記実装面から遠い側に配置された導体板に圧入されたピン状導体に対応する位置に前記ピン状導体よりも大きな径を有する貫通孔が形成され、実装面から遠い側に配置された導体板に圧入されたピン状導体は、前記貫通孔を通ることによって前記貫通孔を有する導体板と非接触となっており、
前記配線基板において前記ピン状導体を貫通させる孔の周囲には、配線層の他の電極となる導体が露出しないように前記配線基板の配線層がパターニングされている実装部材と、
前記電源供給用導体板および接地用導体板を介して、前記実装部材に実装される半導体デバイスに動作電源を供給する電源供給手段とを備えていることを特徴とする半導体デバイスの駆動装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003373136A JP4493981B2 (ja) | 2003-10-31 | 2003-10-31 | 半導体デバイスの実装部材、半導体デバイスの実装構造、および半導体デバイスの駆動装置 |
TW093131141A TWI264078B (en) | 2003-10-31 | 2004-10-14 | Mounting member of semiconductor device, mounting configuration of semiconductor device, and drive unit of semiconductor device |
US10/975,013 US7312522B2 (en) | 2003-10-31 | 2004-10-28 | Mounting member of semiconductor device, mounting configuration of semiconductor device, and drive unit of semiconductor device |
KR1020040087188A KR101046871B1 (ko) | 2003-10-31 | 2004-10-29 | 반도체 디바이스의 실장부재, 반도체 디바이스의 패키지 및 반도체 디바이스의 구동장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2003373136A JP4493981B2 (ja) | 2003-10-31 | 2003-10-31 | 半導体デバイスの実装部材、半導体デバイスの実装構造、および半導体デバイスの駆動装置 |
Publications (2)
Publication Number | Publication Date |
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JP2005134337A JP2005134337A (ja) | 2005-05-26 |
JP4493981B2 true JP4493981B2 (ja) | 2010-06-30 |
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JP2003373136A Expired - Lifetime JP4493981B2 (ja) | 2003-10-31 | 2003-10-31 | 半導体デバイスの実装部材、半導体デバイスの実装構造、および半導体デバイスの駆動装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7312522B2 (ja) |
JP (1) | JP4493981B2 (ja) |
KR (1) | KR101046871B1 (ja) |
TW (1) | TWI264078B (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2009031394A1 (ja) * | 2007-09-03 | 2009-03-12 | Advantest Corporation | 電気接続構造、端子装置、ソケット、電子部品試験装置及びソケットの製造方法 |
JP4611367B2 (ja) * | 2007-12-13 | 2011-01-12 | アヅサテック株式会社 | 半導体集積回路用ソケット |
KR101706982B1 (ko) * | 2012-08-16 | 2017-02-16 | (주)테크윙 | 테스트핸들러용 인서트 |
US11723154B1 (en) * | 2020-02-17 | 2023-08-08 | Nicholas J. Chiolino | Multiwire plate-enclosed ball-isolated single-substrate silicon-carbide-die package |
Citations (4)
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US6188230B1 (en) * | 1997-12-16 | 2001-02-13 | Intel Corporation | Pickup chuck for double sided contact |
JP2001094008A (ja) * | 1999-09-27 | 2001-04-06 | Matsushita Electric Works Ltd | 半導体パッケージ |
US6359452B1 (en) * | 1998-07-22 | 2002-03-19 | Nortel Networks Limited | Method and apparatus for testing an electronic assembly |
US20020129974A1 (en) * | 2000-10-30 | 2002-09-19 | Smith Larry D. | Method and apparatus for distributing power to integrated circuits |
Family Cites Families (14)
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JPH04118984A (ja) | 1990-09-10 | 1992-04-20 | Fujitsu Ltd | 電子部品の実装構造 |
US5633598A (en) * | 1993-06-23 | 1997-05-27 | Everett Charles Technologies, Inc. | Translator fixture with module for expanding test points |
JPH0968557A (ja) | 1995-08-31 | 1997-03-11 | Mitsubishi Electric Corp | バーンインボード |
US6046597A (en) * | 1995-10-04 | 2000-04-04 | Oz Technologies, Inc. | Test socket for an IC device |
TW360790B (en) * | 1996-10-28 | 1999-06-11 | Atg Test Systems Gmbh | Printed circuit board test apparatus and method |
US5955888A (en) * | 1997-09-10 | 1999-09-21 | Xilinx, Inc. | Apparatus and method for testing ball grid array packaged integrated circuits |
CA2217591C (en) * | 1997-10-07 | 2003-07-29 | 700674 Ontario Limited, Doing Business As Carroll Associates | Wireless test fixture |
KR100314135B1 (ko) * | 1999-03-08 | 2001-11-16 | 윤종용 | Bga 패키지의 전기적 검사를 위한 소켓 및 이를 이용한검사방법 |
JP3973340B2 (ja) * | 1999-10-05 | 2007-09-12 | Necエレクトロニクス株式会社 | 半導体装置、配線基板、及び、それらの製造方法 |
JP2001116791A (ja) * | 1999-10-20 | 2001-04-27 | Fujitsu Ltd | 電子部品試験装置及び電気接続体 |
JP4701506B2 (ja) * | 2000-09-14 | 2011-06-15 | ソニー株式会社 | 回路ブロック体の製造方法、配線回路装置の製造方法並びに半導体装置の製造方法 |
JP2002185103A (ja) * | 2000-12-18 | 2002-06-28 | Kyocera Corp | 実装用基板の実装面における電極パッドの平坦性評価方法 |
US6541991B1 (en) * | 2001-05-04 | 2003-04-01 | Xilinx Inc. | Interface apparatus and method for testing different sized ball grid array integrated circuits |
US6974335B1 (en) * | 2005-01-25 | 2005-12-13 | International Business Machines Corporation | Interchangeable multi-form factor module socket |
-
2003
- 2003-10-31 JP JP2003373136A patent/JP4493981B2/ja not_active Expired - Lifetime
-
2004
- 2004-10-14 TW TW093131141A patent/TWI264078B/zh active
- 2004-10-28 US US10/975,013 patent/US7312522B2/en active Active
- 2004-10-29 KR KR1020040087188A patent/KR101046871B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US6188230B1 (en) * | 1997-12-16 | 2001-02-13 | Intel Corporation | Pickup chuck for double sided contact |
US6359452B1 (en) * | 1998-07-22 | 2002-03-19 | Nortel Networks Limited | Method and apparatus for testing an electronic assembly |
JP2001094008A (ja) * | 1999-09-27 | 2001-04-06 | Matsushita Electric Works Ltd | 半導体パッケージ |
US20020129974A1 (en) * | 2000-10-30 | 2002-09-19 | Smith Larry D. | Method and apparatus for distributing power to integrated circuits |
Also Published As
Publication number | Publication date |
---|---|
KR101046871B1 (ko) | 2011-07-05 |
US7312522B2 (en) | 2007-12-25 |
US20050092988A1 (en) | 2005-05-05 |
TW200531197A (en) | 2005-09-16 |
KR20050041955A (ko) | 2005-05-04 |
JP2005134337A (ja) | 2005-05-26 |
TWI264078B (en) | 2006-10-11 |
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