JP4481046B2 - 表面実装型セラミックパッケージ - Google Patents
表面実装型セラミックパッケージ Download PDFInfo
- Publication number
- JP4481046B2 JP4481046B2 JP2004079872A JP2004079872A JP4481046B2 JP 4481046 B2 JP4481046 B2 JP 4481046B2 JP 2004079872 A JP2004079872 A JP 2004079872A JP 2004079872 A JP2004079872 A JP 2004079872A JP 4481046 B2 JP4481046 B2 JP 4481046B2
- Authority
- JP
- Japan
- Prior art keywords
- bottom plate
- plate portion
- ceramic package
- metal plate
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Description
図1は、本発明の実施の形態1における表面実装型セラミックパッケージの断面図である。図1において、図3と同じ構成要素については同じ符号を用い、説明を省略する。
図2は、本発明の実施の形態2における表面実装型セラミックパッケージであり、図2(a)は斜視図を示し、図2(b)は図2(a)のX−X’線に沿った断面図である。図2(a)、(b)において、図3と同じ構成要素については同じ符号を用い、説明を省略する。
101 底板部
102 枠体部
103 電極
104 電極
105 端子
106 端子
107 支持部
108 水晶片
109 低融点ガラス
110 蓋体
Claims (1)
- セラミックから成る底板部と、該底板部上面にセラミックから成る枠体部を備え、前記枠体部上面に蓋体が封止されてなり、前記底板部第一主面に電子素子を支持する電極部が形成され、前記電極部から連続した端子が前記底板部側面に形成され、前記端子に金属板が接着され、該金属板が前記端子を挟んで前記底板部第二主面側に支持されたことを特徴とする表面実装型セラミックパッケージ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004079872A JP4481046B2 (ja) | 2004-03-19 | 2004-03-19 | 表面実装型セラミックパッケージ |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004079872A JP4481046B2 (ja) | 2004-03-19 | 2004-03-19 | 表面実装型セラミックパッケージ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005268580A JP2005268580A (ja) | 2005-09-29 |
JP4481046B2 true JP4481046B2 (ja) | 2010-06-16 |
Family
ID=35092799
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004079872A Expired - Fee Related JP4481046B2 (ja) | 2004-03-19 | 2004-03-19 | 表面実装型セラミックパッケージ |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4481046B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008118585A (ja) | 2006-11-08 | 2008-05-22 | Nippon Dempa Kogyo Co Ltd | 表面実装用の電子部品 |
JP6296687B2 (ja) * | 2012-04-27 | 2018-03-20 | キヤノン株式会社 | 電子部品、電子モジュールおよびこれらの製造方法。 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3434607B2 (ja) * | 1995-01-30 | 2003-08-11 | 新光電気工業株式会社 | 半導体装置用パッケージと該パッケージの集合体 |
JP2002231847A (ja) * | 2001-01-31 | 2002-08-16 | Kyocera Corp | 電子部品の製造方法 |
JP2004072381A (ja) * | 2002-08-06 | 2004-03-04 | Nippon Dempa Kogyo Co Ltd | 表面実装用の水晶デバイス及びその出荷方法 |
-
2004
- 2004-03-19 JP JP2004079872A patent/JP4481046B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005268580A (ja) | 2005-09-29 |
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