JP4435293B2 - Method for manufacturing printed wiring board - Google Patents

Method for manufacturing printed wiring board Download PDF

Info

Publication number
JP4435293B2
JP4435293B2 JP13285699A JP13285699A JP4435293B2 JP 4435293 B2 JP4435293 B2 JP 4435293B2 JP 13285699 A JP13285699 A JP 13285699A JP 13285699 A JP13285699 A JP 13285699A JP 4435293 B2 JP4435293 B2 JP 4435293B2
Authority
JP
Japan
Prior art keywords
resin material
dielectric constant
low dielectric
wiring board
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP13285699A
Other languages
Japanese (ja)
Other versions
JP2000323807A (en
Inventor
圭一 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Noda Screen Co Ltd
Original Assignee
Noda Screen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Noda Screen Co Ltd filed Critical Noda Screen Co Ltd
Priority to JP13285699A priority Critical patent/JP4435293B2/en
Publication of JP2000323807A publication Critical patent/JP2000323807A/en
Application granted granted Critical
Publication of JP4435293B2 publication Critical patent/JP4435293B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

【0001】
【発明の属する技術分野】
本発明はスルーホールを有するプリント配線基板の製造方法に関する。
【0002】
【従来の技術】
近年、高度情報化社会の時代を迎え、電子機器およびそれに使用されるプリント配線基板の小型化、高密度化、信号の高速処理化等が重要な課題となっている。
小型かつ高密度なプリント配線基板を製造するために、ビルドアップ法による回路パターンの形成が多く採用されている。その具体的な製造手順としては、例えば次のようなものがある。
【0003】
まず、基板の所要箇所にスルーホールを形成し、そのスルーホールの内周面および基板表面に化学メッキおよび電解メッキにより導体層を形成する。次に、スルーホール内に孔埋め印刷を行って樹脂材料を充填させ、この樹脂材料の硬化後に、基板表面からはみ出した樹脂部分を研磨して平滑基板を得る。そして、その後再び基板表面に化学メッキおよび電解メッキを行って導体層を形成し、その不要部分をエッチング法により除去して、所定の回路パターンを形成する。
【0004】
ところで、プリント配線基板上に形成された回路パターンでの信号伝搬速度は、基板材料の実効誘電率の平方根の逆数に比例することから、プリント配線基板を構成する基材、充填剤、樹脂などの誘電率はできるだけ低くすることが好ましい。従って、プリント配線基板の基材に形成されたスルーホールを孔埋めする樹脂材料としても、従来はこのような観点から、低誘電率のものが使用されている。
【0005】
【発明が解決しようとする課題】
ところが、従来から使用されている低誘電率の樹脂材料は、回路パターンとの密着性が充分であるとは言い難い。上述したように、近年の配線基板の小型化や高密度化に伴って回路パターンの複数層化がますます進んでいるが、積層される回路パターンの数が増加するほど、最下層の回路パターンにかかる力は大きくなる。このため、スルーホール内に充填される樹脂材料と、その樹脂材料上に形成される最下層の回路パターンとの密着性が悪いと、それらの接触部分で剥離が起こり易くなって、基板の信頼性が低下するという問題が起きる。
【0006】
このような問題を解決するために、スルーホール内に充填する樹脂材料中に金属粉を混合させたり、または樹脂の替わりに金属ペーストを埋め込むことによって、スルーホール内の充填材料と回路パターンとの密着性を高める試みがなされた。しかし、このような材料を使用すると、基板材料全体の誘電率が高くなって信号伝搬速度が大きく低下するため、好ましくない。
【0007】
本発明は上記事情に鑑みてなされたものであって、スルーホール内の樹脂材料の誘電率をこれまでと同様に低く保ちつつ、かつ回路パターンとの密着性にも優れるプリント配線基板の製造方法を提供することを目的とするものである。
【0009】
【課題を解決するための手段・作用及び効果】
本発明で製造されるプリント配線基板によれば、スルーホール内の深層部に位置する樹脂層は低誘電率を有するので、プリント配線基板の信号伝搬速度を従来と遜色なく高速に維持することができる。しかも、回路パターンと接する表層部の樹脂層は密着性に優れる樹脂で構成されているので、回路パターンと樹脂層とが剥離し難く、プリント配線基板の信頼性も併せて向上させ得るという優れた効果を奏する。
【0010】
低誘電率層を構成する樹脂材料としては、従来からプリント配線基板の孔埋め用樹脂として使用されているアクリレート−エポキシ系樹脂が好ましいが、その他にも誘電率が40以下と低いものが使用でき、熱膨張係数が基材と近い、高ガラス転移温度、低吸水率等の諸条件を満たすものであれば何でもよい。また、高密着性層を構成する樹脂材料としては、金属表面および異種樹脂材との界面接着性が良好であるものが好ましく、例えばエポキシ樹脂等が挙げられる。また、銅とのメッキ密着強度は1.0Kg/cm以上であることが好ましい。
【0011】
請求項1の発明に係るプリント配線基板の製造方法は、プリント配線基板に形成したスルーホール内に誘電率が40以下の低誘電率樹脂材料を充填する孔埋め工程と、この樹脂材料の硬化後の低誘電率層の表面部を除去し凹部を形成する凹部形成工程と、凹部に前記低誘電率層よりも回路パターンに対する密着性に優れた高密着性樹脂材料を充填する凹部埋め込み工程と、この樹脂材料の硬化後の高密着性層を研磨して基板を平滑化する研磨工程と、この高密着性層の表面を粗化する表面粗化工程と、その後基板の表面に回路パターンを形成する回路パターン形成工程とを実行するところに特徴を有する。
【0012】
上記製造方法によれば、スルーホール内はまずこれまでと同様の低誘電率樹脂材料によって充填されるから、従来の装置を用いて同様の条件でプリント配線基板のスルーホールを孔埋めすることが可能である(孔埋め工程)。次にこの低誘電率樹脂材料を硬化させた後、樹脂材料の表面部のみを溶解除去して凹部を形成し(凹部形成工程)、この凹部に高密着性の樹脂材料を充填する(凹部埋め込み工程)。そして樹脂材料を硬化させて基板の表面を平滑化する(研磨工程)と、スルーホール内の樹脂層は、その大部分を従来と同様の低誘電率の樹脂層としながら、表層部だけを高密着性の樹脂材料に置き替えた構成となる。さらにその樹脂表面を例えばバフ研磨機によって粗化する(表面粗化工程)ことで、その上に形成される回路パターンとの密着性を著しく向上させることができるという優れた効果を奏する。
【0013】
請求項2の発明に係るプリント配線基板の製造方法は、請求項1において、低誘電率樹脂材料は紫外線硬化及び熱硬化が可能な二段硬化型樹脂であるとともに高密着性樹脂材料は熱硬化型樹脂であって、孔埋め工程の後に紫外線を照射することによって低誘電率樹脂材料を一次硬化させ、上記凹部埋め込み工程の後に加熱することによって低誘電率樹脂材料と高密着性樹脂材料とを熱硬化させるところに特徴を有する。
【0014】
上記製造方法によれば、先にスルーホール内に孔埋めされる低誘電率の樹脂材料は二段硬化型樹脂であるため、まず孔埋めした後に紫外線を照射することによって、この樹脂材料は半硬化状態となる。そしてその状態で表層部の除去が実行されるので、凹部形成を迅速かつ容易に行うことができるという効果を奏する。
また、この低誘電率樹脂材料の熱硬化は、凹部に充填される高密着性樹脂材料の熱硬化と同時に行われるので、硬化工程をわざわざ増やす必要がない。
【0015】
【発明の実施の形態】
以下、本発明の一実施形態について図1ないし図8を参照して説明する。
本実施形態では、基材として、例えば厚さ100〜3000μmのガラスエポキシ基板11の両面に銅箔12を貼り付けてなる銅張り積層板10を使用している(図1参照)。この銅張り積層板10の所要箇所に、周知のドリル等を用いてスルーホール13を孔あけ加工し(図2参照)、化学メッキおよび電解メッキを行ってスルーホールの13の内周面も含めた全域に銅のメッキ層14を形成して、基板表面の導体層の厚みを約20μmとする(図3参照)。この配線基板に対して以下の工程が順次実行される。
【0016】
<孔埋め工程>
まず、配線基板の片側面から、紫外線および熱硬化の二段硬化型低誘電率樹脂材料15を印刷し、スルーホール13内を低誘電率樹脂材料15によって埋め込んだ状態とする。そしてこの低誘電率樹脂材料15を周知の露光装置によって露光して一次硬化させ、表面が平坦になるように例えばバフ研磨機やベルトサンダー等によって研磨する(図4参照)。
【0017】
<凹部形成工程>
次いでこの低誘電率樹脂材料15の表面部のみを、強アルカリ水溶液によって20〜50μm程度溶解除去する。すると、図5に示すように、スルーホール13の位置する部分に凹部16が形成される。
【0018】
<凹部埋め込み工程>
次に、この配線基板の両面に、例えばスクリーン印刷によって上記低誘電率樹脂材料15よりも密着性に優れた高密着性樹脂材料17を凹部16に充填する。そして加熱を行うと、熱によって深層部に位置する半硬化状態の低誘電率樹脂材料15が完全に硬化されると共に、表層部の高密着性樹脂材料17も硬化される。
【0019】
<研磨工程>
そして、スルーホール13から基板表面に盛り上がっている硬化後の高密着性樹脂材料17を、例えばバフ研磨することによって、平滑基板を得る(図6参照)。基板表面のスルーホールの位置には、高密着性樹脂材料17が露出した状態となる。
【0020】
<表面粗化工程>
さらに、研磨された平滑基板の樹脂部分の表面を、例えば過マンガン酸エッチングによって粗化する(図7参照)。これによって、樹脂上に形成される銅の回路パターンとの密着性がさらに向上する。
【0021】
<回路パターン形成工程>
そしてこのようにして得られた配線基板の表面に、化学メッキおよび電解メッキによって再度銅のメッキ層18を形成し、周知のフォトエッチング法によって下層のメッキ層14とともに不要部分を除去することにより、回路パターンを形成する。具体的には、例えば配線基板上にまず感光性のエッチングレジストを印刷し、乾燥後に回路パターンフィルムを重ねて露光する。これを現像すると、回路パターンとして残すべき部分に硬化したエッチングレジストが重ねられた配線基板が得られる。
そこで、この配線基板をエッチングレジスト液中に浸漬して、メッキ層14,18の不要部分を溶解させて除去する。そしてエッチングレジストを除去すれば、所要部分のメッキ層14,18が残り、回路パターンが完成する(図8参照)。
【0022】
<本実施形態の効果>
このように本実施形態のプリント配線基板およびその製造方法によれば、スルーホール内の樹脂層の表層部は、高密着性樹脂材料で構成される。従って、樹脂層とその上に形成される回路パターンとの密着性が高まって両者間の剥離が生じ難くなるため、基板の信頼性を大きく向上させることができる。
【0023】
具体的には、上記実施形態のような製造方法によって作製したプリント配線基板の、回路パターンのピール強度をJIS規格に基づいて測定したところ、スルーホール内に従来の低誘電率樹脂材料のみを埋め込んだ従来のものでは0.3Kg/cmであったのに対し、本実施形態のように表層部を高密着性樹脂材料に置き替えたものでは1.2Kg/cmと大きく向上した。
【0024】
また、深層部は低誘電率樹脂材料にて構成されているので、基板全体の誘電率を低く維持して、信号伝搬速度を従来と遜色なく高速に維持することができる。
また、本実施形態では、先に孔埋めされる深層部の低誘電率樹脂材料が二段硬化型樹脂であるため、半硬化状態で樹脂層の表面部を除去することができ、凹部形成を迅速かつ容易に行うことができるという効果を奏する。しかもこの深層部の樹脂層は、表層部の高密着性樹脂材料の熱硬化時に同時に完全硬化されるので、硬化工程が増えることがない。
【0025】
なお、上記実施形態では、凹部16の深さを20〜50μmとした場合に好ましい結果が得られた。これは、20μm以下では表層部の高密着性層が薄すぎて、過マンガン酸エッチングの際にエッチング液が表層部と深層部との樹脂界面まで入り込み、樹脂界面での剥離が起こり易くなるためと考えられる。また、50μm以上になると、凹部16が深くなり過ぎて、凹部埋め込み工程において印刷不良が起こり易くなるためと考えられる。ただし、基材表面の導体層の厚みや、孔径等によって、凹部深さの適切な範囲は相違するから、上記実施形態の数値に限定されるものではない。
【0026】
<他の実施形態>
本発明は上記記述及び図面によって説明した実施形態に限定されるものではなく、例えば次のような実施形態も本発明の技術的範囲に含まれ、さらに、下記以外にも要旨を逸脱しない範囲内で種々変更して実施することができる。
(1)上記実施形態では、サブトラクティブ法によって回路パターンを形成したが、これに限らず、アディティブ法等、他の方法によって回路パターンを形成する構成としてもよい。
(2)上記実施形態では、低誘電率樹脂材料を片側面からスルーホール内に充填させたが、両側面から充填させてもよい。
(3)上記実施形態では、二段硬化型の低誘電率樹脂材料を使用したが、これに限らず、熱硬化型あるいは紫外線硬化型樹脂等を使用してもよい。
(4)上記実施形態では、樹脂層の上に回路パターンを単層だけ形成したが、これに限らず、複数層積層してよいことはもちろんである。
【図面の簡単な説明】
【図1】本発明の一実施形態に係る配線基板の基材の断面図
【図2】同じく孔あけ工程を示す配線基板の断面図
【図3】同じくメッキ工程を示す配線基板の断面図
【図4】同じく孔埋め工程を示す配線基板の断面図
【図5】同じく凹部形成工程を示す配線基板の断面図
【図6】同じく凹部埋め込み工程を示す配線基板の断面図
【図7】同じく表面粗化工程を示す配線基板の断面図
【図8】同じく回路パターン形成工程を示す配線基板の断面図
【符号の説明】
10…銅張り積層板
13…スルーホール
14、18…メッキ層
15…低誘電率樹脂材料
16…凹部
17…高密着性樹脂材料
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a process for producing a printed wiring board having a through-hole.
[0002]
[Prior art]
In recent years, with the era of highly information-oriented society, downsizing, high density, high-speed signal processing, etc. of electronic devices and printed wiring boards used for them have become important issues.
In order to manufacture a small and high density printed wiring board, formation of a circuit pattern by a build-up method is often employed. Specific manufacturing procedures include, for example, the following.
[0003]
First, a through hole is formed in a required portion of the substrate, and a conductor layer is formed on the inner peripheral surface of the through hole and the substrate surface by chemical plating and electrolytic plating. Next, filling printing is performed in the through holes to fill the resin material, and after the resin material is cured, the resin portion protruding from the substrate surface is polished to obtain a smooth substrate. Then, chemical plating and electrolytic plating are again performed on the substrate surface to form a conductor layer, and unnecessary portions thereof are removed by an etching method to form a predetermined circuit pattern.
[0004]
By the way, since the signal propagation speed in the circuit pattern formed on the printed wiring board is proportional to the reciprocal of the square root of the effective dielectric constant of the board material, the base material, filler, resin, etc. constituting the printed wiring board The dielectric constant is preferably as low as possible. Accordingly, conventionally, a resin material having a low dielectric constant is also used as a resin material for filling a through hole formed in a base material of a printed wiring board from such a viewpoint.
[0005]
[Problems to be solved by the invention]
However, it is difficult to say that the resin material having a low dielectric constant conventionally used has sufficient adhesion to the circuit pattern. As described above, with the recent trend toward miniaturization and higher density of wiring boards, the number of circuit patterns has been increasing. However, as the number of circuit patterns stacked increases, The force applied to increases. For this reason, if the adhesion between the resin material filled in the through-hole and the lowermost circuit pattern formed on the resin material is poor, peeling easily occurs at those contact portions, and the reliability of the substrate The problem of the decline of sex occurs.
[0006]
In order to solve such problems, the metal material is mixed in the resin material to be filled in the through hole, or the metal paste is embedded in place of the resin so that the filling material in the through hole and the circuit pattern are mixed. Attempts were made to increase adhesion. However, the use of such a material is not preferable because the dielectric constant of the entire substrate material is increased and the signal propagation speed is greatly reduced.
[0007]
The present invention has been made in view of the above circumstances, and is a method for producing a printed wiring board that maintains the dielectric constant of a resin material in a through hole as low as before and is excellent in adhesion to a circuit pattern. Is intended to provide .
[0009]
[Means, actions and effects for solving the problems]
According to the printed wiring board manufactured by the present invention , since the resin layer located in the deep layer portion in the through hole has a low dielectric constant, the signal propagation speed of the printed wiring board can be maintained at a high speed comparable to the conventional one. it can. In addition, since the resin layer of the surface layer portion in contact with the circuit pattern is composed of a resin having excellent adhesion, the circuit pattern and the resin layer are difficult to peel off, and the reliability of the printed wiring board can be improved. There is an effect.
[0010]
As the resin material constituting the low dielectric constant layer, an acrylate-epoxy resin that has been conventionally used as a resin for filling holes in printed wiring boards is preferable, but other materials having a low dielectric constant of 40 or less can be used. Any material may be used as long as it satisfies various conditions such as a high glass transition temperature and a low water absorption rate, which has a thermal expansion coefficient close to that of the base material. Moreover, as a resin material which comprises a highly adhesive layer, what has favorable interface adhesiveness with a metal surface and a dissimilar resin material is preferable, for example, an epoxy resin etc. are mentioned. Further, the plating adhesion strength with copper is preferably 1.0 kg / cm or more.
[0011]
According to a first aspect of the present invention, there is provided a printed wiring board manufacturing method comprising: a hole filling step of filling a through hole formed in a printed wiring board with a low dielectric constant resin material having a dielectric constant of 40 or less; and after the resin material is cured A recess forming step for removing the surface portion of the low dielectric constant layer to form a recess, and a recess embedding step for filling the recess with a highly adhesive resin material having better adhesion to the circuit pattern than the low dielectric constant layer, A polishing process for smoothing the substrate by polishing the highly adhesive layer after curing of the resin material, a surface roughening process for roughening the surface of the highly adhesive layer, and then forming a circuit pattern on the surface of the substrate The circuit pattern forming process is performed.
[0012]
According to the above manufacturing method, since the inside of the through hole is first filled with the same low dielectric constant resin material as before, the through hole of the printed wiring board can be filled under the same conditions using a conventional apparatus. Possible (hole filling process). Next, after curing this low dielectric constant resin material, only the surface portion of the resin material is dissolved and removed to form a recess (recess formation process), and this recess is filled with a highly adhesive resin material (recess embedding) Process). When the resin material is cured and the surface of the substrate is smoothed (polishing process), the resin layer in the through-hole is mostly made of a resin layer having a low dielectric constant similar to the conventional one, while only the surface layer portion is increased. The structure is replaced with an adhesive resin material. Furthermore, the resin surface is roughened by, for example, a buffing machine (surface roughening step), thereby providing an excellent effect that adhesion with a circuit pattern formed thereon can be remarkably improved.
[0013]
According to a second aspect of the present invention, there is provided a printed wiring board manufacturing method according to the first aspect, wherein the low dielectric constant resin material is a two-stage curable resin capable of ultraviolet curing and thermosetting, and the high adhesion resin material is thermosetting. A low-dielectric-constant resin material that is primarily cured by irradiating ultraviolet rays after the hole-filling step, and heated after the recess-filling step. Characterized by heat curing.
[0014]
According to the above manufacturing method, since the low dielectric constant resin material previously filled in the through hole is a two-stage curable resin, the resin material is half-filled by first irradiating with ultraviolet rays after filling the hole. It becomes a cured state. And since the removal of a surface layer part is performed in that state, there exists an effect that a recessed part formation can be performed rapidly and easily.
In addition, since the thermosetting of the low dielectric constant resin material is performed simultaneously with the thermosetting of the high adhesion resin material filled in the recess, it is not necessary to increase the number of curing steps.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
In this embodiment, the copper clad laminated board 10 which affixes the copper foil 12 on both surfaces of the glass epoxy board | substrate 11 with a thickness of 100-3000 micrometers is used as a base material (refer FIG. 1). A through hole 13 is drilled in a required portion of the copper-clad laminate 10 using a known drill or the like (see FIG. 2), and chemical plating and electrolytic plating are performed to include the inner peripheral surface of the through hole 13. Then, a copper plating layer 14 is formed over the entire area so that the thickness of the conductor layer on the substrate surface is about 20 μm (see FIG. 3). The following steps are sequentially performed on this wiring board.
[0016]
<Hole filling process>
First, the two-stage curing type low dielectric constant resin material 15 of ultraviolet and heat curing is printed from one side of the wiring board, and the through hole 13 is filled with the low dielectric constant resin material 15. Then, this low dielectric constant resin material 15 is exposed by a well-known exposure apparatus, is primarily cured, and is polished by, for example, a buffing machine or a belt sander so that the surface becomes flat (see FIG. 4).
[0017]
<Recess formation process>
Next, only the surface portion of the low dielectric constant resin material 15 is dissolved and removed by a strong alkaline aqueous solution by about 20 to 50 μm. Then, as shown in FIG. 5, a recess 16 is formed in the portion where the through hole 13 is located.
[0018]
<Recess filling process>
Next, the recesses 16 are filled with a high adhesion resin material 17 having better adhesion than the low dielectric constant resin material 15 on both sides of the wiring board by, for example, screen printing. When heating is performed, the semi-cured low dielectric constant resin material 15 located in the deep layer portion is completely cured by heat, and the high adhesion resin material 17 in the surface layer portion is also cured.
[0019]
<Polishing process>
Then, the cured highly adhesive resin material 17 rising from the through hole 13 to the substrate surface is, for example, buffed to obtain a smooth substrate (see FIG. 6). The highly adhesive resin material 17 is exposed at the position of the through hole on the substrate surface.
[0020]
<Surface roughening process>
Further, the surface of the polished resin portion of the smooth substrate is roughened by, for example, permanganic acid etching (see FIG. 7). This further improves the adhesion with the copper circuit pattern formed on the resin.
[0021]
<Circuit pattern formation process>
Then, a copper plating layer 18 is formed again on the surface of the wiring board thus obtained by chemical plating and electrolytic plating, and unnecessary portions are removed together with the lower plating layer 14 by a known photoetching method. A circuit pattern is formed. Specifically, for example, a photosensitive etching resist is first printed on a wiring substrate, and after drying, a circuit pattern film is overlaid and exposed. When this is developed, a wiring board is obtained in which a cured etching resist is superimposed on a portion to be left as a circuit pattern.
Therefore, this wiring board is immersed in an etching resist solution, and unnecessary portions of the plating layers 14 and 18 are dissolved and removed. Then, if the etching resist is removed, the required portions of the plating layers 14 and 18 remain, and the circuit pattern is completed (see FIG. 8).
[0022]
<Effect of this embodiment>
As described above, according to the printed wiring board and the manufacturing method thereof of the present embodiment, the surface layer portion of the resin layer in the through hole is made of a highly adhesive resin material. Accordingly, the adhesiveness between the resin layer and the circuit pattern formed thereon is increased, and separation between the two is less likely to occur, so that the reliability of the substrate can be greatly improved.
[0023]
Specifically, when the peel strength of the circuit pattern of the printed wiring board produced by the manufacturing method as in the above embodiment was measured based on the JIS standard, only the conventional low dielectric constant resin material was embedded in the through hole. However, while the conventional one was 0.3 kg / cm, the one obtained by replacing the surface layer portion with a highly adhesive resin material as in the present embodiment was greatly improved to 1.2 kg / cm.
[0024]
Further, since the deep layer portion is made of a low dielectric constant resin material, the dielectric constant of the entire substrate can be kept low, and the signal propagation speed can be maintained at a high speed comparable to that of the prior art.
Further, in this embodiment, since the low dielectric constant resin material in the deep layer portion that is previously filled in the hole is a two-stage curable resin, the surface portion of the resin layer can be removed in a semi-cured state, thereby forming a recess. There is an effect that it can be performed quickly and easily. In addition, since the resin layer in the deep layer portion is completely cured simultaneously with the thermosetting of the highly adhesive resin material in the surface layer portion, the number of curing steps does not increase.
[0025]
In the above embodiment, a preferable result was obtained when the depth of the recess 16 was 20 to 50 μm. This is because, when the thickness is 20 μm or less, the high adhesion layer of the surface layer portion is too thin, and the etching liquid enters the resin interface between the surface layer portion and the deep layer portion during permanganic acid etching, and peeling at the resin interface is likely to occur. it is conceivable that. On the other hand, when the thickness is 50 μm or more, it is considered that the concave portion 16 becomes too deep, and printing defects easily occur in the concave portion embedding process. However, the appropriate range of the recess depth varies depending on the thickness of the conductor layer on the surface of the base material, the hole diameter, and the like, and is not limited to the numerical values in the above embodiment.
[0026]
<Other embodiments>
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention, and further, within the scope not departing from the gist of the invention other than the following. Various modifications can be made.
(1) In the above embodiment, the circuit pattern is formed by the subtractive method. However, the present invention is not limited to this, and the circuit pattern may be formed by another method such as an additive method.
(2) In the above embodiment, the low dielectric constant resin material is filled into the through hole from one side surface, but may be filled from both side surfaces.
(3) In the above-described embodiment, the two-stage curable low dielectric constant resin material is used. However, the present invention is not limited to this, and a thermosetting or ultraviolet curable resin may be used.
(4) In the above embodiment, only a single layer of the circuit pattern is formed on the resin layer. However, the present invention is not limited to this, and it goes without saying that a plurality of layers may be laminated.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a substrate of a wiring board according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the wiring board that also shows a drilling process. 4 is a cross-sectional view of the wiring board that also shows the hole filling process. FIG. 5 is a cross-sectional view of the wiring board that also shows the recessed portion forming process. FIG. Cross-sectional view of the wiring board showing the roughening process. [FIG. 8] Cross-sectional view of the wiring board showing the circuit pattern forming process.
DESCRIPTION OF SYMBOLS 10 ... Copper-clad laminate 13 ... Through-hole 14, 18 ... Plating layer 15 ... Low dielectric constant resin material 16 ... Concave part 17 ... High adhesion resin material

Claims (2)

プリント配線基板に形成したスルーホール内に誘電率が40以下の低誘電率樹脂材料を充填する孔埋め工程と、この樹脂材料の硬化後の低誘電率層の表面部を除去し凹部を形成する凹部形成工程と、前記凹部に前記低誘電率層よりも回路パターンに対する密着性に優れた高密着性樹脂材料を充填する凹部埋め込み工程と、この樹脂材料の硬化後の高密着性層を研磨して基板を平滑化する研磨工程と、この高密着性層の表面を粗化する表面粗化工程と、その後基板の表面に回路パターンを形成する回路パターン形成工程とを実行することを特徴とするプリント配線基板の製造方法。A hole filling step for filling a through hole formed in the printed wiring board with a low dielectric constant resin material having a dielectric constant of 40 or less, and removing a surface portion of the low dielectric constant layer after curing of the resin material to form a recess. Polishing the recessed portion forming step, filling the recessed portion with a highly adhesive resin material having better adhesion to the circuit pattern than the low dielectric constant layer, and polishing the highly adhesive layer after curing of the resin material A polishing step for smoothing the substrate, a surface roughening step for roughening the surface of the highly adhesive layer, and a circuit pattern forming step for forming a circuit pattern on the surface of the substrate. A method for manufacturing a printed wiring board. 前記低誘電率樹脂材料は紫外線硬化及び熱硬化が可能な二段硬化型樹脂であるとともに前記高密着性樹脂材料は熱硬化型樹脂であって、前記孔埋め工程の後に紫外線を照射することによって前記低誘電率樹脂材料を一次硬化させ、上記凹部埋め込み工程の後に加熱することによって前記低誘電率樹脂材料と前記高密着性樹脂材料とを熱硬化させることを特徴とする請求項1に記載のプリント配線基板の製造方法。The low dielectric constant resin material is a two-stage curable resin capable of ultraviolet curing and thermosetting, and the high adhesion resin material is a thermosetting resin, and is irradiated with ultraviolet rays after the hole filling step. 2. The low dielectric constant resin material is first cured, and the low dielectric constant resin material and the high adhesion resin material are thermally cured by heating after the recess embedding step. A method for manufacturing a printed wiring board.
JP13285699A 1999-05-13 1999-05-13 Method for manufacturing printed wiring board Expired - Fee Related JP4435293B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13285699A JP4435293B2 (en) 1999-05-13 1999-05-13 Method for manufacturing printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13285699A JP4435293B2 (en) 1999-05-13 1999-05-13 Method for manufacturing printed wiring board

Publications (2)

Publication Number Publication Date
JP2000323807A JP2000323807A (en) 2000-11-24
JP4435293B2 true JP4435293B2 (en) 2010-03-17

Family

ID=15091135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13285699A Expired - Fee Related JP4435293B2 (en) 1999-05-13 1999-05-13 Method for manufacturing printed wiring board

Country Status (1)

Country Link
JP (1) JP4435293B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100992720B1 (en) * 2003-07-24 2010-11-05 엘지이노텍 주식회사 Via-hole filling method of PCB
CN111787684A (en) * 2020-07-20 2020-10-16 昆山大洋电路板有限公司 Many PP stacks structure and melts landfill hole response discernment circuit board

Also Published As

Publication number Publication date
JP2000323807A (en) 2000-11-24

Similar Documents

Publication Publication Date Title
JP4405993B2 (en) Method for manufacturing high-density printed circuit board
JP2013211431A (en) Electronic component to be built in printed wiring board and manufacturing method of component built-in printed wiring board
JP2009177153A (en) Wiring substrate and its manufacturing method
JP2000349435A (en) Multilayered printed wiring board and manufacture thereof
KR100861619B1 (en) Radiant heat printed circuit board and fabricating method of the same
US6938336B2 (en) Methods of manufacturing board having throughholes filled with resin and multi-layered printed wiring board using the board
JP2007288022A (en) Multilayer printed wiring board and its manufacturing method
JP3619421B2 (en) Manufacturing method of multilayer wiring board
JP2004152904A (en) Electrolytic copper foil, film and multilayer wiring substrate therewith, and method of manufacturing the same
JP2002324974A (en) Multilayer printed wiring board and method of manufacturing multilayer printed wiring board
KR100722599B1 (en) All layer inner via hall printed circuit board and the manufacturing method that utilize the fill plating
JP4435293B2 (en) Method for manufacturing printed wiring board
JP2001308536A (en) Multilayer board and method of its manufacture
JP2009176897A (en) Multilayer printed wiring board and manufacturing method therefor
JP3674662B2 (en) Wiring board manufacturing method
JP2000332387A (en) Manufacture of printed wiring board
KR100754061B1 (en) Method of fabricating printed circuit board
JP2010129997A (en) Printed-circuit board with embedded pattern, and its manufacturing method
KR100584974B1 (en) Method for fabricating printed circuit board using liquid-type photoresist
JP2002252459A (en) Multilayer wiring board and its manufacturing method
JP2002204043A (en) Circuit board and its manufacturing method
JP3071722B2 (en) Method for manufacturing multilayer printed wiring board
KR100905567B1 (en) Fabricating Method of Printed Circuit Board
KR100807487B1 (en) Method of fabricating printed circuit board
JPH09260849A (en) Inner layer circuit board manufacturing method and multilayered printed wiring board manufacturing method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060510

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20070717

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20081216

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090108

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090309

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20090604

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090904

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20091104

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20091217

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20091223

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130108

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130108

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140108

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees