JP2002252459A - Multilayer wiring board and its manufacturing method - Google Patents

Multilayer wiring board and its manufacturing method

Info

Publication number
JP2002252459A
JP2002252459A JP2001050978A JP2001050978A JP2002252459A JP 2002252459 A JP2002252459 A JP 2002252459A JP 2001050978 A JP2001050978 A JP 2001050978A JP 2001050978 A JP2001050978 A JP 2001050978A JP 2002252459 A JP2002252459 A JP 2002252459A
Authority
JP
Japan
Prior art keywords
conductor
wiring layer
layer
insulating layer
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001050978A
Other languages
Japanese (ja)
Other versions
JP3631682B2 (en
Inventor
Akihiko Nishimoto
昭彦 西本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001050978A priority Critical patent/JP3631682B2/en
Priority to US10/083,691 priority patent/US6623844B2/en
Publication of JP2002252459A publication Critical patent/JP2002252459A/en
Application granted granted Critical
Publication of JP3631682B2 publication Critical patent/JP3631682B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • ing And Chemical Polishing (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a highly reliable multilayer wiring board which can prevent via-hole conductors from causing a resistance change even under a high-humidity environmental condition by preventing the instruction of moisture into the board through an interface between conductor wiring layers and insulating layers by improving adhesion between the layers. SOLUTION: This multilayer wiring board is provided with the insulating layers 1 containing at least a thermosetting resin, respectively, the conductor wiring layers 2 buried in the surfaces of the layers 1, and the via-hole conductors 3 which are filled with conductor component containing metallic powder into through holes for connecting the wiring layers 2 to each other. The cross sections of the wiring layers 2 connected with the conductors 3 are formed in inverted trapezoids having formed angles (θ) of 45-80 deg. and side faces having surface roughness (Ra) of >=0.2 μm. In addition, an organic matter containing a hydrophilic group and a hydrophobic group is interposed between the contact faces of the wiring layers 2 and insulating layers 1 on the side faces of the wiring layers 2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えば、多層配線
基板及び半導体素子収納用パッケージなどに適した多層
配線基板とその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board suitable for, for example, a multilayer wiring board and a package for accommodating a semiconductor device, and a method of manufacturing the same.

【0002】[0002]

【従来技術】近年、電子機器は小型化が進んでいるが、
近年携帯情報端末の発達や、コンピューターを持ち運ん
で操作するいわゆるモバイルコンピューティングの普及
によってさらに小型、薄型且つ高精細の多層配線基板が
求められる傾向にある。
2. Description of the Related Art In recent years, electronic devices have been reduced in size.
In recent years, with the development of portable information terminals and the spread of so-called mobile computing in which a computer is carried and operated, there is a tendency that a smaller, thinner, and higher-definition multilayer wiring board is required.

【0003】また、通信機器に代表されるように、高速
動作が求められる電子機器が広く使用されるようになっ
てきた。高速動作が求められるということは、高い周波
数の信号に対し、正確なスイッチングが可能であるなど
多種な要求を含んでいる。そのような電子機器に対応す
るため、高速な動作に適した多層プリント配線板が求め
られている。
[0003] Further, electronic devices that require high-speed operation, such as communication devices, have been widely used. The requirement for high-speed operation includes various requirements such as accurate switching of high-frequency signals. In order to cope with such electronic devices, a multilayer printed wiring board suitable for high-speed operation is required.

【0004】高速な動作を行うためには、配線の長さを
短くし、電気信号の伝播に要する時間を短縮することが
必要である。配線の長さを短縮するために、配線の幅を
細くし、配線の間隙を小さくするという、小型、薄型且
つ高精細の多層配線基板が求められる傾向にある。
In order to perform high-speed operation, it is necessary to reduce the length of wiring and shorten the time required for transmitting an electric signal. In order to reduce the length of the wiring, there is a tendency for a small, thin, and high-definition multilayer wiring substrate in which the width of the wiring is reduced and the gap between the wirings is reduced.

【0005】そのような高密度配線の要求に対応するた
め、ビルドアツプ法と呼ばれる製造方法が用いられてい
る。ビルドアップ法の基本構造としては、JPCA規格
では(1)ベース+ビルドアップ法、(2)全層ビルド
アップ法の2種類に分類されている。
In order to meet such a demand for high-density wiring, a manufacturing method called a build-up method is used. The basic structure of the build-up method is classified into two types in the JPCA standard: (1) base + build-up method and (2) all-layer build-up method.

【0006】(1)ベース+ビルドアップ法は、両面銅
張ガラスエポキシ基板などの絶縁基板の表面に導体配線
層やスルーホール導体などが形成されたコア基板の表面
に感光性樹脂を塗布後、露光現象してバイアホールを形
成した後、感光性絶縁層の表面全面に銅などのメッキ層
を施し、その後、メッキ層に感光性レジストを塗布し、
回路パターンを露光、現像した後、非レジスト形成部を
エッチングして回路を形成した後、レジストを除去して
導体配線層を作製するもので、この工程をを繰り返して
多層化するものである。
(1) In the base + build-up method, a photosensitive resin is applied to the surface of a core substrate having a conductor wiring layer, a through-hole conductor, etc. formed on the surface of an insulating substrate such as a double-sided copper-clad glass epoxy substrate. After the exposure phenomenon to form via holes, apply a plating layer such as copper to the entire surface of the photosensitive insulating layer, and then apply a photosensitive resist to the plating layer,
After exposing and developing the circuit pattern, the non-resist forming portion is etched to form a circuit, and then the resist is removed to form a conductor wiring layer. This process is repeated to form a multilayer.

【0007】また、(2)全層ビルドアップの製造方法
は、例えば特許2587593号の様に、絶縁層にレー
ザーなどでバイアホールを形成し、そのバイアホール内
に導電性ペーストを充填することにより絶縁層の表面に
形成された導体配線層を電気的に接続して配線層を形成
し、このように作製した配線層を繰り返して形成して多
層化するものである。
[0007] (2) A method of manufacturing an all-layer build-up is to form a via hole in an insulating layer with a laser or the like and fill a conductive paste in the via hole as disclosed in, for example, Japanese Patent No. 2587593. A wiring layer is formed by electrically connecting the conductive wiring layers formed on the surface of the insulating layer, and the wiring layer thus manufactured is repeatedly formed to form a multilayer.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、(1)
ベース+ビルドアップ法では、絶縁層として感光性エポ
キシ樹脂などが多用されるが、エポキシ樹脂はもともと
ガラス転移点が低い上に感光性としたことで吸水率が増
加し、高温高湿放置で絶縁性が低下するなど信頼性が低
下するという問題がある。また、コア基板表面には銅箔
から形成された導体配線層の厚さ分の凹凸が存在してお
り、ビルドアップ法に使用する感光性樹脂は液状のた
め、コア基板表面の凹凸がビルドアップされた多層配線
層表面にまで反映され、完成品の基板表面にも凹凸が形
成され、フリップチップ等のシリコンチップ実装には不
適であった。また、温度サイクル試験や高温高湿試験に
おいてコア基板とビルドアップ層の絶縁層との界面で剥
離が生じやすいものであった。
However, (1)
In the base + build-up method, photosensitive epoxy resin is often used as the insulating layer. However, the epoxy resin originally has a low glass transition point and is made photosensitive to increase the water absorption rate, and it is insulated when left at high temperature and high humidity. There is a problem that reliability decreases, such as deterioration of reliability. In addition, the surface of the core substrate has irregularities corresponding to the thickness of the conductor wiring layer formed of copper foil, and the photosensitive resin used in the build-up method is in a liquid state. The unevenness was also reflected on the surface of the finished substrate, which was not suitable for mounting on a silicon chip such as a flip chip. Further, in a temperature cycle test or a high-temperature and high-humidity test, peeling was likely to occur at the interface between the core substrate and the insulating layer of the build-up layer.

【0009】上記問題に対して様々な解決策が提案され
ており、エレクトロニクス実装技術誌1998,1(V
ol.14 No.1)には、ステンレス板にパターン
めっき法で作製した回路パターンを積層プレスによりパ
ターンを転写することによって平滑なビルドアップ基板
を製造する方法が記載されている。しかし、コア基板と
ビルドアップ層の絶縁樹脂との化学的な結合を改善する
には至っておらず、信頼性の点で問題があった。
Various solutions to the above problem have been proposed, and are described in Electronics Packaging Technology Magazine 1998, 1 (V
ol. 14 No. 1) describes a method for producing a smooth build-up substrate by transferring a circuit pattern formed on a stainless steel plate by a pattern plating method using a lamination press. However, the chemical bonding between the core substrate and the insulating resin of the build-up layer has not been improved, and there has been a problem in reliability.

【0010】また、前記(2)全層ビルドアップ法で
は、バイア導体を、貫通孔内への導電性ペーストの充填
によって形成するものの高温放置等の信頼性試験におい
てバイア導体が酸化し、電気抵抗が上昇するという問題
がある。また、導体配線層を絶縁層の表面に埋設して表
面の平坦化を図った多層配線基板も提案されているが、
このような導体配線層が埋設された配線基板において
も、導体配線層の埋設側側面と絶縁層中の有機樹脂との
密着力が充分でなく、導体配線層と絶縁層との界面から
水分が浸入しバイア導体が酸化して抵抗を増大させると
いう問題があった。
In the above (2) all-layer build-up method, a via conductor is formed by filling a conductive paste into a through hole, but the via conductor is oxidized in a reliability test such as leaving at a high temperature, and the electric resistance is lowered. There is a problem that rises. Also, a multilayer wiring board in which a conductor wiring layer is buried in the surface of the insulating layer to achieve a flat surface has been proposed.
Even in a wiring board in which such a conductive wiring layer is buried, the adhesion between the buried side surface of the conductive wiring layer and the organic resin in the insulating layer is not sufficient, and moisture is generated from the interface between the conductive wiring layer and the insulating layer. There is a problem in that the via conductor invades and oxidizes the via conductor to increase the resistance.

【0011】本発明は、上記のような従来の多層配線基
板における課題を解決することを目的とするものであ
り、具体的には、導体配線層と絶縁層との密着性を高
め、導体配線層と絶縁層との界面からの水分の侵入を防
止し、高湿度環境下でもバイア導体の抵抗変化のない信
頼性の高い多層配線基板と、これを容易に製造すること
のできる製造方法を提供することを目的とするものであ
る。
An object of the present invention is to solve the above-mentioned problems in the conventional multilayer wiring board, and more specifically, to improve the adhesion between the conductive wiring layer and the insulating layer, To provide a highly reliable multilayer wiring board that prevents moisture penetration from the interface between the layer and the insulating layer and that does not change the resistance of the via conductor even in a high-humidity environment, and a manufacturing method that can easily manufacture this. It is intended to do so.

【0012】[0012]

【課題を解決するための手段】本発明の多層配線基板
は、少なくとも熱硬化性樹脂を含む絶縁層と、該絶縁層
表面に埋設された導体配線層と、導体配線層間を接続す
るために貫通孔に金属粉末を含む導体成分を充填された
バイア導体とを具備する多層配線基板において、前記多
層配線基板の少なくとも表面の導体配線層側面の表面粗
さ(Ra)が0.2μm以上で絶縁層との界面に親水基
と疎水基を含有する有機物が存在することを特徴とする
ものである。さらに詳細には、前記絶縁層の熱硬化性樹
脂の吸水率が0.5%以下、前記導体配線層が金属箔を
エッチングして得られたこと、前記絶縁層に埋設された
導体配線層が逆台形で形成角(θ)が45°〜80°で
あることである。
According to the present invention, there is provided a multilayer wiring board comprising at least an insulating layer containing a thermosetting resin, a conductive wiring layer buried on the surface of the insulating layer, and a through-hole for connecting the conductive wiring layers. A via conductor filled with a conductor component containing a metal powder in a hole, wherein the surface roughness (Ra) of at least the surface of the conductor wiring layer on at least the surface of the multilayer wiring board is 0.2 μm or more and the insulating layer Characterized by the presence of an organic substance containing a hydrophilic group and a hydrophobic group at the interface with. More specifically, the water absorption of the thermosetting resin of the insulating layer is 0.5% or less, the conductive wiring layer is obtained by etching a metal foil, and the conductive wiring layer embedded in the insulating layer is It is an inverted trapezoid and the formation angle (θ) is 45 ° to 80 °.

【0013】さらに、本発明の多層配線基板の製造方法
によれば、(a)金属箔を接着剤を介して樹脂フィルム
に接着させる工程と、(b)(a)によって作製された
前記樹脂フィルムの金属箔表面に、鏡像の配線パターン
状にレジストを塗布後、非レジスト部をエッチングによ
って除去して、断面が、形成角45°〜80°の台形型
の導体配線層を形成する工程と、(c)(b)によって
形成された前記導体配線層の台形型の側面を表面粗さ
(Ra)を0.2μm以上に粗化する工程と、(d)
(c)の粗化処理後の前記導体配線層の台形型の側面
に、親水基と疎水基を含む有機物を塗布する工程と、
(e)前記導体配線層上面のレジストを除去する工程
と、(f)少なくとも熱硬化性樹脂を含有するBステー
ジ状の絶縁層に、貫通孔を形成し、金属粉末を含む導体
ペーストを充填してバイア導体を形成する工程と、
(g)(a)〜(e)で作製した樹脂フィルム表面の導
体配線層を(f)で作製した絶縁層表面のバイア導体形
成箇所に積層加圧した後、樹脂フィルムを剥がして導体
配線層を転写し、絶縁層表面に導体配線層を埋設した配
線層を形成する工程と、(h)(a)〜(g)で作製し
た複数の配線層を積層し、圧力をかけながら一括で硬化
する工程と、を含むことを特徴とするものである。ま
た、前記樹脂フィルム表面に形成された導体配線層の断
面が、形成角(θ)が45°〜80°の台形型であるこ
とが密着性を高める上で望ましい。
Further, according to the method for manufacturing a multilayer wiring board of the present invention, (a) a step of adhering a metal foil to a resin film via an adhesive, and (b) the resin film produced by (a) A step of forming a trapezoidal conductor wiring layer having a cross section of 45 ° to 80 ° by applying a resist in a mirror image wiring pattern on the surface of the metal foil and removing the non-resist portion by etching; (C) roughening the trapezoidal side surface of the conductor wiring layer formed by (b) to a surface roughness (Ra) of 0.2 μm or more; and (d).
(C) applying an organic material containing a hydrophilic group and a hydrophobic group to the trapezoidal side surface of the conductor wiring layer after the roughening treatment;
(E) a step of removing the resist on the upper surface of the conductor wiring layer; and (f) a through hole is formed in at least a B-stage-shaped insulating layer containing a thermosetting resin, and a conductor paste containing a metal powder is filled. Forming a via conductor with
(G) After the conductor wiring layer on the surface of the resin film prepared in (a) to (e) is laminated and pressed on the via conductor forming portion on the surface of the insulating layer prepared in (f), the resin film is peeled off and the conductor wiring layer is removed. (A) a step of forming a wiring layer in which a conductor wiring layer is embedded on the surface of the insulating layer, and (h) laminating a plurality of wiring layers prepared in (a) to (g), and curing at once while applying pressure And a step of performing In order to enhance the adhesion, it is preferable that the cross section of the conductor wiring layer formed on the surface of the resin film is a trapezoid having a formation angle (θ) of 45 ° to 80 °.

【0014】本発明の多層配線基板によれば、導体配線
層が絶縁層の表面と同一平面となるように埋設されてい
るために、多層配線基板の表面の平滑性に優れる。ま
た、本発明の多層配線基板は、埋設された導体配線層側
面が表面粗さ(Ra)0.2μm以上に粗化されてお
り、且つ絶縁層との界面に親水基と疎水基を有する有機
物が存在するため、有機樹脂を含む絶縁層と金属箔界面
との密着力が強く、また絶縁層と導体配線層との隙間か
らの水分などの浸入がなく、バイア導体の抵抗の劣化が
少ない。また、導体配線層のピール強度も高めることが
でき、基板の落下などに対しても部品欠落のない高信頼
性の多層配線基板を得ることができる。
According to the multilayer wiring board of the present invention, since the conductor wiring layer is embedded so as to be flush with the surface of the insulating layer, the surface of the multilayer wiring board is excellent in smoothness. Further, in the multilayer wiring board of the present invention, the side surface of the buried conductor wiring layer is roughened to have a surface roughness (Ra) of 0.2 μm or more, and an organic substance having a hydrophilic group and a hydrophobic group at the interface with the insulating layer. , The adhesive strength between the insulating layer containing the organic resin and the metal foil interface is strong, there is no intrusion of moisture or the like from the gap between the insulating layer and the conductor wiring layer, and the deterioration of the resistance of the via conductor is small. In addition, the peel strength of the conductor wiring layer can be increased, and a highly reliable multilayer wiring board free from parts loss even when the board falls can be obtained.

【0015】また、本発明の製造方法によれば、上記の
多層配線層における導体配線層間を接続するためのバイ
ア導体をレーザー照射によって形成するために、感光性
樹脂を使用する必要がなく、絶縁層材料としてガラス転
移点が高く、吸水率の小さいなどの材料特性に優れた任
意の有機樹脂の絶縁材料を選定できる。また、導体配線
層の絶縁層との界面側に親水基と疎水基を有する有機物
を塗布することによって有機樹脂を含む絶縁層と金属箔
界面との密着力を高めることができる。しかも、絶縁層
の形成と、導体配線層との形成を同時に平行して行うこ
とができために製造工程の簡略化と短縮化を図ることが
できる。
Further, according to the manufacturing method of the present invention, since the via conductor for connecting the conductor wiring layers in the above-mentioned multilayer wiring layer is formed by laser irradiation, it is not necessary to use a photosensitive resin, and it is not necessary to use a photosensitive resin. As the layer material, any organic resin insulating material excellent in material properties such as a high glass transition point and a small water absorption can be selected. Further, by applying an organic substance having a hydrophilic group and a hydrophobic group to the interface side of the conductor wiring layer with the insulating layer, the adhesion between the insulating layer containing the organic resin and the metal foil interface can be increased. In addition, since the formation of the insulating layer and the formation of the conductor wiring layer can be performed simultaneously in parallel, the manufacturing process can be simplified and shortened.

【0016】[0016]

【発明の実施の形態】本発明の多層配線基板を製造方法
とあわせて図面をもとに説明する。図1は、本発明にお
ける多層配線基板を説明するための概略図である。ま
た、図2は本発明における多層配線基板の製造方法の一
例を説明するための工程図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer wiring board according to the present invention will be described with reference to the drawings together with a manufacturing method. FIG. 1 is a schematic diagram for explaining a multilayer wiring board according to the present invention. FIG. 2 is a process chart for explaining an example of a method for manufacturing a multilayer wiring board according to the present invention.

【0017】図2の(a)に示すように樹脂フィルム1
2の表面に接着剤を介して金属箔11を接着する。この
時、金属箔11はこの後の配線の形成のしやすさ、電気
抵抗等を考慮すると銅箔を用いるのが望ましい。そし
て、金属箔11表面にさらにフォトレジスト13を貼付
する(b)。そして、フォトレジスト13を露光、現像
することにより、導体配線部分にフォトレジスト14を
残す(c)。フォトレジスト14はネガ型を用いる方
が、その後の導体配線層15を粗化するときに処理が行
いやすい。その後、金属箔11をエッチングすることに
より導体配線層15を形成する(d)。この時、樹脂フ
ィルム12表面に形成した導体配線層15の断面は台形
型に形成することが重要であって、台形の形成角は
(θ)は45°〜80°でこと、望ましくは50°〜7
5°が良い。これは、台形の形成角が45°以上とする
ことによって、多層配線基板を作製した時に導体配線層
15のピール強度を高くすることができ、45°よりも
小さいと導体配線層のピール強度が低くなるためであ
る。また、台形の形成角が80°より大きいと導体配線
層15側面の長さが短くなるため、絶縁層との界面に水
分が浸入してバイア導体18への到達が早く、バイア導
体18の酸化によって抵抗上昇も速くなるためである。
As shown in FIG. 2A, the resin film 1
The metal foil 11 is adhered to the surface of 2 via an adhesive. At this time, it is desirable to use a copper foil as the metal foil 11 in consideration of the ease of forming the wiring thereafter, electric resistance, and the like. Then, a photoresist 13 is further attached to the surface of the metal foil 11 (b). Then, the photoresist 13 is exposed and developed to leave the photoresist 14 on the conductor wiring portion (c). When the photoresist 14 is of a negative type, the processing is easier to perform when the subsequent conductor wiring layer 15 is roughened. Thereafter, the conductor wiring layer 15 is formed by etching the metal foil 11 (d). At this time, it is important that the cross section of the conductive wiring layer 15 formed on the surface of the resin film 12 is formed in a trapezoidal shape, and the angle of formation of the trapezoid is (θ) of 45 ° to 80 °, preferably 50 °. ~ 7
5 ° is good. This is because the peel strength of the conductive wiring layer 15 can be increased when the multilayer wiring board is manufactured by setting the trapezoidal formation angle to 45 ° or more, and when the trapezoid is smaller than 45 °, the peel strength of the conductive wiring layer is reduced. It is because it becomes low. If the angle of formation of the trapezoid is larger than 80 °, the length of the side surface of the conductor wiring layer 15 becomes short, so that moisture penetrates into the interface with the insulating layer and reaches the via conductor 18 quickly. This is because resistance increases faster.

【0018】導体配線層15の断面の台形の形成角
(θ)を45°〜80°にするには金属箔11の種類に
よっても若干異なるが2〜50μm/minでエッチン
グするのが良い。
In order to set the trapezoidal formation angle (θ) of the cross section of the conductor wiring layer 15 to 45 ° to 80 °, it is preferable to perform etching at 2 to 50 μm / min, although it varies slightly depending on the type of the metal foil 11.

【0019】次に、導体配線層15側面を表面粗さ(R
a)を0.2μm以上に粗化する。金属の種類によって
も異なるが、蟻酸、NaClO2、NaOH、Na2PO
4あるいはこれらの混合液等の酸性溶液を吹き付けた
り、ディッピングするのが良く、特に蟻酸を吹き付ける
のが表面粗さを細かく制御できる点で望ましい。導体配
線層15側面の表面粗さ(Ra)が0.2μmよりも小
さいと、絶縁基板中の樹脂との密着力が低くなるため、
水分が侵入しやすくなり、また水分の侵入経路が短くな
るために、導体配線層15と接続されるバイア導体18
の抵抗が上昇したり、導体配線層15のピール強度が低
下する。
Next, the side surface of the conductor wiring layer 15 is made to have a surface roughness (R
a) is roughened to 0.2 μm or more. Depending on the type of metal, formic acid, NaClO 2 , NaOH, Na 2 PO
It is preferable to spray or dipping an acidic solution such as 4 or a mixture thereof, and it is particularly preferable to spray formic acid in that the surface roughness can be finely controlled. If the surface roughness (Ra) of the side surface of the conductor wiring layer 15 is smaller than 0.2 μm, the adhesion to the resin in the insulating substrate becomes low,
The via conductors 18 connected to the conductor wiring layer 15 are easily connected to the conductor wiring layer 15 because the water easily penetrates and the path for the water to penetrate becomes short.
And the peel strength of the conductor wiring layer 15 decreases.

【0020】次に、粗化した導体配線層15の少なくと
も側面に、親水基と疎水基を有する有機物を塗布する。
親水基と疎水基を有する有機物によれば、親水基として
は、シラノール基、カルボキシル基、水酸基の群から選
ばれる少なくとも1種が挙げられ、疎水基としては、ビ
ニル基、エポキシ基、メタクリル基、アミノ基およびメ
ルカプト基の群から選ばれる少なくとも1種が挙げられ
る。
Next, an organic material having a hydrophilic group and a hydrophobic group is applied to at least the side surfaces of the roughened conductor wiring layer 15.
According to the organic substance having a hydrophilic group and a hydrophobic group, the hydrophilic group includes at least one selected from the group consisting of a silanol group, a carboxyl group, and a hydroxyl group, and the hydrophobic group includes a vinyl group, an epoxy group, a methacryl group, At least one selected from the group consisting of an amino group and a mercapto group is exemplified.

【0021】このような親水基と疎水基を有する有機物
としては、親水基と疎水基を有するシラン系化合物が好
適であって、特にN−フェニル−γ−アミノプロピルト
リメトキシシラン、γ−グリシドキシプロピルトリメト
キシシラン、N−β(アミノエチル)γ−アミノプロピ
ルトリメトキシシランの群から選ばれる少なくとも1種
のシランカップリング剤が好適に使用できる。
As such an organic substance having a hydrophilic group and a hydrophobic group, a silane compound having a hydrophilic group and a hydrophobic group is preferable. In particular, N-phenyl-γ-aminopropyltrimethoxysilane, γ-glycide At least one silane coupling agent selected from the group consisting of xylpropyltrimethoxysilane and N-β (aminoethyl) γ-aminopropyltrimethoxysilane can be suitably used.

【0022】また、親水基と疎水基を有する有機物は、
250℃以上の沸点を有することが望ましい。これは、
沸点が250℃よりも低いと、半田耐熱試験等で導体配
線層15と絶縁層の界面に膨れが生じて導体配線層15
と絶縁層との密着不良やバイア導体18の抵抗の増加を
引き起こすおそれがあるためである。
The organic substance having a hydrophilic group and a hydrophobic group is
It is desirable to have a boiling point of 250 ° C. or higher. this is,
If the boiling point is lower than 250 ° C., swelling occurs at the interface between the conductor wiring layer 15 and the insulating layer in a soldering heat test or the like, and the conductor wiring layer 15
This is because there is a risk of causing poor adhesion between the via conductor 18 and the insulating layer and an increase in the resistance of the via conductor 18.

【0023】導体配線層15側面の粗化後の親水基と疎
水基を有する有機物を塗布した後にレジスト14を除去
する(e)。この有機物の塗布がレジスト除去後に行う
ことも可能であるが、導体配線層15の上下面は、バイ
ア導体18と金属−金属の接続をしているため、導体配
線層15の上面には、親水基と疎水基を有する有機物は
塗布しない方が、バイア導体18との接触抵抗が低くで
きるので良い。
After applying an organic material having a hydrophilic group and a hydrophobic group after roughening the side surface of the conductor wiring layer 15, the resist 14 is removed (e). The application of the organic substance may be performed after the resist is removed. However, since the upper and lower surfaces of the conductor wiring layer 15 are connected to the metal-metal connection with the via conductor 18, the upper surface of the conductor wiring layer 15 has a hydrophilic surface. It is better not to apply an organic substance having a group and a hydrophobic group, because the contact resistance with the via conductor 18 can be reduced.

【0024】一方、図2(f)に示すように、まず絶縁
シート16を準備する。この絶縁シート16は、未硬化
または半硬化の熱硬化性樹脂を含み、例えば熱硬化性樹
脂と無機フィラーからなるものである。絶縁シート16
を構成する熱硬化性樹脂は、吸水率が0.5%以下のも
のが良く、望ましくは0.3%以下が良い。熱硬化性樹
脂の吸水率が0.5%より高いと水分の影響を受けてバ
イア導体18の抵抗が上昇する。具体的には、A−PP
E(アリル化ポリフェニレンエーテル)、BTレジン
(ビスマレイミドトリアジン)、ポリイミド樹脂、ポリ
アミドビスマレイミド等の樹脂が望ましい。また、絶縁
シート16の無機フィラーは、SiO2、Al23、A
lN等が好適であり、平均粒径が20μm以下、特に1
0μm以下、最適には7μm以下の略球形状の粉末が用
いられる。また、多層配線基板の強度を持たせるために
は繊維質の織布や不織布を含有することが望ましく、多
層構造において少なくとも1層は繊維質のフィラーを含
む絶縁シートを用いるのが良い。これらの無機質フィラ
ーは、有機樹脂:無機質フィラーの体積比率で15:8
5〜95:5の比率範囲で混合される。
On the other hand, as shown in FIG. 2F, first, an insulating sheet 16 is prepared. The insulating sheet 16 contains an uncured or semi-cured thermosetting resin, and is made of, for example, a thermosetting resin and an inorganic filler. Insulation sheet 16
The thermosetting resin constituting (1) preferably has a water absorption of 0.5% or less, more preferably 0.3% or less. If the water absorption of the thermosetting resin is higher than 0.5%, the resistance of the via conductor 18 increases due to the influence of moisture. Specifically, A-PP
Resins such as E (allylated polyphenylene ether), BT resin (bismaleimide triazine), polyimide resin, and polyamide bismaleimide are desirable. The inorganic filler of the insulating sheet 16 is SiO 2 , Al 2 O 3 , A
1N or the like is preferable, and the average particle size is 20 μm or less, particularly 1 μm.
Substantially spherical powder of 0 μm or less, optimally 7 μm or less is used. Further, in order to impart the strength of the multilayer wiring board, it is desirable to contain a fibrous woven fabric or a nonwoven fabric. In a multilayer structure, it is preferable to use an insulating sheet containing at least one layer containing a fibrous filler. These inorganic fillers have an organic resin: inorganic filler volume ratio of 15: 8.
It is mixed in a ratio range of 5 to 95: 5.

【0025】次に、レーザー光を照射して絶縁シート1
6のバイアホール17加工を行う。バイアホール17の
加工はCO2、YAGレーザー等が使用できる。その
後、金、銀、銅、アルミニウム等から選ばれる少なくと
も1種を含む金属粉末にバインダーを添加し、導電性ペ
ーストを作製する。そして、バイアホール17に導電性
ペーストを充填し、バイア導体18を形成する。導電性
ペースト中のバインダーは不揮発で絶縁層中の熱硬化性
樹脂と反応するものを用いるのが望ましい。また、導電
性ペーストの充填方法として常圧の印刷機等も使用でき
るが、真空印刷機を用いる方がより充填率を上げること
ができる。
Next, the insulating sheet 1 is irradiated with a laser beam.
The via hole 17 of No. 6 is processed. The processing of the via hole 17 can use CO 2 , YAG laser or the like. Thereafter, a binder is added to a metal powder containing at least one selected from gold, silver, copper, aluminum, and the like, to produce a conductive paste. Then, the via hole 17 is filled with a conductive paste to form the via conductor 18. It is desirable to use a binder that is non-volatile and reacts with the thermosetting resin in the insulating layer as the binder in the conductive paste. A normal pressure printing machine or the like can also be used as a method for filling the conductive paste, but using a vacuum printing machine can further increase the filling rate.

【0026】その後、樹脂フィルム12上に作製した鏡
像の導体配線層15をバイア導体18を形成した絶縁シ
ート16に熱圧着により転写する。そして、この鏡像の
導体配線層15のパターンを有する樹脂フィルム12を
Bステージ状の絶縁シート16の表面に積層して3kg
/cm2以上の圧力を印加した後、樹脂フィルム12を
剥離する(図1(i))ことにより、絶縁層の表面に導
体配線層15を転写するとともに、導体配線層15を絶
縁層の表面に埋設し、配線シート19を得ることができ
る。
Thereafter, the mirror-image conductor wiring layer 15 formed on the resin film 12 is transferred to the insulating sheet 16 on which the via conductor 18 is formed by thermocompression bonding. Then, the resin film 12 having the pattern of the conductor wiring layer 15 of the mirror image is laminated on the surface of the B-stage-shaped insulating sheet 16 and 3 kg
After applying a pressure of at least / cm 2 , the resin film 12 is peeled off (FIG. 1 (i)), whereby the conductor wiring layer 15 is transferred to the surface of the insulating layer and the conductor wiring layer 15 is transferred to the surface of the insulating layer. And the wiring sheet 19 can be obtained.

【0027】次に、上記(a)〜(j)と同様な方法に
よって作成された複数の配線シート19−1〜19−5
を複数枚位置を合せて重ねて、一括硬化することにより
図1に示すような絶縁層1、導体配線層2、バイア導体
3を具備し、導体配線層2が絶縁層1の表面に埋設され
た表面平坦性に優れた多層配線基板を作製することがで
きる。
Next, a plurality of wiring sheets 19-1 to 19-5 prepared by a method similar to the above (a) to (j).
A plurality of are aligned with each other, and are cured together to provide an insulating layer 1, a conductive wiring layer 2, and a via conductor 3 as shown in FIG. 1, and the conductive wiring layer 2 is embedded in the surface of the insulating layer 1. Thus, a multilayer wiring board having excellent surface flatness can be manufactured.

【0028】また、本発明の多層配線基板によれば、図
1(b)に示すように、バイア導体3と接続する導体配
線層2において、その導体配線層2の断面が、形成角
(θ)が45°〜80°の逆台形型からなるもので、か
かる形状に導体配線層2の絶縁層1への埋設性を高める
ことができるとともに、導体配線層2の絶縁層1への密
着性を高めることができる。
Further, according to the multilayer wiring board of the present invention, as shown in FIG. 1B, in the conductive wiring layer 2 connected to the via conductor 3, the cross section of the conductive wiring layer 2 has a formation angle (θ ) Is an inverted trapezoidal shape of 45 ° to 80 °, so that the embedding property of the conductor wiring layer 2 in the insulating layer 1 can be improved in such a shape, and the adhesion of the conductor wiring layer 2 to the insulating layer 1 can be improved. Can be increased.

【0029】また、導体配線層2の逆台形型における側
面の表面粗さ(Ra)が0.2μm以上であることによ
って導体配線層2の絶縁層1との接触面積が大きくなる
結果、絶縁層1の表面における導体配線層2と絶縁層1
との界面部分から水分が浸入した場合に、バイア導体3
までに到達するまでの距離が長くなる。
When the surface roughness (Ra) of the side surface of the conductive wiring layer 2 in the inverted trapezoidal shape is 0.2 μm or more, the contact area of the conductive wiring layer 2 with the insulating layer 1 is increased. Conductor wiring layer 2 and insulating layer 1 on the surface of
When moisture invades from the interface with the via conductor, the via conductor 3
The distance to reach is longer.

【0030】さらに、この導体配線層2と絶縁層1との
界面に、親水基および疎水基を有する有機物を存在せし
めることによって水分のバイア導体3への侵入を阻止す
ることができる。
Further, by allowing an organic substance having a hydrophilic group and a hydrophobic group to be present at the interface between the conductor wiring layer 2 and the insulating layer 1, it is possible to prevent moisture from entering the via conductor 3.

【0031】その結果、従来より発生していた導体配線
層2と絶縁層1との界面を経由した水分の侵入を防止で
きるために、高湿度環境下においてもバイア導体の抵抗
変化がなく、またフリップチップ実装にも適用可能な高
信頼性の多層配線基板を得ることができる。
As a result, since the intrusion of moisture through the interface between the conductor wiring layer 2 and the insulating layer 1 which has conventionally occurred can be prevented, the resistance of the via conductor does not change even in a high humidity environment. A highly reliable multilayer wiring board applicable to flip-chip mounting can be obtained.

【0032】また、製造方法においては、各層において
導体配線層の加工、絶縁層の加工を並列に行うことがで
きるため、また、多層化した絶縁樹脂を一括で硬化でき
るため、短いサイクルタイムで多層配線基板を作製する
ことができる。
Further, in the manufacturing method, the processing of the conductor wiring layer and the processing of the insulating layer can be performed in parallel on each layer, and the multilayered insulating resin can be cured at a time. A wiring substrate can be manufactured.

【0033】[0033]

【実施例】(多層配線基板の作製)絶縁層として以下の
2種類を用意した。ガラス布にアリル化ポリフェニレン
エーテル樹脂(A−PPE樹脂)系とBTレジン系のプ
リプレグを作製した。また、比較例としてエポキシ樹脂
系のプリプレグを作製した。
EXAMPLES (Production of multilayer wiring board) The following two types of insulating layers were prepared. An allylated polyphenylene ether resin (A-PPE resin) -based and BT resin-based prepreg were prepared on a glass cloth. As a comparative example, an epoxy resin prepreg was prepared.

【0034】また、A−PPE樹脂とBTレジンを用
い、さらに無機フィラーとして球状シリカを用い、これ
らをA−PPE樹脂またはBTレジン:無機フィラーが
体積比で50:50となる組成物を用い、これをドクタ
ーブレード法によって厚さ40μmのBステージ状態の
絶縁層を作製した。
Further, an A-PPE resin and a BT resin are used, spherical silica is used as an inorganic filler, and a composition in which the volume ratio of the A-PPE resin or the BT resin: the inorganic filler is 50:50 is used. This was formed into an insulating layer in a B-stage state with a thickness of 40 μm by a doctor blade method.

【0035】また、比較例として、エポキシ樹脂を用
い、さらに無機フィラーとして球状シリカを用い、これ
らをエポキシ樹脂:無機フィラーが体積比で50:50
となる組成を用い、上記と同じくドクターブレード法に
よって厚さ40μmのBステージ状態の絶縁層を作製し
た。
As a comparative example, an epoxy resin was used, and spherical silica was further used as an inorganic filler.
Using the composition shown below, an insulating layer in the B-stage state having a thickness of 40 μm was formed by the doctor blade method as described above.

【0036】この2種類の絶縁層にCO2レーザーで貫
通孔を形成し、次いで銅の表面を銀でコーティングした
粉末とバインダーを混合し、導電性ペーストを貫通孔に
充填してバイア導体を形成した。
Through holes are formed in these two types of insulating layers with a CO 2 laser, and then a powder obtained by coating a copper surface with silver and a binder are mixed, and a conductive paste is filled in the through holes to form via conductors. did.

【0037】一方、38μmのPETフィルムに12μ
mの厚さの電解銅箔を貼り合わせて転写用の銅箔付きフ
ィルムを準備した。銅箔表面にドライフィルムレジスト
を貼付し、露光、炭酸ナトリウムによる現像、塩化第二
鉄によるエッチングを行い台形の形成角45°〜80°
の形成角を持つ配線を形成した。
On the other hand, 12 μm is applied to a 38 μm PET film.
An electrolytic copper foil having a thickness of m was attached to prepare a film with a copper foil for transfer. A dry film resist is stuck on the copper foil surface, exposed, developed with sodium carbonate, and etched with ferric chloride to form a trapezoidal formation angle of 45 ° to 80 °.
The wiring having the formation angle of was formed.

【0038】この後、10%の蟻酸により導体配線層側
面を0.1〜0.8μmに粗化した後、適宜、N−フェ
ニル−γ−アミノプロピルトリメトキシシラン、または
N−β(アミノエチル)γ−アミノプロピルトリメトキ
シシランを塗布した。その後、水酸化ナトリウムによる
レジストの剥離を行い、PETフィルム上に配線パター
ンを形成した。
Thereafter, the side surface of the conductor wiring layer is roughened to 0.1 to 0.8 μm with 10% formic acid, and then N-phenyl-γ-aminopropyltrimethoxysilane or N-β (aminoethyl ) Γ-Aminopropyltrimethoxysilane was applied. Thereafter, the resist was stripped off with sodium hydroxide to form a wiring pattern on the PET film.

【0039】その後、PETフィルム上に形成したパタ
ーンを130℃、20kg/cm2で上記2種類の絶縁
層に転写し、配線シートを作製した。
Thereafter, the pattern formed on the PET film was transferred to the above two kinds of insulating layers at 130 ° C. and 20 kg / cm 2 to prepare a wiring sheet.

【0040】ガラス布を含有する絶縁層から作製した配
線シートを4層重ね合わせて導体配線層5層の多層配線
基板を作製した。また、ガラス布から作製した絶縁層の
上下にシリカフィラーを含有する絶縁層を各2層重ね合
わせて導体配線層9層の多層配線基板も同時に作製し
た。その後、200℃、20kg/cm2ですべての絶
縁層を一括で硬化した。
Four wiring sheets made of an insulating layer containing a glass cloth were superposed on each other to produce a multilayer wiring board having five conductive wiring layers. In addition, two insulating layers each containing a silica filler were superposed on and under the insulating layer made of a glass cloth, and a multilayer wiring board having nine conductive wiring layers was simultaneously manufactured. Thereafter, all the insulating layers were simultaneously cured at 200 ° C. and 20 kg / cm 2 .

【0041】(評価)作製した多層配線基板において、
導体配線層側面の表面粗さ(Ra)は粗化処理後に原子
間力顕微鏡(AFM)により測定した。また、台形型の
導体配線の形成角は断面をSEM観察することにより測
定した。また、樹脂の吸水率は、50mm×50mm、
厚さ1mmの硬化したシートを50℃、24時間乾燥
し、その後、23℃の水中に浸し、その重量差により求
めた。
(Evaluation) In the manufactured multilayer wiring board,
The surface roughness (Ra) of the side surface of the conductor wiring layer was measured by an atomic force microscope (AFM) after the roughening treatment. Further, the formation angle of the trapezoidal conductor wiring was measured by observing the cross section by SEM. The water absorption of the resin is 50 mm x 50 mm,
The cured sheet having a thickness of 1 mm was dried at 50 ° C. for 24 hours, then immersed in water at 23 ° C., and determined by the weight difference.

【0042】作製した多層配線基板は、150℃、10
00時間の高温放置試験、130℃、85%RH、2.
3atm、200時間のプレッシャーPCTクッカー試
験を行った。
The prepared multilayer wiring board was heated at 150.degree.
1. High temperature storage test for 00 hours, 130 ° C., 85% RH,
A pressure PCT cooker test was performed at 3 atm for 200 hours.

【0043】上記試験の前後で800個のバイア導体を
導体配線層で直列に接続したデイジーチェーンの抵抗変
化が10%以内のものを良品、10%を越えるものを不
良品としてN数20個の基板について試験した。
A daisy chain in which 800 via conductors are connected in series by a conductor wiring layer before and after the above test has a resistance change of 10% or less as a good product, and a daisy chain having a resistance change of more than 10% as a defective product. The substrate was tested.

【0044】[0044]

【表1】 [Table 1]

【0045】表1に示すように、断面が形成角45°〜
80°の逆台形型の導体配線層側面の表面粗さ(Ra)
を0.2μm以上とし、絶縁層との界面に親水基と疎水
基を有する有機物を存在させることにより、高温放置試
験やPCT試験においても抵抗上昇のない多層配線基板
を作製することができた。また、本発明の多層配線基板
は絶縁層の加工と導体配線層の加工を並列して行うこと
ができ、絶縁層の熱硬化性樹脂を一括で硬化できるため
サイクルタイムを大幅に短縮することができた。
As shown in Table 1, the cross section has a formation angle of 45 ° or more.
Surface roughness (Ra) of 80 ° inverted trapezoidal type conductor wiring layer side surface
Was set to 0.2 μm or more, and an organic substance having a hydrophilic group and a hydrophobic group was present at the interface with the insulating layer, whereby a multilayer wiring board having no increase in resistance even in a high-temperature storage test or a PCT test could be manufactured. In addition, the multilayer wiring board of the present invention can perform the processing of the insulating layer and the processing of the conductor wiring layer in parallel, and can simultaneously cure the thermosetting resin of the insulating layer, thereby greatly reducing the cycle time. did it.

【0046】[0046]

【発明の効果】以上詳述したように、本発明によれば、
高湿度環境下においても水分侵入によるバイア導体の酸
化とともに抵抗増大を防止することができ、導体配線層
の信頼性向上を達成することができ、また、半導体素子
のフリップチップ実装に適した多層配線基板を得ること
ができる。また、本発明の製造方法によれば、従来のビ
ルドアップ法などに比較して絶縁層の加工と導体配線層
の加工を並列して行え、絶縁層の樹脂を一括で硬化でき
るためサイクルタイムを大幅に短縮することができる。
As described in detail above, according to the present invention,
Even in a high humidity environment, the resistance of the via conductors can be prevented from increasing due to the oxidation of the via conductors due to the intrusion of moisture, the reliability of the conductor wiring layer can be improved, and multilayer wiring suitable for flip-chip mounting of semiconductor elements A substrate can be obtained. In addition, according to the manufacturing method of the present invention, the processing of the insulating layer and the processing of the conductor wiring layer can be performed in parallel compared with the conventional build-up method and the like, and the resin of the insulating layer can be cured at a time, so that the cycle time is reduced. It can be greatly reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層配線基板を説明するための(a)
概略断面図と、(b)要部拡大断面図である。
FIG. 1A illustrates a multilayer wiring board according to the present invention.
It is a schematic sectional view, and (b) a principal part enlarged sectional view.

【図2】本発明の多層配線基板の製造方法の一例を説明
するための工程図である。
FIG. 2 is a process diagram illustrating an example of a method for manufacturing a multilayer wiring board according to the present invention.

【符号の説明】[Explanation of symbols]

1 絶縁層 2 導体配線層 3 バイア導体 11 金属箔 12 樹脂フィルム 13,14 レジスト 15 導体配線層 16 絶縁シート 17 バイアホール 18 バイア導体 19 配線シート 19−1〜19−5 配線シート REFERENCE SIGNS LIST 1 insulating layer 2 conductor wiring layer 3 via conductor 11 metal foil 12 resin film 13, 14 resist 15 conductor wiring layer 16 insulating sheet 17 via hole 18 via conductor 19 wiring sheet 19-1 to 19-5 wiring sheet

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】少なくとも熱硬化性樹脂を含む絶縁層と、
該絶縁層表面に埋設された導体配線層と、導体配線層間
を接続するために貫通孔に金属粉末を含む導体成分を充
填されたバイア導体とを具備する多層配線基板におい
て、前記バイア導体と接続された導体配線層の断面が形
成角(θ)が45°〜80°の逆台形型であるととも
に、該逆台形形状の側面の表面粗さ(Ra)が0.2μ
m以上であり、かつ側面の絶縁層との接触界面に親水基
と疎水基を有する有機物が存在することを特徴とする多
層配線基板。
An insulating layer containing at least a thermosetting resin,
A multilayer wiring board comprising: a conductor wiring layer buried on the surface of the insulating layer; and a via conductor filled with a conductor component containing a metal powder in a through hole for connecting the conductor wiring layers. The cross section of the formed conductor wiring layer has an inverted trapezoidal shape having a formation angle (θ) of 45 ° to 80 °, and the side roughness (Ra) of the side surface of the inverted trapezoidal shape is 0.2 μ
m or more, and an organic substance having a hydrophilic group and a hydrophobic group is present at a contact interface with a side insulating layer.
【請求項2】前記絶縁層の熱硬化性樹脂の吸水率が0.
5%以下であることを特徴とする請求項1記載の多層配
線基板。
2. The thermosetting resin of the insulating layer has a water absorption of 0.1.
2. The multilayer wiring board according to claim 1, wherein the content is 5% or less.
【請求項3】前記導体配線層が金属箔を加工したもので
あることを特徴とする請求項1または請求項2記載の多
層配線基板。
3. The multilayer wiring board according to claim 1, wherein the conductive wiring layer is formed by processing a metal foil.
【請求項4】前記疎水基および親水基を有する化合物が
シラン系化合物からなる請求項1乃至請求項3のいずれ
か記載の多層配線基板。
4. The multilayer wiring board according to claim 1, wherein the compound having a hydrophobic group and a hydrophilic group comprises a silane-based compound.
【請求項5】(a)金属箔を接着剤を介して樹脂フィル
ムに接着させる工程と、(b)(a)によって作製され
た前記樹脂フィルムの金属箔表面に、鏡像の配線パター
ン状にレジストを塗布後、非レジスト部をエッチングに
よって除去して、断面が、形成角45°〜80°の台形
型の導体配線層を形成する工程と、(c)(b)によっ
て形成された前記導体配線層の台形型の側面を表面粗さ
(Ra)を0.2μm以上に粗化する工程と、(d)
(c)の粗化処理後の前記導体配線層の台形型の側面
に、親水基と疎水基を含む有機物を塗布する工程と、
(e)前記導体配線層上面のレジストを除去する工程
と、(f)少なくとも熱硬化性樹脂を含有するBステー
ジ状の絶縁層に、貫通孔を形成し、金属粉末を含む導体
ペーストを充填してバイア導体を形成する工程と、
(g)(a)〜(e)で作製した樹脂フィルム表面の導
体配線層を(f)で作製した絶縁層表面のバイア導体形
成箇所に積層加圧した後、樹脂フィルムを剥がして導体
配線層を転写し、絶縁層表面に導体配線層を埋設した配
線層を形成する工程と、(h)(a)〜(g)で作製し
た複数の配線層を積層し、圧力をかけながら一括で硬化
する工程と、を含むことを特徴とする多層配線基板の製
造方法。
5. A step of (a) adhering a metal foil to a resin film via an adhesive, and (b) a resist in a mirror image wiring pattern on the surface of the metal foil of the resin film produced in (a). Forming a trapezoidal conductor wiring layer having a cross-section angle of 45 ° to 80 ° by removing the non-resist portion by etching, and (c) forming the conductor wiring layer formed by (b). Roughening the trapezoidal side surface of the layer to a surface roughness (Ra) of 0.2 μm or more; (d)
(C) applying an organic material containing a hydrophilic group and a hydrophobic group to the trapezoidal side surface of the conductor wiring layer after the roughening treatment;
(E) a step of removing the resist on the upper surface of the conductor wiring layer; and (f) a through hole is formed in at least a B-stage-shaped insulating layer containing a thermosetting resin, and a conductor paste containing a metal powder is filled. Forming a via conductor with
(G) After the conductor wiring layer on the surface of the resin film prepared in (a) to (e) is laminated and pressed on the via conductor forming portion on the surface of the insulating layer prepared in (f), the resin film is peeled off and the conductor wiring layer is removed. (A) a step of forming a wiring layer in which a conductor wiring layer is embedded on the surface of the insulating layer, and (h) laminating a plurality of wiring layers prepared in (a) to (g), and curing at once while applying pressure A method of manufacturing a multilayer wiring board.
【請求項6】前記熱硬化性樹脂の吸水率が0.5%以下
であることを特徴とする請求項5記載の多層配線基板の
製造方法。
6. The method according to claim 5, wherein the thermosetting resin has a water absorption of 0.5% or less.
【請求項7】前記疎水基および親水基を有する化合物
が、シラン系化合物からなる請求項5または請求項6記
載の多層配線基板の製造方法。
7. The method according to claim 5, wherein the compound having a hydrophobic group and a hydrophilic group comprises a silane compound.
JP2001050978A 2001-02-26 2001-02-26 Multilayer wiring board and manufacturing method thereof Expired - Fee Related JP3631682B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001050978A JP3631682B2 (en) 2001-02-26 2001-02-26 Multilayer wiring board and manufacturing method thereof
US10/083,691 US6623844B2 (en) 2001-02-26 2002-02-25 Multi-layer wiring board and method of producing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001050978A JP3631682B2 (en) 2001-02-26 2001-02-26 Multilayer wiring board and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2002252459A true JP2002252459A (en) 2002-09-06
JP3631682B2 JP3631682B2 (en) 2005-03-23

Family

ID=18911850

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
JP (1) JP3631682B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007273632A (en) * 2006-03-30 2007-10-18 Kyocera Corp Woven cloth for wiring board, and prepreg
JP2014086679A (en) * 2012-10-26 2014-05-12 Kyocera Corp Thin film wiring board, multilayer wiring board and substrate for probe card
US9040832B2 (en) 2011-03-29 2015-05-26 Shinko Electric Industries Co., Ltd. Wiring substrate and method of manufacturing the same
US9232644B2 (en) 2012-09-27 2016-01-05 Shinko Electric Industries Co., Ltd. Wiring substrate
CN112165773A (en) * 2020-10-07 2021-01-01 广州添利电子科技有限公司 Process for manufacturing pattern in circuit burying mode
CN113784510A (en) * 2021-08-02 2021-12-10 景旺电子科技(珠海)有限公司 Method for selectively plugging hole and circuit board

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007273632A (en) * 2006-03-30 2007-10-18 Kyocera Corp Woven cloth for wiring board, and prepreg
US9040832B2 (en) 2011-03-29 2015-05-26 Shinko Electric Industries Co., Ltd. Wiring substrate and method of manufacturing the same
US9232644B2 (en) 2012-09-27 2016-01-05 Shinko Electric Industries Co., Ltd. Wiring substrate
JP2014086679A (en) * 2012-10-26 2014-05-12 Kyocera Corp Thin film wiring board, multilayer wiring board and substrate for probe card
CN112165773A (en) * 2020-10-07 2021-01-01 广州添利电子科技有限公司 Process for manufacturing pattern in circuit burying mode
CN112165773B (en) * 2020-10-07 2022-10-11 广州添利电子科技有限公司 Process for manufacturing graph in circuit burying mode
CN113784510A (en) * 2021-08-02 2021-12-10 景旺电子科技(珠海)有限公司 Method for selectively plugging hole and circuit board

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