JP4421592B2 - マルチプロセッサシステム、その制御方法、プログラム及び情報記憶媒体 - Google Patents

マルチプロセッサシステム、その制御方法、プログラム及び情報記憶媒体 Download PDF

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Publication number
JP4421592B2
JP4421592B2 JP2006304555A JP2006304555A JP4421592B2 JP 4421592 B2 JP4421592 B2 JP 4421592B2 JP 2006304555 A JP2006304555 A JP 2006304555A JP 2006304555 A JP2006304555 A JP 2006304555A JP 4421592 B2 JP4421592 B2 JP 4421592B2
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Japan
Prior art keywords
processor
bus
processors
communication
communication restriction
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JP2006304555A
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English (en)
Japanese (ja)
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JP2008123134A (ja
JP2008123134A5 (zh
Inventor
勉 堀川
保吉 大川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Interactive Entertainment Inc
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Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc filed Critical Sony Computer Entertainment Inc
Priority to JP2006304555A priority Critical patent/JP4421592B2/ja
Priority to EP07807867.2A priority patent/EP2085885B1/en
Priority to US12/444,747 priority patent/US8266476B2/en
Priority to CN2007800401077A priority patent/CN101529387B/zh
Priority to PCT/JP2007/068651 priority patent/WO2008056489A1/ja
Publication of JP2008123134A publication Critical patent/JP2008123134A/ja
Publication of JP2008123134A5 publication Critical patent/JP2008123134A5/ja
Application granted granted Critical
Publication of JP4421592B2 publication Critical patent/JP4421592B2/ja
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Bus Control (AREA)
JP2006304555A 2006-11-09 2006-11-09 マルチプロセッサシステム、その制御方法、プログラム及び情報記憶媒体 Active JP4421592B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2006304555A JP4421592B2 (ja) 2006-11-09 2006-11-09 マルチプロセッサシステム、その制御方法、プログラム及び情報記憶媒体
EP07807867.2A EP2085885B1 (en) 2006-11-09 2007-09-26 Multiprocessor system, its control method, and information recording medium
US12/444,747 US8266476B2 (en) 2006-11-09 2007-09-26 Multiprocessor system, its control method, and information recording medium
CN2007800401077A CN101529387B (zh) 2006-11-09 2007-09-26 多处理器系统、其控制方法和信息存储介质
PCT/JP2007/068651 WO2008056489A1 (fr) 2006-11-09 2007-09-26 Système à processeurs multiples, son procédé de commande et support d'enregistrement d'informations

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006304555A JP4421592B2 (ja) 2006-11-09 2006-11-09 マルチプロセッサシステム、その制御方法、プログラム及び情報記憶媒体

Publications (3)

Publication Number Publication Date
JP2008123134A JP2008123134A (ja) 2008-05-29
JP2008123134A5 JP2008123134A5 (zh) 2009-12-03
JP4421592B2 true JP4421592B2 (ja) 2010-02-24

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Family Applications (1)

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JP2006304555A Active JP4421592B2 (ja) 2006-11-09 2006-11-09 マルチプロセッサシステム、その制御方法、プログラム及び情報記憶媒体

Country Status (2)

Country Link
JP (1) JP4421592B2 (zh)
CN (1) CN101529387B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012252490A (ja) * 2011-06-02 2012-12-20 Renesas Electronics Corp マルチプロセッサおよびそれを用いた画像処理システム
US8824603B1 (en) * 2013-03-01 2014-09-02 Futurewei Technologies, Inc. Bi-directional ring-bus architecture for CORDIC-based matrix inversion
CN111639045B (zh) * 2020-06-03 2023-10-13 地平线(上海)人工智能技术有限公司 数据处理方法、装置、介质和设备

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3120033B2 (ja) * 1996-03-19 2000-12-25 株式会社東芝 分散メモリ型マルチプロセッサシステム及び故障回復方法
CN1258716C (zh) * 2003-11-26 2006-06-07 中国人民解放军国防科学技术大学 片内多处理器局部cache一致性的双环监听方法

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Publication number Publication date
JP2008123134A (ja) 2008-05-29
CN101529387A (zh) 2009-09-09
CN101529387B (zh) 2012-08-08

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