JP4414096B2 - 多重プロセッサ・コンピュータ・システム用の順序外れスヌーピング - Google Patents

多重プロセッサ・コンピュータ・システム用の順序外れスヌーピング Download PDF

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Publication number
JP4414096B2
JP4414096B2 JP2000564132A JP2000564132A JP4414096B2 JP 4414096 B2 JP4414096 B2 JP 4414096B2 JP 2000564132 A JP2000564132 A JP 2000564132A JP 2000564132 A JP2000564132 A JP 2000564132A JP 4414096 B2 JP4414096 B2 JP 4414096B2
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node
snoop
message
request
order
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JP2000564132A
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JP2002522827A (ja
JP2002522827A5 (enExample
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ネイガー，ギルバート・エイ
ウェイド，ニコラス・ディ
チェン，カイ
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Intel Corp
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
JP2000564132A 1998-08-06 1999-07-27 多重プロセッサ・コンピュータ・システム用の順序外れスヌーピング Expired - Fee Related JP4414096B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/130,302 US6112283A (en) 1998-08-06 1998-08-06 Out-of-order snooping for multiprocessor computer systems
US09/130,302 1998-08-06
PCT/US1999/017040 WO2000008564A1 (en) 1998-08-06 1999-07-27 Out-of-order snooping for multiprocessor computer systems

Publications (3)

Publication Number Publication Date
JP2002522827A JP2002522827A (ja) 2002-07-23
JP2002522827A5 JP2002522827A5 (enExample) 2006-08-31
JP4414096B2 true JP4414096B2 (ja) 2010-02-10

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ID=22444049

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Application Number Title Priority Date Filing Date
JP2000564132A Expired - Fee Related JP4414096B2 (ja) 1998-08-06 1999-07-27 多重プロセッサ・コンピュータ・システム用の順序外れスヌーピング

Country Status (6)

Country Link
US (1) US6112283A (enExample)
JP (1) JP4414096B2 (enExample)
AU (1) AU5133799A (enExample)
DE (1) DE19983443B4 (enExample)
GB (1) GB2357867B (enExample)
WO (1) WO2000008564A1 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6574219B1 (en) * 1998-08-06 2003-06-03 Intel Corp Passive message ordering on a decentralized ring
US6377582B1 (en) * 1998-08-06 2002-04-23 Intel Corporation Decentralized ring arbitration for multiprocessor computer systems
US6848003B1 (en) * 1999-11-09 2005-01-25 International Business Machines Corporation Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response
US6604162B1 (en) 2000-06-28 2003-08-05 Intel Corporation Snoop stall reduction on a microprocessor external bus
DE60221235T2 (de) 2001-02-24 2008-04-10 International Business Machines Corp. Datenerfassungstechnik für die schnelle zeichengabe
US20030115402A1 (en) * 2001-11-16 2003-06-19 Fredrik Dahlgren Multiprocessor system
JP2003271574A (ja) 2002-03-14 2003-09-26 Hitachi Ltd 共有メモリ型マルチプロセッサシステムにおけるデータ通信方法
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7069362B2 (en) * 2003-05-12 2006-06-27 International Business Machines Corporation Topology for shared memory computer system
US7644237B1 (en) * 2003-06-23 2010-01-05 Mips Technologies, Inc. Method and apparatus for global ordering to insure latency independent coherence
US7551564B2 (en) * 2004-05-28 2009-06-23 Intel Corporation Flow control method and apparatus for single packet arrival on a bidirectional ring interconnect
US7360008B2 (en) * 2004-12-30 2008-04-15 Intel Corporation Enforcing global ordering through a caching bridge in a multicore multiprocessor system
US7451231B2 (en) * 2005-02-10 2008-11-11 International Business Machines Corporation Data processing system, method and interconnect fabric for synchronized communication in a data processing system
US20060176890A1 (en) * 2005-02-10 2006-08-10 International Business Machines Corporation Data processing system, method and interconnect fabric for improved communication in a data processing system
US7707387B2 (en) * 2005-06-01 2010-04-27 Microsoft Corporation Conditional execution via content addressable memory and parallel computing execution model
US7451297B2 (en) 2005-06-01 2008-11-11 Microsoft Corporation Computing system and method that determines current configuration dependent on operand input from another configuration
US7793040B2 (en) 2005-06-01 2010-09-07 Microsoft Corporation Content addressable memory architecture
JP4912789B2 (ja) * 2006-08-18 2012-04-11 富士通株式会社 マルチプロセッサシステム，システムボードおよびキャッシュリプレース要求処理方法
JP4680851B2 (ja) * 2006-08-18 2011-05-11 富士通株式会社 システムコントローラ，同一アドレスリクエストキューイング防止方法および情報処理装置
CN101821717A (zh) 2007-10-18 2010-09-01 Nxp股份有限公司 采用高速缓存一致性负荷测试控制的电路和方法
WO2012077169A1 (ja) * 2010-12-06 2012-06-14 富士通株式会社 情報処理システムおよび情報送信方法
US8635411B2 (en) * 2011-07-18 2014-01-21 Arm Limited Data processing apparatus and method for managing coherency of cached data
JP6003607B2 (ja) * 2012-12-14 2016-10-05 富士通株式会社 サーバ装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5025365A (en) * 1988-11-14 1991-06-18 Unisys Corporation Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors
US5018063A (en) * 1988-12-05 1991-05-21 International Business Machines Corporation Method for reducing cross-interrogate delays in a multiprocessor system
US5715428A (en) * 1994-02-28 1998-02-03 Intel Corporation Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system
US5751986A (en) * 1994-03-01 1998-05-12 Intel Corporation Computer system with self-consistent ordering mechanism
US5682516A (en) * 1994-03-01 1997-10-28 Intel Corporation Computer system that maintains system wide cache coherency during deferred communication transactions
US5623628A (en) * 1994-03-02 1997-04-22 Intel Corporation Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
US5604450A (en) * 1995-07-27 1997-02-18 Intel Corporation High speed bidirectional signaling scheme
US5881303A (en) * 1996-07-01 1999-03-09 Sun Microsystems, Inc. Multiprocessing system configured to perform prefetch coherency activity with separate reissue queue for each processing subnode

Also Published As

Publication number Publication date
HK1035045A1 (en) 2001-11-09
GB2357867A (en) 2001-07-04
WO2000008564A8 (en) 2000-04-27
DE19983443T1 (de) 2001-07-26
GB2357867B (en) 2003-04-09
WO2000008564A1 (en) 2000-02-17
DE19983443B4 (de) 2007-07-19
US6112283A (en) 2000-08-29
GB0102431D0 (en) 2001-03-14
JP2002522827A (ja) 2002-07-23
AU5133799A (en) 2000-02-28

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